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2013-06-27drm/radeon: fix up ring functions for compute ringsAlex Deucher
The compute rings use RELEASE_MEM rather then EOP packets for writing fences and there is no SYNC_PFP_ME packet on the compute rings. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: switch to type3 nop packet for compute rings (v2)Alex Deucher
Type 2 packets are deprecated on CIK MEC and we should use type 3 nop packets. Setting the count field to the max value (0x3fff) indicates that only one dword should be skipped like a type 2 packet. v2: add comment to code Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon/cik: Add support for compute queues (v4)Alex Deucher
On CIK, the compute rings work slightly differently than on previous asics, however the basic concepts are the same. The main differences: - New MEC engines for compute queues - Multiple queues per MEC: - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues - KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues - Queues can be allocated and scheduled by another queue - New doorbell aperture allows you to assign space in the aperture for the wptr which allows for userspace access to queues v2: add wptr shadow, fix eop setup v3: fix comment v4: switch to new callback method Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon: implement simple doorbell page allocatorAlex Deucher
The doorbell aperture is a PCI BAR whose pages can be mapped to compute resources for things like wptrs for userspace queues. This patch maps the BAR and sets up a simple allocator to allocate pages from the BAR. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: use callbacks for ring pointer handling (v3)Alex Deucher
Add callbacks to the radeon_asic struct to handle rptr/wptr fetchs and wptr updates. We currently use one version for all rings, but this allows us to override with a ring specific versions. Needed for compute rings on CIK. v2: udpate as per Christian's comments v3: fix some rebase cruft Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: add srbm_select functionAlex Deucher
Allows us to select instanced registers based on: - ME (micro engine - Pipe - Queue - VMID Switch MC setup to use this new function. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add UVD support for CIK (v3)Christian König
v2: agd5f: fix clock dividers setup for bonaire v3: agd5f: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: update radeon_atom_get_clock_dividers for CIKAlex Deucher
CIK uses a slightly different variant of the table structs and params. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: update radeon_atom_get_clock_dividers() for SIAlex Deucher
SI uses v5 of the command table and uses a different table for memory PLLs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: add pcie_port indirect register accessorsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add get_xclk() callback for CIKAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add indirect register accessors for SMC registersAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: update CIK soft resetAlex Deucher
Update to the newer programming model. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add get_gpu_clock_counter() callback for cikAlex Deucher
Used for GPU clock counter snapshots. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: Update radeon_info_ioctl for CIK (v2)Alex Deucher
v2: rebase changes, fix a couple missed cases Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add SS override support for KB/KVAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: use frac fb div on DCE8Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: Handle PPLL0 powerdown on DCE8Alex Deucher
Only Bonaire has PPLL0. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add support pll selection for DCE8 (v4)Alex Deucher
v2: make PPLL0 is available for non-DP on CI v3: rebase changes, update documentation v4: fix kabini Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: update DISPCLK programming for DCE8Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/atom: add support for new DVO tablesAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/atom: add DCE8 encoder supportAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/dce8: crtc_set_base updatesAlex Deucher
Some new fields and DESKTOP_HEIGHT register moved. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/dce8: properly handle interlaced timingAlex Deucher
The register bits changed on DCE8 compared to previous families. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: add hw cursor support (v2)Alex Deucher
CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit v2: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/dce8: add support for display watermark setupAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: update power state parsing for CIAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: handle the integrated thermal controller on CIAlex Deucher
No support for reading the temperature yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: atombios power table updates (v2)Alex Deucher
v2: further updates Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: upstream atombios.h updates (v2)Alex Deucher
v2: further updates Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: upstream ObjectID.h updates (v2)Alex Deucher
v2: further updates Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: fill in startup/shutdown callbacks (v5)Alex Deucher
v2: update to latest driver changes v3: properly tear down vm on suspend v4: fix up irq init ordering v5: remove outdated comment Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-06-25drm/radeon/cik: add support for doing async VM pt updates (v5)Alex Deucher
Async page table updates using the sDMA engine. sDMA has a special packet for updating entries for contiguous pages that reduces overhead. v2: add support for and use the CP for now. v3: update for 2 level PTs v4: rebase, fix DMA packet v5: switch to using an IB Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: implement async vm_flush for the sDMA (v6)Alex Deucher
Update the page table base address and flush the VM TLB using the sDMA. V2: update for 2 level PTs V3: update vm flush V4: update SH_MEM* regs V5: switch back to old style VM TLB invalidate V6: fix packet formatting Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon/cik: add support for sDMA dma engines (v8)Alex Deucher
CIK has new asynchronous DMA engines called sDMA (system DMA). Each engine supports 1 ring buffer for kernel and gfx and 2 userspace queues for compute. TODO: fill in the compute setup. v2: update to the latest reset code v3: remove ib_parse v4: fix copy_dma() v5: drop WIP compute sDMA queues v6: rebase v7: endian fixes for IB v8: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon/cik: log and handle VM page fault interruptsAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: add support for interrupts on CIK (v5)Alex Deucher
Todo: - handle interrupts for compute queues v2: add documentation v3: update to latest reset code v4: update to latest illegal CP handling v5: fix missing break in interrupt handler switch statement Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: Add support for RLC init on CIK (v4)Alex Deucher
RLC handles the interrupt controller and other tasks on the GPU. v2: add documentation v3: update programming sequence v4: additional setup Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: implement async vm_flush for the CP (v7)Alex Deucher
Update the page table base address and flush the VM TLB using the CP. v2: update for 2 level PTs v3: use new packet for invalidate v4: update SH_MEM* regs when flushing the VM v5: add pfp sync, go back to old style vm TLB invalidate v6: fix hdp flush packet count v7: use old style HDP flush Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: add ring and IB tests for CIK (v3)Alex Deucher
v2: add documenation v3: update the latest ib changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: add IB and fence dispatch functions for CIK gfx (v7)Alex Deucher
For gfx ring only. Compute is still todo. v2: add documentation v3: update to latest reset changes, integrate emit update patch. v4: fix count on wait_reg_mem for HDP flush v5: use old hdp flush method for fence v6: set valid bit for IB v7: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: Add CP init for CIK (v7)Alex Deucher
Sets up the GFX ring and loads ucode for GFX and Compute. Todo: - handle compute queue setup. v2: add documentation v3: integrate with latest reset changes v4: additional init fixes v5: scratch reg write back no longer supported on CIK v6: properly set CP_RB0_BASE_HI v7: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: add support mc ucode loading on CIK (v2)Alex Deucher
Load the GDDR5 ucode and train the links. v2: update ucode Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: add initial ucode loading for CIK (v5)Alex Deucher
Currently the driver required 6 sets of ucode: 1. pfp - pre-fetch parser, part of the GFX CP 2. me - micro engine, part of the GFX CP 3. ce - constant engine, part of the GFX CP 4. rlc - interrupt, etc. controller 5. mc - memory controller (discrete cards only) 6. mec - compute engines, part of Compute CP V2: add documentation V3: update MC ucode V4: rebase V5: update mc ucode Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon/cik: stop page faults from hanging the system (v2)Alex Deucher
Redirect invalid memory accesses to the default page instead of locking up the memory controller. v2: rebase on top of 2 level PTs Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: add support for MC/VM setup on CIK (v6)Alex Deucher
The vm callbacks are the same as the SI ones right now (same regs and bits). We could share the SI variants, and I may yet do that, but I figured I would add CIK specific ones for now in case we need to change anything. V2: add documentation, minor fixes. V3: integrate vram offset fixes for APUs V4: enable 2 level VM PTs V5: index SH_MEM_* regs properly V6: add ib_parse() Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: Add support for CIK GPU reset (v2)Alex Deucher
v2: split soft reset into compute and gfx. Still need to make reset more fine grained, but this should be a start. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: add gpu init support for CIK (v9)Alex Deucher
v2: tiling fixes v3: more tiling fixes v4: more tiling fixes v5: additional register init v6: rebase v7: fix gb_addr_config for KV/KB v8: drop wip KV bits for now, add missing config reg v9: fix cu count on Bonaire Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: adapt to PCI BAR changes on CIKAlex Deucher
register BAR is now at PCI BAR 5. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon: add DCE8 macro for CIKAlex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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