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2014-11-15Merge tag 'drm/tegra/for-3.19-rc1' of ↵Dave Airlie
git://people.freedesktop.org/~tagr/linux into drm-next drm/tegra: Changes for v3.19-rc1 The highlights in this pull request are: * IOMMU support: The Tegra DRM driver can now deal with discontiguous buffers if an IOMMU exists in the system. That means it can allocate using drm_gem_get_pages() and will map them into IOVA space via the IOMMU API. Similarly, non-contiguous PRIME buffers can be imported from a different driver, which allows better integration with gk20a (nouveau) and less hacks. * Universal planes: This is precursory work for atomic modesetting and will allow hardware cursor support to be implemented on pre-Tegra114 where RGB cursors were not supported. * DSI ganged-mode support: The DSI controller can now gang up with a second DSI controller to drive high resolution DSI panels. Besides those bigger changes there is a slew of fixes, cleanups, plugged memory leaks and so on. * tag 'drm/tegra/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: (44 commits) drm/tegra: gem: Check before freeing CMA memory drm/tegra: fb: Add error codes to error messages drm/tegra: fb: Properly release GEM objects on failure drm/tegra: Detach panel when a connector is removed drm/tegra: Plug memory leak drm/tegra: gem: Use more consistent data types drm/tegra: fb: Do not destroy framebuffer drm/tegra: gem: dumb: pitch and size are outputs drm/tegra: Enable the hotplug interrupt only when necessary drm/tegra: dc: Universal plane support drm/tegra: dc: Registers are 32 bits wide drm/tegra: dc: Factor out DC, window and cursor commit drm/tegra: Add IOMMU support drm/tegra: Fix error handling cleanup drm/tegra: gem: Use dma_mmap_writecombine() drm/tegra: gem: Remove redundant drm_gem_free_mmap_offset() drm/tegra: gem: Cleanup tegra_bo_create_with_handle() drm/tegra: gem: Extract tegra_bo_alloc_object() drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier drm/tegra: dsi: Replace 1000000 by USEC_PER_SEC ...
2014-11-15Merge tag 'drm/fixes/for-3.19-rc1' of ↵Dave Airlie
git://people.freedesktop.org/~tagr/linux into drm-next drm: Miscellaneous fixes for v3.19-rc1 This is a small collection of fixes that I've been carrying around for a while now. Many of these have been posted and reviewed or acked. The few that haven't I deemed too trivial to bother. * tag 'drm/fixes/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: video/hdmi: Relicense header under MIT license drm/gma500: mdfld: Reuse video/mipi_display.h drm: Make drm_mode_create_tv_properties() signature consistent drm: Implement drm_get_pci_dev() dummy for !PCI drm/prime: Use unsigned type for number of pages drm/gem: Fix typo in kerneldoc drm: Use const data when creating blob properties drm: Use size_t for blob property sizes
2014-11-15Merge tag 'drm/panel/for-3.19-rc1' of ↵Dave Airlie
git://people.freedesktop.org/~tagr/linux into drm-next drm/panel: Changes for v3.19-rc1 This contains support for a couple of new panels, updates for some GPIO API changes and a bunch of updates to the MIPI DSI support that should make it easier to write panel drivers in the future. * tag 'drm/panel/for-3.19-rc1' of git://people.freedesktop.org/~tagr/linux: (31 commits) drm/panel: Add Sharp LQ101R1SX01 support drm/dsi: Do not require .owner field to be set drm/dsi: Resolve MIPI DSI device from phandle drm/dsi: Implement DCS set_{column,page}_address commands drm/dsi: Implement DCS {get,set}_pixel_format commands drm/dsi: Implement DCS get_power_mode command drm/dsi: Implement DCS soft_reset command drm/dsi: Implement DCS nop command drm/dsi: Add to DocBook documentation drm/dsi: Implement some standard DCS commands drm/dsi: Implement generic read and write commands drm/panel: s6e8aa0: Use standard MIPI DSI function drm/dsi: Add mipi_dsi_set_maximum_return_packet_size() helper drm/dsi: Constify mipi_dsi_msg drm/dsi: Make mipi_dsi_dcs_{read,write}() symmetrical drm/dsi: Add DSI transfer helper drm/dsi: Add message to packet translator drm/dsi: Introduce packet format helpers drm/panel: s6e8aa0: Fix build warnings on 64-bit drm/panel: ld9040: Fix build warnings on 64-bit ...
2014-11-15Merge tag 'drm-intel-next-2014-11-07-fixups' of ↵Dave Airlie
git://anongit.freedesktop.org/drm-intel into drm-next - skl watermarks code (Damien, Vandana, Pradeep) - reworked audio codec /eld handling code (Jani) - rework the mmio_flip code to use the vblank evade logic and wait for rendering using the standard wait_seqno interface (Ander) - skl forcewake support (Zhe Wang) - refactor the chv interrupt code to use functions shared with vlv (Ville) - prep work for different global gtt views (Tvrtko Ursulin) - precompute the display PLL config before touching hw state (Ander) - completely reworked panel power sequencer code for chv/vlv (Ville) - pre work to split the plane update code into a prepare and commit phase (Gustavo Padovan) - golden context for skl (Armin Reese) - as usual tons of fixes and improvements all over * tag 'drm-intel-next-2014-11-07-fixups' of git://anongit.freedesktop.org/drm-intel: (135 commits) drm/i915: Use correct pipe config to update pll dividers. V2 drm/i915: Plug memory leak in intel_shared_dpll_start_config() drm/i915: Update DRIVER_DATE to 20141107 drm/i915: Add gen to the gpu hang ecode drm/i915: Cache HPLL frequency on VLV/CHV Revert "drm/i915/vlv: Remove check for Old Ack during forcewake" drm/i915: Make mmio flip wait for seqno in the work function drm/i915: Make __wait_seqno non-static and rename to __i915_wait_seqno drm/i915: Move the .global_resources() hook call into modeset_update_crtc_power_domains() drm/i915/audio: add DOC comment describing HDA over HDMI/DP drm/i915: make pipe/port based audio valid accessors easier to use drm/i915/audio: add audio codec enable debug log for g4x drm/i915/audio: add audio codec disable on g4x drm/i915: enable audio codec after port drm/i915/audio: add vlv/chv/gen5-7 audio codec disable sequence drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence drm/i915/skl: Enable Gen9 RC6 drm/i915/skl: Gen9 Forcewake drm/i915/skl: Log the order in which we flush the pipes in the WM code drm/i915/skl: Flush the WM configuration ...
2014-11-15drm/dp/mst: Handle invalid link bandwidth from DPCD gracefullyChris Wilson
Don't BUG out if the link reports an invalid (or plain unknown) bandwidth value, but report the failure and fail gracefully. Fixes a trivial compiler warning in case the BUG is ever compiled away. Link: http://lkml.kernel.org/p/1415785566-12758-1-git-send-email-geert@linux-m68k.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Airlie <airlied@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15drm/atomic: rip out unnecessary locking checksRob Clark
For async commit, it is *intentional* that those locks are not held. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15drm: flip-work: change drm_flip_work_init prototypeBoris BREZILLON
Now that we're using lists instead of kfifo to store drm flip-work tasks we do not need the size parameter passed to drm_flip_work_init function anymore. Moreover this function cannot fail anymore, we can thus remove the return code. Modify drm_flip_work_init users to take account of these changes. [airlied: fixed two unused variable warnings] Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-15drm: rework flip-work helpers to avoid calling func when the FIFO is fullBoris BREZILLON
Make use of lists instead of kfifo in order to dynamically allocate task entry when someone require some delayed work, and thus preventing drm_flip_work_queue from directly calling func instead of queuing this call. This allow drm_flip_work_queue to be safely called even within irq handlers. Add new helper functions to allocate a flip work task and queue it when needed. This prevents allocating data within irq context (which might impact the time spent in the irq handler). Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-14drm/i915: Use correct pipe config to update pll dividers. V2Bob Paauwe
Use the new pipe config values to calculate the updated pll dividers. This regression was introduced in commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59 Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:33 2014 +0200 drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs and commit 00d958817dd3daaa452c221387ddaf23d1e4c06f Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Date: Wed Oct 29 11:32:36 2014 +0200 drm/i915: Covert remaining platforms to choose DPLLS before disabling CRTCs v2: Use intel_pipe_will_have_type() to look at new configuration - Ander Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> CC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-13drm/tegra: gem: Check before freeing CMA memoryThierry Reding
dma_free_writecombine() must not be called on a buffer that couldn't be allocated. Check for a valid virtual address before attempting to free the memory to avoid a crash. Reported-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: fb: Add error codes to error messagesThierry Reding
This helps in determining what errors happened at specifics points in the initialization sequence. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: fb: Properly release GEM objects on failureThierry Reding
When fbdev initialization fails, make sure to unreference the GEM objects properly. Note that we can't do this in the general error unwinding path because ownership of the GEM object references is transferred to the framebuffer upon creation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: Detach panel when a connector is removedThierry Reding
When the DRM device is torn down and the connector is removed, make sure to detach the panel to make sure there are no dangling pointers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: Plug memory leakThierry Reding
Free the DRM device-private memory upon driver unload to make sure the memory doesn't leak. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: gem: Use more consistent data typesThierry Reding
Use size_t consistently for sizes and u32/u64 instead of uint32_t and uint64_t. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: fb: Do not destroy framebufferThierry Reding
Drop a reference instead of directly calling the framebuffer .destroy() callback at fbdev free time. This is necessary to make sure the object isn't destroyed if anyone else still has a reference. Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: gem: dumb: pitch and size are outputsThierry Reding
When creating a dumb buffer object using the DRM_IOCTL_MODE_CREATE_DUMB IOCTL, only the width, height, bpp and flags parameters are inputs. The caller is not guaranteed to zero out or set handle, pitch and size, so the driver must not treat these values as possible inputs. Fixes a bug where running the Weston compositor on Tegra DRM would cause an attempt to allocate a 3 GiB framebuffer to be allocated. Fixes: de2ba664c30f ("gpu: host1x: drm: Add memory manager and fb") Cc: stable@vger.kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: Enable the hotplug interrupt only when necessaryThierry Reding
The hotplug handling needs access to the DRM device, which only appears at ->init() time. Disable interrupts up until that time. Similarly, when an output is removed, disable the hotplug interrupt again because the DRM device (and with it the hotplug infrastructure) is going away. Also make sure to only access the DRM device if it's available. Given the above change for the hotplug interrupt this should really never happen, but the extra check doesn't hurt either. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dc: Universal plane supportThierry Reding
This allows the primary plane and cursor to be exposed as regular DRM/KMS planes, which is a prerequisite for atomic modesetting and gives userspace more flexibility over controlling them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dc: Registers are 32 bits wideThierry Reding
Using an unsigned long type will cause these variables to become 64-bit on 64-bit SoCs. In practice this should always work, but there's no need for carrying around the additional 32 bits. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dc: Factor out DC, window and cursor commitThierry Reding
The sequence to commit changes to the DC, window or cursor configuration is repetitive and can be extracted into separate functions for ease of use. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: Add IOMMU supportThierry Reding
When an IOMMU device is available on the platform bus, allocate an IOMMU domain and attach the display controllers to it. The display controllers can then scan out non-contiguous buffers by mapping them through the IOMMU. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: Fix error handling cleanupThierry Reding
The DRM driver's ->load() implementation didn't do a good job (no job at all really) cleaning up on failure. Fix that by undoing any prior setup when an error occurs. This requires a bit of rework to make it possible to clean up fbdev midway. This was tested by injecting errors at various points during the initialization sequence and verifying that error cleanup didn't crash and no memory leaked (using kmemleak). Reported-by: Stéphane Marchesin <marcheu@chromium.org> Reported-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: gem: Use dma_mmap_writecombine()Thierry Reding
Use the existing API rather than open-coding equivalent functionality in the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: gem: Remove redundant drm_gem_free_mmap_offset()Thierry Reding
The drm_gem_object_release() function already performs this cleanup, so there is no reason to do it explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: gem: Cleanup tegra_bo_create_with_handle()Thierry Reding
There is only a single location where the function needs to do cleanup. Skip the error unwinding path and call the cleanup function directly instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: gem: Extract tegra_bo_alloc_object()Thierry Reding
This function implements the common buffer object allocation used for both allocation and import paths. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlierSean Paul
Make sure the DSI PHY_TIMING and BTA_TIMING registers are initialized when the clocks are set up as opposed to when the output is enabled. This makes sure that the PHY timings are properly set up when the panel is prepared and that DCS commands sent at that time use the appropriate timings. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Replace 1000000 by USEC_PER_SECThierry Reding
Using the symbolic constant instantly provides a lot more context. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Replace 1000000000UL by NSEC_PER_SECThierry Reding
Using the symbolic constant instantly provides a lot more context. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Implement host transfersThierry Reding
Add support for sending MIPI DSI command packets from the host to a peripheral. This is required for panels that need configuration before they accept video data. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Add ganged mode supportThierry Reding
Implement ganged mode support for the Tegra DSI driver. The DSI host controller to gang up with is specified via a phandle in the device tree and the resolved DSI host controller used for the programming of the ganged-mode registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Split out tegra_dsi_set_timeout()Thierry Reding
In preparation for adding ganged-mode support, this commit splits out the tegra_dsi_set_timeout() function so that it can be reused for the slave DSI controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Add command mode supportThierry Reding
Add support for DC-driven command mode. This is a mode where the video stream sent by the display controller is packed into DCS command packets (write_memory_start and write_memory_continue) by the DSI controller. It can be used for panels with a remote framebuffer and is useful to save power when used with a dynamic refresh rate (not yet supported by the driver). Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Refactor in preparation for command modeThierry Reding
For command mode panels, the DSI controller needs to be enabled and configured so that panel drivers can send commands prior to the video stream being enabled. Move code from the monolithic output enable/disable functions into smaller, reusable units to allow more fine-grained control over the controller state. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Properly cleanup on probe failureThierry Reding
The driver wasn't even attempting to do any cleanup when probing failed. Fix this by releasing any resources acquired up to the point of failure and putting the device back into the original state (reset, clocks off). Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Mark connector hotpluggableThierry Reding
DSI panels can always be hotplugged via the DSI bus' attach/detach infrastructure, so unconditionally mark the connector hotpluggable. While at it, also make sure that when a panel is detached the connector is marked unconnected before calling into the DRM hotplug helpers to reflect the correct state. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Leave parent clock aloneThierry Reding
The common clock framework will take care of preparing and enabling the parent of the DSI clock automatically. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Do not manage clock on enable/disableThierry Reding
In preparation for supporting command mode panels, don't disable the clock when the output is disabled. The output will be enabled only after the panel has been programmed in command mode, so the clock must always remain on. As a side-effect, pad calibration now only needs to be done at driver probe time, since neither power nor controller state will go away before driver removal. While at it, use a 32-bit variable to store register content because the registers are 32-bit even on 64-bit Tegra. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dsi: Make FIFO depths host parametersThierry Reding
Rather than hardcoding them as macros, make the host and video FIFO depths parameters so that they can be more easily adjusted if a new generation of the Tegra SoC changes them. While at it, set the depth of the video FIFO to the correct value of 1920 *words* rather than *bytes*. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: DPMS off/on in encoder prepare/commitSean Paul
Previously the panel and output were only enabled on encoder->dpms(). If userspace called dpms on before doing a modeset, the driver would get into a state where the connector had a dpms state of ON, but the encoder and output were not enabled (because the encoder is not yet attached to the connector). Subsequent dpms ON calls are ignored b/c the connector's state already matches the desired state. This patch enables/disables the panel and output on modeset as well, so we can catch the above case. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: Do not enable output on .mode_set()Thierry Reding
The output is already enabled in .dpms(), doing it in .mode_set() too can cause noticeable flicker. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13drm/tegra: dc: Add powergate supportThierry Reding
Both display controllers are in their own power partition. Currently the driver relies on the assumption that these partitions are on (which is the hardware default). However some bootloaders may disable them, so the driver must make sure to turn them back on to avoid hangs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 registerSean Paul
During calibration, sets the "internal reference level for drive pull- down" to the value specified in the Tegra TRM. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13gpu: host1x: mipi: Calibrate clock lanesSean Paul
Include the clock lanes when calibrating the MIPI PHY on Tegra124 compatible devices. Signed-off-by: Sean Paul <seanpaul@chromium.org> [treding@nvidia.com: bikeshedding] Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRLSean Paul
By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE ("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states that if the value of the prescale is 0 (or 0.1us), the filter should be set between 2-5. However, the current code sets it to 0. For now, let's keep the prescale and filter values as-is, which is most likely the power-on-reset values of 0x2 and 0xa, respectively. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13gpu: host1x: mipi: Registers are 32 bits wideThierry Reding
On 64-bit platforms an unsigned long would be 64 bit and cause unnecessary casting when being passed to writel() or returned from readl(). Make register values 32 bits wide to avoid that. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13gpu: host1x: Make gather offsets unsignedThierry Reding
Use the u32 type for the offset in the host1x_job_gather structure for consistentcy with other structures. Negative offsets don't make sense in this context. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13gpu: host1x: Print address/offset pairs consistentlyThierry Reding
Consistently use a format of %pad+%#x to print address/offset in debug messages. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13gpu: host1x: Fix typo in commentThierry Reding
Signed-off-by: Thierry Reding <treding@nvidia.com>
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