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-rw-r--r--include/asm-blackfin/.gitignore1
-rw-r--r--include/asm-blackfin/bfin-global.h10
-rw-r--r--include/asm-blackfin/bug.h13
-rw-r--r--include/asm-blackfin/cplb.h26
-rw-r--r--include/asm-blackfin/dma-mapping.h15
-rw-r--r--include/asm-blackfin/dma.h4
-rw-r--r--include/asm-blackfin/gptimers.h150
-rw-r--r--include/asm-blackfin/ide.h4
-rw-r--r--include/asm-blackfin/mach-bf527/anomaly.h80
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf527/bfin_sir.h133
-rw-r--r--include/asm-blackfin/mach-bf527/blackfin.h15
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h90
-rw-r--r--include/asm-blackfin/mach-bf527/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf533/anomaly.h10
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_serial_5xx.h50
-rw-r--r--include/asm-blackfin/mach-bf533/bfin_sir.h120
-rw-r--r--include/asm-blackfin/mach-bf533/blackfin.h15
-rw-r--r--include/asm-blackfin/mach-bf533/cdefBF532.h31
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h29
-rw-r--r--include/asm-blackfin/mach-bf533/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf533/mem_init.h10
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h17
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf537/bfin_sir.h133
-rw-r--r--include/asm-blackfin/mach-bf537/blackfin.h39
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF534.h65
-rw-r--r--include/asm-blackfin/mach-bf537/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h1
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h48
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_sir.h149
-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h38
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF542.h12
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF544.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF547.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF548.h33
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF549.h35
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h418
-rw-r--r--include/asm-blackfin/mach-bf548/dma.h2
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h20
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h6
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_serial_5xx.h50
-rw-r--r--include/asm-blackfin/mach-bf561/bfin_sir.h120
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h14
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h34
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h31
-rw-r--r--include/asm-blackfin/mach-bf561/dma.h3
-rw-r--r--include/asm-blackfin/portmux.h4
-rw-r--r--include/asm-blackfin/processor.h5
-rw-r--r--include/asm-blackfin/semaphore-helper.h82
-rw-r--r--include/asm-blackfin/semaphore.h106
-rw-r--r--include/asm-blackfin/signal.h2
-rw-r--r--include/asm-blackfin/thread_info.h11
-rw-r--r--include/asm-blackfin/time.h36
-rw-r--r--include/asm-blackfin/timex.h17
-rw-r--r--include/asm-blackfin/trace.h4
-rw-r--r--include/asm-blackfin/uaccess.h4
-rw-r--r--include/asm-blackfin/unistd.h26
58 files changed, 1594 insertions, 948 deletions
diff --git a/include/asm-blackfin/.gitignore b/include/asm-blackfin/.gitignore
new file mode 100644
index 000000000000..7858564a4466
--- /dev/null
+++ b/include/asm-blackfin/.gitignore
@@ -0,0 +1 @@
++mach
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 5dba3a735596..716df7c85923 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -112,20 +112,10 @@ extern void init_leds(void);
extern const char bfin_board_name[];
extern unsigned long wall_jiffies;
-extern unsigned long ipdt_table[];
-extern unsigned long dpdt_table[];
-extern unsigned long icplb_table[];
-extern unsigned long dcplb_table[];
-
-extern unsigned long ipdt_swapcount_table[];
-extern unsigned long dpdt_swapcount_table[];
-
-extern unsigned long table_start, table_end;
extern unsigned long bfin_sic_iwr[];
extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
extern struct file_operations dpmc_fops;
-extern char _start;
extern unsigned long _ramstart, _ramend, _rambase;
extern unsigned long memory_start, memory_end, physical_mem_end;
extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
diff --git a/include/asm-blackfin/bug.h b/include/asm-blackfin/bug.h
index 41e53b29f167..6d3e11b1fc57 100644
--- a/include/asm-blackfin/bug.h
+++ b/include/asm-blackfin/bug.h
@@ -1,4 +1,17 @@
#ifndef _BLACKFIN_BUG_H
#define _BLACKFIN_BUG_H
+
+#ifdef CONFIG_BUG
+#define HAVE_ARCH_BUG
+
+#define BUG() do { \
+ dump_bfin_trace_buffer(); \
+ printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
+ panic("BUG!"); \
+} while (0)
+
+#endif
+
#include <asm-generic/bug.h>
+
#endif
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 654375c2b746..5b0da9a69b67 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -74,32 +74,6 @@
#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
-/*
-* Number of required data CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 16 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Data Memory
-* possibly 1 for L2 Data Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-* 1 for ASYNC Memory
-*/
-
-
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
- + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
-
-/*
-* Number of required instruction CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 12 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Instruction Memory
-* possibly 1 for L2 Instruction Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-*/
-
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
-
-
#define CPLB_ENABLE_ICACHE_P 0
#define CPLB_ENABLE_DCACHE_P 1
#define CPLB_ENABLE_DCACHE2_P 2
diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h
index 282fabccf6a6..1a13c2fc3667 100644
--- a/include/asm-blackfin/dma-mapping.h
+++ b/include/asm-blackfin/dma-mapping.h
@@ -27,6 +27,14 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
enum dma_data_direction direction);
+static inline dma_addr_t
+dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction dir)
+{
+ return dma_map_single(dev, page_address(page) + offset, size, dir);
+}
+
/*
* Unmap a single streaming mode DMA translation. The dma_addr and size
* must match what was provided for in a previous pci_map_single call. All
@@ -38,6 +46,13 @@ extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
enum dma_data_direction direction);
+static inline void
+dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
+ enum dma_data_direction dir)
+{
+ dma_unmap_single(dev, dma_addr, size, dir);
+}
+
/*
* Map a set of buffers described by scatterlist in streaming
* mode for DMA. This is the scather-gather version of the
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index 5abaa2cee8db..c0d5259e315b 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -33,7 +33,6 @@
#include <linux/slab.h>
#include <asm/irq.h>
#include <asm/signal.h>
-#include <asm/semaphore.h>
#include <linux/kernel.h>
#include <asm/mach/dma.h>
@@ -192,4 +191,7 @@ void clear_dma_irqstat(unsigned int channel);
void *dma_memcpy(void *dest, const void *src, size_t count);
void *safe_dma_memcpy(void *dest, const void *src, size_t count);
+extern int channel2irq(unsigned int channel);
+extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL];
+
#endif
diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h
index 4f318f1fd2d9..0520d2aac8f3 100644
--- a/include/asm-blackfin/gptimers.h
+++ b/include/asm-blackfin/gptimers.h
@@ -22,6 +22,18 @@
# define TIMER0_GROUP_REG TIMER_ENABLE
#endif
/*
+ * BF54x: 11 timers (BF542: 8 timers):
+ */
+#if defined(BF548_FAMILY)
+# ifdef CONFIG_BF542
+# define MAX_BLACKFIN_GPTIMERS 8
+# else
+# define MAX_BLACKFIN_GPTIMERS 11
+# define TIMER8_GROUP_REG TIMER_ENABLE1
+# endif
+# define TIMER0_GROUP_REG TIMER_ENABLE0
+#endif
+/*
* BF561: 12 timers:
*/
#if defined(CONFIG_BF561)
@@ -44,40 +56,28 @@
#define TIMER0bit 0x0001 /* 0001b */
#define TIMER1bit 0x0002 /* 0010b */
#define TIMER2bit 0x0004 /* 0100b */
-
-#if (MAX_BLACKFIN_GPTIMERS > 3)
-# define TIMER3bit 0x0008
-# define TIMER4bit 0x0010
-# define TIMER5bit 0x0020
-# define TIMER6bit 0x0040
-# define TIMER7bit 0x0080
-#endif
-
-#if (MAX_BLACKFIN_GPTIMERS > 8)
-# define TIMER8bit 0x0100
-# define TIMER9bit 0x0200
-# define TIMER10bit 0x0400
-# define TIMER11bit 0x0800
-#endif
+#define TIMER3bit 0x0008
+#define TIMER4bit 0x0010
+#define TIMER5bit 0x0020
+#define TIMER6bit 0x0040
+#define TIMER7bit 0x0080
+#define TIMER8bit 0x0100
+#define TIMER9bit 0x0200
+#define TIMER10bit 0x0400
+#define TIMER11bit 0x0800
#define TIMER0_id 0
#define TIMER1_id 1
#define TIMER2_id 2
-
-#if (MAX_BLACKFIN_GPTIMERS > 3)
-# define TIMER3_id 3
-# define TIMER4_id 4
-# define TIMER5_id 5
-# define TIMER6_id 6
-# define TIMER7_id 7
-#endif
-
-#if (MAX_BLACKFIN_GPTIMERS > 8)
-# define TIMER8_id 8
-# define TIMER9_id 9
-# define TIMER10_id 10
-# define TIMER11_id 11
-#endif
+#define TIMER3_id 3
+#define TIMER4_id 4
+#define TIMER5_id 5
+#define TIMER6_id 6
+#define TIMER7_id 7
+#define TIMER8_id 8
+#define TIMER9_id 9
+#define TIMER10_id 10
+#define TIMER11_id 11
/* associated timers for ppi framesync: */
@@ -124,45 +124,31 @@
/*
* Timer Status Register Bits
*/
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#if (MAX_BLACKFIN_GPTIMERS > 3)
-# define TIMER_STATUS_TIMIL3 0x00000008
-# define TIMER_STATUS_TIMIL4 0x00010000
-# define TIMER_STATUS_TIMIL5 0x00020000
-# define TIMER_STATUS_TIMIL6 0x00040000
-# define TIMER_STATUS_TIMIL7 0x00080000
-# if (MAX_BLACKFIN_GPTIMERS > 8)
-# define TIMER_STATUS_TIMIL8 0x0001
-# define TIMER_STATUS_TIMIL9 0x0002
-# define TIMER_STATUS_TIMIL10 0x0004
-# define TIMER_STATUS_TIMIL11 0x0008
-# endif
-# define TIMER_STATUS_INTR 0x000F000F
-#else
-# define TIMER_STATUS_INTR 0x0007 /* any timer interrupt */
-#endif
-
-#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0020
-#define TIMER_STATUS_TOVF2 0x0040
-#if (MAX_BLACKFIN_GPTIMERS > 3)
-# define TIMER_STATUS_TOVF3 0x00000080
-# define TIMER_STATUS_TOVF4 0x00100000
-# define TIMER_STATUS_TOVF5 0x00200000
-# define TIMER_STATUS_TOVF6 0x00400000
-# define TIMER_STATUS_TOVF7 0x00800000
-# if (MAX_BLACKFIN_GPTIMERS > 8)
-# define TIMER_STATUS_TOVF8 0x0010
-# define TIMER_STATUS_TOVF9 0x0020
-# define TIMER_STATUS_TOVF10 0x0040
-# define TIMER_STATUS_TOVF11 0x0080
-# endif
-# define TIMER_STATUS_OFLOW 0x00F000F0
-#else
-# define TIMER_STATUS_OFLOW 0x0070 /* any timer overflow */
-#endif
+#define TIMER_STATUS_TIMIL0 0x0001
+#define TIMER_STATUS_TIMIL1 0x0002
+#define TIMER_STATUS_TIMIL2 0x0004
+#define TIMER_STATUS_TIMIL3 0x00000008
+#define TIMER_STATUS_TIMIL4 0x00010000
+#define TIMER_STATUS_TIMIL5 0x00020000
+#define TIMER_STATUS_TIMIL6 0x00040000
+#define TIMER_STATUS_TIMIL7 0x00080000
+#define TIMER_STATUS_TIMIL8 0x0001
+#define TIMER_STATUS_TIMIL9 0x0002
+#define TIMER_STATUS_TIMIL10 0x0004
+#define TIMER_STATUS_TIMIL11 0x0008
+
+#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
+#define TIMER_STATUS_TOVF1 0x0020
+#define TIMER_STATUS_TOVF2 0x0040
+#define TIMER_STATUS_TOVF3 0x00000080
+#define TIMER_STATUS_TOVF4 0x00100000
+#define TIMER_STATUS_TOVF5 0x00200000
+#define TIMER_STATUS_TOVF6 0x00400000
+#define TIMER_STATUS_TOVF7 0x00800000
+#define TIMER_STATUS_TOVF8 0x0010
+#define TIMER_STATUS_TOVF9 0x0020
+#define TIMER_STATUS_TOVF10 0x0040
+#define TIMER_STATUS_TOVF11 0x0080
/*
* Timer Slave Enable Status : write 1 to clear
@@ -170,22 +156,16 @@
#define TIMER_STATUS_TRUN0 0x1000
#define TIMER_STATUS_TRUN1 0x2000
#define TIMER_STATUS_TRUN2 0x4000
-#if (MAX_BLACKFIN_GPTIMERS > 3)
-# define TIMER_STATUS_TRUN3 0x00008000
-# define TIMER_STATUS_TRUN4 0x10000000
-# define TIMER_STATUS_TRUN5 0x20000000
-# define TIMER_STATUS_TRUN6 0x40000000
-# define TIMER_STATUS_TRUN7 0x80000000
-# define TIMER_STATUS_TRUN 0xF000F000
-# if (MAX_BLACKFIN_GPTIMERS > 8)
-# define TIMER_STATUS_TRUN8 0x1000
-# define TIMER_STATUS_TRUN9 0x2000
-# define TIMER_STATUS_TRUN10 0x4000
-# define TIMER_STATUS_TRUN11 0x8000
-# endif
-#else
-# define TIMER_STATUS_TRUN 0x7000
-#endif
+#define TIMER_STATUS_TRUN3 0x00008000
+#define TIMER_STATUS_TRUN4 0x10000000
+#define TIMER_STATUS_TRUN5 0x20000000
+#define TIMER_STATUS_TRUN6 0x40000000
+#define TIMER_STATUS_TRUN7 0x80000000
+#define TIMER_STATUS_TRUN 0xF000F000
+#define TIMER_STATUS_TRUN8 0x1000
+#define TIMER_STATUS_TRUN9 0x2000
+#define TIMER_STATUS_TRUN10 0x4000
+#define TIMER_STATUS_TRUN11 0x8000
/* The actual gptimer API */
diff --git a/include/asm-blackfin/ide.h b/include/asm-blackfin/ide.h
index 121e272581d6..5b88de115bf4 100644
--- a/include/asm-blackfin/ide.h
+++ b/include/asm-blackfin/ide.h
@@ -19,10 +19,6 @@
#define MAX_HWIFS 1
-/* Legacy ... BLK_DEV_IDECS */
-#define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */
-
-
#include <asm-generic/ide_iops.h>
/****************************************************************************/
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
index a89120445be6..735fa02fafb2 100644
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -2,12 +2,12 @@
* File: include/asm-blackfin/mach-bf527/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
- * - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
+ * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -15,35 +15,85 @@
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
#define ANOMALY_05000337 (1)
-/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
+/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
+#define ANOMALY_05000341 (1)
+/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
#define ANOMALY_05000342 (1)
-/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (1)
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (1)
+/* Security Features Are Not Functional */
+#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (1)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* New Feature: Higher Default CCLK Rate */
+#define ANOMALY_05000368 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
+/* Authentication Fails To Initiate */
+#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
+/* Data Read From L3 Memory by USB DMA May be Corrupted */
+#define ANOMALY_05000380 (1)
+/* USB Full-speed Mode not Fully Tested */
+#define ANOMALY_05000381 (1)
+/* New Feature: Boot from OTP Memory */
+#define ANOMALY_05000385 (1)
+/* New Feature: bfrom_SysControl() Routine */
+#define ANOMALY_05000386 (1)
+/* New Feature: Programmable Preboot Settings */
+#define ANOMALY_05000387 (1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (1)
+/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (1)
+/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (1)
+/* New Feature: Log Buffer Functionality */
+#define ANOMALY_05000394 (1)
+/* New Feature: Hook Routine Functionality */
+#define ANOMALY_05000395 (1)
+/* New Feature: Header Indirect Bit */
+#define ANOMALY_05000396 (1)
+/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
+#define ANOMALY_05000397 (1)
+/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
+#define ANOMALY_05000398 (1)
+/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
+#define ANOMALY_05000399 (1)
+/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
+#define ANOMALY_05000401 (1)
/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000198 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000158 (0)
-#define ANOMALY_05000273 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
-#define ANOMALY_05000230 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000363 (0)
+
#endif
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index c0694ecd2ecd..f0ab2736a680 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
+/*
+ * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 2
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h
new file mode 100644
index 000000000000..0612d0c9501c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/bfin_sir.h
@@ -0,0 +1,133 @@
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART0_RX,
+ CH_UART0_RX,
+ CH_UART0_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ 0xFFC02000,
+ IRQ_UART1_RX,
+ CH_UART1_RX,
+ CH_UART1_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
+{
+ unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
+ port->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | port->lsr;
+}
+
+static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
+{
+ port->lsr = 0;
+ bfin_read16(port->membase + OFFSET_LSR);
+}
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR1
+ peripheral_request(P_UART1_TX, DRIVER_NAME);
+ peripheral_request(P_UART1_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h
index 1bd07e30781c..2891727b6176 100644
--- a/include/asm-blackfin/mach-bf527/blackfin.h
+++ b/include/asm-blackfin/mach-bf527/blackfin.h
@@ -64,6 +64,21 @@
#define STATUS_P1 0x02
#define STATUS_P0 0x01
+#define BFIN_UART_NR_PORTS 2
+
+#define OFFSET_THR 0x00 /* Transmit Holding register */
+#define OFFSET_RBR 0x00 /* Receive Buffer register */
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_IER 0x04 /* Interrupt Enable Register */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_GCTL 0x24 /* Global Control Register */
+
/* DPMC*/
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 3f4de5d9d4cb..9dbdbec8ea1b 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -29,18 +29,71 @@
*/
#ifndef _CDEF_BF52X_H
+#define _CDEF_BF52X_H
+
+#include <asm/system.h>
+#include <asm/blackfin.h>
#include "defBF52x_base.h"
+/* Include core specific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
/* ==== begin from cdefBF534.h ==== */
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+ unsigned long flags, iwr0, iwr1;
+
+ if (val == bfin_read_PLL_CTL())
+ return;
+
+ local_irq_save(flags);
+ /* Enable the PLL Wakeup bit in SIC IWR */
+ iwr0 = bfin_read32(SIC_IWR0);
+ iwr1 = bfin_read32(SIC_IWR1);
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+ bfin_write32(SIC_IWR1, 0);
+
+ bfin_write16(PLL_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+ bfin_write32(SIC_IWR0, iwr0);
+ bfin_write32(SIC_IWR1, iwr1);
+ local_irq_restore(flags);
+}
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+ unsigned long flags, iwr0, iwr1;
+
+ if (val == bfin_read_VR_CTL())
+ return;
+
+ local_irq_save(flags);
+ /* Enable the PLL Wakeup bit in SIC IWR */
+ iwr0 = bfin_read32(SIC_IWR0);
+ iwr1 = bfin_read32(SIC_IWR1);
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+ bfin_write32(SIC_IWR1, 0);
+
+ bfin_write16(VR_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+ bfin_write32(SIC_IWR0, iwr0);
+ bfin_write32(SIC_IWR1, iwr1);
+ local_irq_restore(flags);
+}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -873,39 +926,6 @@
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-
/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
index 2dfee12864f6..49dd693223e8 100644
--- a/include/asm-blackfin/mach-bf527/dma.h
+++ b/include/asm-blackfin/mach-bf527/dma.h
@@ -59,7 +59,4 @@
#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
#endif
-extern int channel2irq(unsigned int channel);
-extern struct dma_register *base_addr[];
-
#endif
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index 98209d40abba..5a6dcc5fa36c 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -7,7 +7,7 @@
*/
/* This file shoule be up to date with:
- * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -251,10 +251,18 @@
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
+/* PPI Does Not Start Properly In Specific Mode */
+#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index b6f513bee56e..fbe88dee3e2d 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
+/*
+ * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 1
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
@@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
#define DRIVER_NAME "bfin-uart"
-int nr_ports = NR_PORTS;
+int nr_ports = BFIN_UART_NR_PORTS;
static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{
diff --git a/include/asm-blackfin/mach-bf533/bfin_sir.h b/include/asm-blackfin/mach-bf533/bfin_sir.h
new file mode 100644
index 000000000000..cefcf8bb505b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bfin_sir.h
@@ -0,0 +1,120 @@
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART_RX,
+ CH_UART_RX,
+ CH_UART_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
+{
+ unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
+ port->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | port->lsr;
+}
+
+static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
+{
+ port->lsr = 0;
+ bfin_read16(port->membase + OFFSET_LSR);
+}
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
index f3b240abf170..d80971b4e3aa 100644
--- a/include/asm-blackfin/mach-bf533/blackfin.h
+++ b/include/asm-blackfin/mach-bf533/blackfin.h
@@ -42,4 +42,19 @@
#include "cdefBF532.h"
#endif
+#define BFIN_UART_NR_PORTS 1
+
+#define OFFSET_THR 0x00 /* Transmit Holding register */
+#define OFFSET_RBR 0x00 /* Receive Buffer register */
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_IER 0x04 /* Interrupt Enable Register */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_GCTL 0x24 /* Global Control Register */
+
#endif /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
index c803e14b529c..154655452d4c 100644
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -43,7 +43,27 @@
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+ unsigned long flags, iwr;
+
+ if (val == bfin_read_PLL_CTL())
+ return;
+
+ local_irq_save(flags);
+ /* Enable the PLL Wakeup bit in SIC IWR */
+ iwr = bfin_read32(SIC_IWR);
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+ bfin_write16(PLL_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+ bfin_write32(SIC_IWR, iwr);
+ local_irq_restore(flags);
+}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -57,6 +77,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
+ if (val == bfin_read_VR_CTL())
+ return;
+
+ local_irq_save(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
@@ -64,11 +88,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write16(VR_CTL, val);
SSYNC();
-
- local_irq_save(flags);
asm("IDLE;");
- local_irq_restore(flags);
+
bfin_write32(SIC_IWR, iwr);
+ local_irq_restore(flags);
}
/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 37134aaf9954..17e1548cec08 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -88,20 +88,25 @@
#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR 0xFFC00400 /* Transmit Holding register */
-#define UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART_LCR 0xFFC0040C /* Line Control Register */
-#define UART_MCR 0xFFC00410 /* Modem Control Register */
-#define UART_LSR 0xFFC00414 /* Line Status Register */
+
+/*
+ * Because include/linux/serial_reg.h have defined UART_*,
+ * So we define blackfin uart regs to BFIN_UART_*.
+ */
+#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
+#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
+#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
+#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
+#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
+#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
#if 0
-#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
+#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
#endif
-#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART_GCTL 0xFFC00424 /* Global Control Register */
+#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
+#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
index 16c672c01d80..bd9d5e94307d 100644
--- a/include/asm-blackfin/mach-bf533/dma.h
+++ b/include/asm-blackfin/mach-bf533/dma.h
@@ -51,7 +51,4 @@
#define CH_MEM_STREAM1_DEST 10 /* TX */
#define CH_MEM_STREAM1_SRC 11 /* RX */
-extern int channel2irq(unsigned int channel);
-extern struct dma_register *base_addr[];
-
#endif
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
index 1620dae5254d..f8f31901fca9 100644
--- a/include/asm-blackfin/mach-bf533/mem_init.h
+++ b/include/asm-blackfin/mach-bf533/mem_init.h
@@ -29,7 +29,8 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD)
+#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
+ CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
#if (CONFIG_SCLK_HZ > 119402985)
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
@@ -118,6 +119,13 @@
#define SDRAM_CL CL_3
#endif
+#if (CONFIG_MEM_MT48LC32M16A2TG_75)
+ /*SDRAM INFORMATION: */
+#define SDRAM_Tref 64 /* Refresh period in milliseconds */
+#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
+#define SDRAM_CL CL_3
+#endif
+
#if (CONFIG_MEM_GENERIC_BOARD)
/*SDRAM INFORMATION: Modify this for your board */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 746a794b3119..a6b08facb242 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -7,7 +7,7 @@
*/
/* This file shoule be up to date with:
- * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -132,10 +132,24 @@
#define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
+/* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */
+#define ANOMALY_05000350 (__SILICON_REVISION__ < 3)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000359 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ >= 3)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+
+
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
@@ -146,5 +160,6 @@
#define ANOMALY_05000266 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
+#define ANOMALY_05000363 (0)
#endif
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index 8fc672d31057..fd100a415b98 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
+/*
+ * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver header files
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 2
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -92,7 +108,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h
new file mode 100644
index 000000000000..0612d0c9501c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bfin_sir.h
@@ -0,0 +1,133 @@
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART0_RX,
+ CH_UART0_RX,
+ CH_UART0_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ 0xFFC02000,
+ IRQ_UART1_RX,
+ CH_UART1_RX,
+ CH_UART1_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
+{
+ unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
+ port->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | port->lsr;
+}
+
+static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
+{
+ port->lsr = 0;
+ bfin_read16(port->membase + OFFSET_LSR);
+}
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR1
+ peripheral_request(P_UART1_TX, DRIVER_NAME);
+ peripheral_request(P_UART1_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
index 53fcfa3408d0..cffc786b2a2b 100644
--- a/include/asm-blackfin/mach-bf537/blackfin.h
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -82,8 +82,6 @@
#define STATUS_P1 0x02
#define STATUS_P0 0x01
-/* UART 0*/
-
/* DMA Channnel */
#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
@@ -106,37 +104,52 @@
/* MMR Registers*/
#define bfin_read_UART_THR() bfin_read_UART0_THR()
#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
-#define UART_THR UART0_THR
+#define BFIN_UART_THR UART0_THR
#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
-#define UART_RBR UART0_RBR
+#define BFIN_UART_RBR UART0_RBR
#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
-#define UART_DLL UART0_DLL
+#define BFIN_UART_DLL UART0_DLL
#define bfin_read_UART_IER() bfin_read_UART0_IER()
#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
-#define UART_IER UART0_IER
+#define BFIN_UART_IER UART0_IER
#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
-#define UART_DLH UART0_DLH
+#define BFIN_UART_DLH UART0_DLH
#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
-#define UART_IIR UART0_IIR
+#define BFIN_UART_IIR UART0_IIR
#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
-#define UART_LCR UART0_LCR
+#define BFIN_UART_LCR UART0_LCR
#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
-#define UART_MCR UART0_MCR
+#define BFIN_UART_MCR UART0_MCR
#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
-#define UART_LSR UART0_LSR
+#define BFIN_UART_LSR UART0_LSR
#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
-#define UART_SCR UART0_SCR
+#define BFIN_UART_SCR UART0_SCR
#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
-#define UART_GCTL UART0_GCTL
+#define BFIN_UART_GCTL UART0_GCTL
+
+#define BFIN_UART_NR_PORTS 2
+
+#define OFFSET_THR 0x00 /* Transmit Holding register */
+#define OFFSET_RBR 0x00 /* Receive Buffer register */
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_IER 0x04 /* Interrupt Enable Register */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_GCTL 0x24 /* Global Control Register */
/* DPMC*/
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index 78227bc855df..82de526f8097 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -44,7 +44,27 @@
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+ unsigned long flags, iwr;
+
+ if (val == bfin_read_PLL_CTL())
+ return;
+
+ local_irq_save(flags);
+ /* Enable the PLL Wakeup bit in SIC IWR */
+ iwr = bfin_read32(SIC_IWR);
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+ bfin_write16(PLL_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+ bfin_write32(SIC_IWR, iwr);
+ local_irq_restore(flags);
+}
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -53,6 +73,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr;
+ if (val == bfin_read_VR_CTL())
+ return;
+
+ local_irq_save(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr = bfin_read32(SIC_IWR);
/* Only allow PPL Wakeup) */
@@ -60,11 +84,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write16(VR_CTL, val);
SSYNC();
-
- local_irq_save(flags);
asm("IDLE;");
- local_irq_restore(flags);
+
bfin_write32(SIC_IWR, iwr);
+ local_irq_restore(flags);
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
@@ -858,39 +881,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
-#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
index 021991984e6e..7a964040870a 100644
--- a/include/asm-blackfin/mach-bf537/dma.h
+++ b/include/asm-blackfin/mach-bf537/dma.h
@@ -52,7 +52,4 @@
#define CH_MEM_STREAM1_DEST 14 /* TX */
#define CH_MEM_STREAM1_SRC 15 /* RX */
-extern int channel2irq(unsigned int channel);
-extern struct dma_register *base_addr[];
-
#endif
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index 850dc12eb7f2..49d3cebc5293 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -93,5 +93,6 @@
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
+#define ANOMALY_05000363 (0)
#endif
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 7e6339f62a50..6547027cd3e6 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
+/*
+ * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 4
-
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_GCTL 0x08 /* Global Control Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
-#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
-#define OFFSET_THR 0x28 /* Transmit Holding register */
-#define OFFSET_RBR 0x2C /* Receive Buffer register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
@@ -80,7 +96,7 @@ struct bfin_serial_port {
#endif
};
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h
new file mode 100644
index 000000000000..5e94271c7e3b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bfin_sir.h
@@ -0,0 +1,149 @@
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
+#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART0_RX,
+ CH_UART0_RX,
+ CH_UART0_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ 0xFFC02000,
+ IRQ_UART1_RX,
+ CH_UART1_RX,
+ CH_UART1_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR2
+ {
+ 0xFFC02100,
+ IRQ_UART2_RX,
+ CH_UART2_RX,
+ CH_UART2_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR3
+ {
+ 0xFFC03100,
+ IRQ_UART3_RX,
+ CH_UART3_RX,
+ CH_UART3_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR1
+ peripheral_request(P_UART1_TX, DRIVER_NAME);
+ peripheral_request(P_UART1_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR2
+ peripheral_request(P_UART2_TX, DRIVER_NAME);
+ peripheral_request(P_UART2_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR3
+ peripheral_request(P_UART3_TX, DRIVER_NAME);
+ peripheral_request(P_UART3_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
index 3bd67da86053..d6ee74ac0460 100644
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -153,17 +153,33 @@
#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
-#define UART_THR UART1_THR
-#define UART_RBR UART1_RBR
-#define UART_DLL UART1_DLL
-#define UART_IER UART1_IER
-#define UART_DLH UART1_DLH
-#define UART_IIR UART1_IIR
-#define UART_LCR UART1_LCR
-#define UART_MCR UART1_MCR
-#define UART_LSR UART1_LSR
-#define UART_SCR UART1_SCR
-#define UART_GCTL UART1_GCTL
+
+#define BFIN_UART_THR UART1_THR
+#define BFIN_UART_RBR UART1_RBR
+#define BFIN_UART_DLL UART1_DLL
+#define BFIN_UART_IER UART1_IER
+#define BFIN_UART_DLH UART1_DLH
+#define BFIN_UART_IIR UART1_IIR
+#define BFIN_UART_LCR UART1_LCR
+#define BFIN_UART_MCR UART1_MCR
+#define BFIN_UART_LSR UART1_LSR
+#define BFIN_UART_SCR UART1_SCR
+#define BFIN_UART_GCTL UART1_GCTL
+
+#define BFIN_UART_NR_PORTS 4
+
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_GCTL 0x08 /* Global Control Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
+#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
+#define OFFSET_THR 0x28 /* Transmit Holding register */
+#define OFFSET_RBR 0x2C /* Receive Buffer register */
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h
index 308b33ab5311..60b9f77576f1 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF542.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF542.h
@@ -123,12 +123,12 @@
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() fin_read16(SDH_DATA_CNT)
+#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() fin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) fin_write16(SDH_STATUS_CLR, val)
+#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
@@ -184,8 +184,8 @@
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() fin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) fin_write16(USB_TESTMODE, val)
+#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
@@ -244,7 +244,7 @@
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) fin_write16(USB_OTG_VBUS_IRQ, val)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h
index 7a2d177c8dc2..ea9b4ab496f3 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF544.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF544.h
@@ -113,39 +113,6 @@
/* Two Wire Interface Registers (TWI1) */
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
-#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
-#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
-#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-
/* CAN Controller 1 Config 1 Registers */
#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h
index d0a200b08abd..ba716277c00d 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF547.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF547.h
@@ -185,39 +185,6 @@
/* Two Wire Interface Registers (TWI1) */
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
-#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
-#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
-#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-
/* SPI2 Registers */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h
index 674be0216bff..ae971ebff6a0 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF548.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF548.h
@@ -185,39 +185,6 @@
/* Two Wire Interface Registers (TWI1) */
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
-#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
-#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
-#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-
/* SPI2 Registers */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h
index 2ab5b7c00820..92d07d961999 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF549.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF549.h
@@ -185,39 +185,6 @@
/* Two Wire Interface Registers (TWI1) */
-#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
-#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
-#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
-#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
-#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
-#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
-#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
-#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
-#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
-#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
-#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
-#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
-#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
-#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
-#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
-#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
-#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
-#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
-#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
-#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
-#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
-#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
-#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
-#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-
/* SPI2 Registers */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
@@ -1773,7 +1740,7 @@
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) fin_write16(USB_DMA5COUNTLOW, val)
+#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 19ddcd83c71f..57ac8cb9b1f6 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -43,7 +43,33 @@
/* PLL Registers */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+ unsigned long flags, iwr0, iwr1, iwr2;
+
+ if (val == bfin_read_PLL_CTL())
+ return;
+
+ local_irq_save(flags);
+ /* Enable the PLL Wakeup bit in SIC IWR */
+ iwr0 = bfin_read32(SIC_IWR0);
+ iwr1 = bfin_read32(SIC_IWR1);
+ iwr2 = bfin_read32(SIC_IWR2);
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SIC_IWR0, IWR_ENABLE(0));
+ bfin_write32(SIC_IWR1, 0);
+ bfin_write32(SIC_IWR2, 0);
+
+ bfin_write16(PLL_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+ bfin_write32(SIC_IWR0, iwr0);
+ bfin_write32(SIC_IWR1, iwr1);
+ bfin_write32(SIC_IWR2, iwr2);
+ local_irq_restore(flags);
+}
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -52,6 +78,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1, iwr2;
+ if (val == bfin_read_VR_CTL())
+ return;
+
+ local_irq_save(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SIC_IWR0);
iwr1 = bfin_read32(SIC_IWR1);
@@ -63,13 +93,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write16(VR_CTL, val);
SSYNC();
-
- local_irq_save(flags);
asm("IDLE;");
- local_irq_restore(flags);
+
bfin_write32(SIC_IWR0, iwr0);
bfin_write32(SIC_IWR1, iwr1);
bfin_write32(SIC_IWR2, iwr2);
+ local_irq_restore(flags);
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
@@ -211,39 +240,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* Two Wire Interface Registers (TWI0) */
-#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
-#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
-#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
-#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
-#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
-#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
-#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
-#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
-#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define bfin_read_TWI0_MASTER_CTRL() bfin_read16(TWI0_MASTER_CTRL)
-#define bfin_write_TWI0_MASTER_CTRL(val) bfin_write16(TWI0_MASTER_CTRL, val)
-#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
-#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
-#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
-#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
-#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
-#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
-#define bfin_read_TWI0_FIFO_CTRL() bfin_read16(TWI0_FIFO_CTRL)
-#define bfin_write_TWI0_FIFO_CTRL(val) bfin_write16(TWI0_FIFO_CTRL, val)
-#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
-#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
-#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
-#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
-#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
-#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-
/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
/* SPORT1 Registers */
@@ -323,7 +319,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
@@ -392,23 +388,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 0 Registers */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
@@ -421,23 +417,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 1 Registers */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
@@ -450,23 +446,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 2 Registers */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
@@ -479,23 +475,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 3 Registers */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
@@ -508,23 +504,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 4 Registers */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
@@ -537,23 +533,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 5 Registers */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
@@ -566,23 +562,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 6 Registers */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
@@ -595,23 +591,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 7 Registers */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
@@ -624,23 +620,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 8 Registers */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
@@ -653,23 +649,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 9 Registers */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
@@ -682,23 +678,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 10 Registers */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
@@ -711,23 +707,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 11 Registers */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
@@ -740,7 +736,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* MDMA Stream 0 Registers */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
@@ -803,11 +799,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
@@ -829,11 +825,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
@@ -1246,23 +1242,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 12 Registers */
#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
@@ -1275,23 +1271,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 13 Registers */
#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
@@ -1304,23 +1300,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 14 Registers */
#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
@@ -1333,23 +1329,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 15 Registers */
#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
@@ -1362,23 +1358,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 16 Registers */
#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
@@ -1391,23 +1387,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 17 Registers */
#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
@@ -1420,23 +1416,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 18 Registers */
#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
@@ -1449,23 +1445,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 19 Registers */
#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
@@ -1478,23 +1474,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 20 Registers */
#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
@@ -1507,23 +1503,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 21 Registers */
#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
@@ -1536,23 +1532,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 22 Registers */
#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
@@ -1565,23 +1561,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* DMA Channel 23 Registers */
#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
@@ -1594,23 +1590,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* MDMA Stream 2 Registers */
#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
@@ -1620,23 +1616,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
@@ -1649,23 +1645,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
/* MDMA Stream 3 Registers */
#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
@@ -1675,23 +1671,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
index 46ff31f20ae5..36a2ef7e7849 100644
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ b/include/asm-blackfin/mach-bf548/dma.h
@@ -73,6 +73,4 @@
#define MAX_BLACKFIN_DMA_CHANNEL 32
-extern int channel2irq(unsigned int channel);
-extern struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL];
#endif
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index befc2903d5a5..ab0b863eee66 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -29,16 +29,19 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
+#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
+#define DDR_CLK_HZ(x) (1000*1000*1000/x)
#if (CONFIG_MEM_MT46V32M16_6T)
#define DDR_SIZE DEVSZ_512
#define DDR_WIDTH DEVWD_16
+#define DDR_MAX_tCK 13
#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
-#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
+#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
#define DDR_tWTR DDR_TWTR(1)
@@ -49,12 +52,13 @@
#if (CONFIG_MEM_MT46V32M16_5B)
#define DDR_SIZE DEVSZ_512
#define DDR_WIDTH DEVWD_16
+#define DDR_MAX_tCK 13
#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
-#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
+#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
#define DDR_tWTR DDR_TWTR(2)
@@ -65,6 +69,7 @@
#if (CONFIG_MEM_GENERIC_BOARD)
#define DDR_SIZE DEVSZ_512
#define DDR_WIDTH DEVWD_16
+#define DDR_MAX_tCK 13
#define DDR_tRCD DDR_TRCD(3)
#define DDR_tWTR DDR_TWTR(2)
@@ -77,14 +82,15 @@
#define DDR_tREFI DDR_TREFI(1288)
#endif
-#if (CONFIG_SCLK_HZ <= 133333333)
-#define DDR_CL CL_2
-#elif (CONFIG_SCLK_HZ <= 166666666)
-#define DDR_CL CL_2_5
+#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
+# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
+#elif(CONFIG_SCLK_HZ <= 133333333)
+# define DDR_CL CL_2
#else
-#define DDR_CL CL_3
+# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
#endif
+
#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
| DDR_tMRD | DDR_tWR | DDR_tRCD)
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index 0c1d46193939..82157caa96a2 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -7,7 +7,7 @@
*/
/* This file shoule be up to date with:
- * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
+ * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -256,10 +256,14 @@
#define ANOMALY_05000357 (1)
/* Conflicting Column Address Widths Causes SDRAM Errors */
#define ANOMALY_05000362 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0)
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index b6f513bee56e..8a4e66d1db37 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -1,22 +1,38 @@
+/*
+ * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 1
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
@@ -84,7 +100,7 @@ static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
@@ -115,7 +131,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
#define DRIVER_NAME "bfin-uart"
-int nr_ports = NR_PORTS;
+int nr_ports = BFIN_UART_NR_PORTS;
static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{
diff --git a/include/asm-blackfin/mach-bf561/bfin_sir.h b/include/asm-blackfin/mach-bf561/bfin_sir.h
new file mode 100644
index 000000000000..cefcf8bb505b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/bfin_sir.h
@@ -0,0 +1,120 @@
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART_RX,
+ CH_UART_RX,
+ CH_UART_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
+{
+ unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
+ port->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | port->lsr;
+}
+
+static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
+{
+ port->lsr = 0;
+ bfin_read16(port->membase + OFFSET_LSR);
+}
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 3a16df2c86d8..0ea8666e6764 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -69,5 +69,19 @@
#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
+#define BFIN_UART_NR_PORTS 1
+
+#define OFFSET_THR 0x00 /* Transmit Holding register */
+#define OFFSET_RBR 0x00 /* Receive Buffer register */
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_IER 0x04 /* Interrupt Enable Register */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_GCTL 0x24 /* Global Control Register */
#endif /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 1bc8d2f89ccc..b07ffccd66dd 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -47,7 +47,30 @@
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+ unsigned long flags, iwr0, iwr1;
+
+ if (val == bfin_read_PLL_CTL())
+ return;
+
+ local_irq_save(flags);
+ /* Enable the PLL Wakeup bit in SIC IWR */
+ iwr0 = bfin_read32(SICA_IWR0);
+ iwr1 = bfin_read32(SICA_IWR1);
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+ bfin_write32(SICA_IWR1, 0);
+
+ bfin_write16(PLL_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+ bfin_write32(SICA_IWR0, iwr0);
+ bfin_write32(SICA_IWR1, iwr1);
+ local_irq_restore(flags);
+}
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -56,6 +79,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
{
unsigned long flags, iwr0, iwr1;
+ if (val == bfin_read_VR_CTL())
+ return;
+
+ local_irq_save(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SICA_IWR0);
iwr1 = bfin_read32(SICA_IWR1);
@@ -65,12 +92,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
bfin_write16(VR_CTL, val);
SSYNC();
-
- local_irq_save(flags);
asm("IDLE;");
- local_irq_restore(flags);
+
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
+ local_irq_restore(flags);
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index c3c0eb13c819..366c9b9a0cb7 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -110,18 +110,23 @@
#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR 0xFFC00400 /* Transmit Holding register */
-#define UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART_LCR 0xFFC0040C /* Line Control Register */
-#define UART_MCR 0xFFC00410 /* Modem Control Register */
-#define UART_LSR 0xFFC00414 /* Line Status Register */
-#define UART_MSR 0xFFC00418 /* Modem Status Register */
-#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART_GCTL 0xFFC00424 /* Global Control Register */
+
+/*
+ * Because include/linux/serial_reg.h have defined UART_*,
+ * So we define blackfin uart regs to BFIN_UART0_*.
+ */
+#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
+#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
+#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
+#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
+#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
+#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
+#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
+#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
+#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500
@@ -866,6 +871,8 @@
/* PLL_DIV Masks */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
+#define CSEL 0x30 /* Core Select */
+#define SSEL 0xf /* System Select */
#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
index 766334b7d8ab..21d982003e75 100644
--- a/include/asm-blackfin/mach-bf561/dma.h
+++ b/include/asm-blackfin/mach-bf561/dma.h
@@ -32,7 +32,4 @@
#define CH_IMEM_STREAM1_SRC 34
#define CH_IMEM_STREAM1_DEST 35
-extern int channel2irq(unsigned int channel);
-extern struct dma_register *base_addr[];
-
#endif
diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h
index 0d3f650d2d99..0807b286cd9e 100644
--- a/include/asm-blackfin/portmux.h
+++ b/include/asm-blackfin/portmux.h
@@ -17,8 +17,8 @@
int peripheral_request(unsigned short per, const char *label);
void peripheral_free(unsigned short per);
-int peripheral_request_list(unsigned short per[], const char *label);
-void peripheral_free_list(unsigned short per[]);
+int peripheral_request_list(const unsigned short per[], const char *label);
+void peripheral_free_list(const unsigned short per[]);
#include <asm/gpio.h>
#include <asm/mach/portmux.h>
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
index 1033e5c76011..1c0040724612 100644
--- a/include/asm-blackfin/processor.h
+++ b/include/asm-blackfin/processor.h
@@ -26,9 +26,10 @@ static inline void wrusp(unsigned long usp)
/*
* User space process size: 1st byte beyond user address space.
+ * Fairly meaningless on nommu. Parts of user programs can be scattered
+ * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
*/
-extern unsigned long memory_end;
-#define TASK_SIZE (memory_end)
+#define TASK_SIZE 0xFFFFFFFF
#ifdef __KERNEL__
#define STACK_TOP TASK_SIZE
diff --git a/include/asm-blackfin/semaphore-helper.h b/include/asm-blackfin/semaphore-helper.h
deleted file mode 100644
index 9082b0dc3eb5..000000000000
--- a/include/asm-blackfin/semaphore-helper.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Based on M68K version, Lineo Inc. May 2001 */
-
-#ifndef _BFIN_SEMAPHORE_HELPER_H
-#define _BFIN_SEMAPHORE_HELPER_H
-
-/*
- * SMP- and interrupt-safe semaphores helper functions.
- *
- * (C) Copyright 1996 Linus Torvalds
- *
- */
-
-#include <asm/errno.h>
-
-/*
- * These two _must_ execute atomically wrt each other.
- */
-static inline void wake_one_more(struct semaphore *sem)
-{
- atomic_inc(&sem->waking);
-}
-
-static inline int waking_non_zero(struct semaphore *sem)
-{
- int ret;
- unsigned long flags = 0;
-
- spin_lock_irqsave(&semaphore_wake_lock, flags);
- ret = 0;
- if (atomic_read(&sem->waking) > 0) {
- atomic_dec(&sem->waking);
- ret = 1;
- }
- spin_unlock_irqrestore(&semaphore_wake_lock, flags);
- return ret;
-}
-
-/*
- * waking_non_zero_interruptible:
- * 1 got the lock
- * 0 go to sleep
- * -EINTR interrupted
- */
-static inline int waking_non_zero_interruptible(struct semaphore *sem,
- struct task_struct *tsk)
-{
- int ret = 0;
- unsigned long flags = 0;
-
- spin_lock_irqsave(&semaphore_wake_lock, flags);
- if (atomic_read(&sem->waking) > 0) {
- atomic_dec(&sem->waking);
- ret = 1;
- } else if (signal_pending(tsk)) {
- atomic_inc(&sem->count);
- ret = -EINTR;
- }
- spin_unlock_irqrestore(&semaphore_wake_lock, flags);
- return ret;
-}
-
-/*
- * waking_non_zero_trylock:
- * 1 failed to lock
- * 0 got the lock
- */
-static inline int waking_non_zero_trylock(struct semaphore *sem)
-{
- int ret = 1;
- unsigned long flags = 0;
-
- spin_lock_irqsave(&semaphore_wake_lock, flags);
- if (atomic_read(&sem->waking) > 0) {
- atomic_dec(&sem->waking);
- ret = 0;
- } else
- atomic_inc(&sem->count);
- spin_unlock_irqrestore(&semaphore_wake_lock, flags);
- return ret;
-}
-
-#endif /* _BFIN_SEMAPHORE_HELPER_H */
diff --git a/include/asm-blackfin/semaphore.h b/include/asm-blackfin/semaphore.h
index 533f90fb2e4e..d9b2034ed1d2 100644
--- a/include/asm-blackfin/semaphore.h
+++ b/include/asm-blackfin/semaphore.h
@@ -1,105 +1 @@
-#ifndef _BFIN_SEMAPHORE_H
-#define _BFIN_SEMAPHORE_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/linkage.h>
-#include <linux/wait.h>
-#include <linux/spinlock.h>
-#include <linux/rwsem.h>
-#include <asm/atomic.h>
-
-/*
- * Interrupt-safe semaphores..
- *
- * (C) Copyright 1996 Linus Torvalds
- *
- * BFIN version by akbar hussain Lineo Inc April 2001
- *
- */
-
-struct semaphore {
- atomic_t count;
- int sleepers;
- wait_queue_head_t wait;
-};
-
-#define __SEMAPHORE_INITIALIZER(name, n) \
-{ \
- .count = ATOMIC_INIT(n), \
- .sleepers = 0, \
- .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
-}
-
-#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
- struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
-
-#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
-
-static inline void sema_init(struct semaphore *sem, int val)
-{
- *sem = (struct semaphore)__SEMAPHORE_INITIALIZER(*sem, val);
-}
-
-static inline void init_MUTEX(struct semaphore *sem)
-{
- sema_init(sem, 1);
-}
-
-static inline void init_MUTEX_LOCKED(struct semaphore *sem)
-{
- sema_init(sem, 0);
-}
-
-asmlinkage void __down(struct semaphore *sem);
-asmlinkage int __down_interruptible(struct semaphore *sem);
-asmlinkage int __down_trylock(struct semaphore *sem);
-asmlinkage void __up(struct semaphore *sem);
-
-extern spinlock_t semaphore_wake_lock;
-
-/*
- * This is ugly, but we want the default case to fall through.
- * "down_failed" is a special asm handler that calls the C
- * routine that actually waits.
- */
-static inline void down(struct semaphore *sem)
-{
- might_sleep();
- if (atomic_dec_return(&sem->count) < 0)
- __down(sem);
-}
-
-static inline int down_interruptible(struct semaphore *sem)
-{
- int ret = 0;
-
- might_sleep();
- if (atomic_dec_return(&sem->count) < 0)
- ret = __down_interruptible(sem);
- return (ret);
-}
-
-static inline int down_trylock(struct semaphore *sem)
-{
- int ret = 0;
-
- if (atomic_dec_return(&sem->count) < 0)
- ret = __down_trylock(sem);
- return ret;
-}
-
-/*
- * Note! This is subtle. We jump to wake people up only if
- * the semaphore was negative (== somebody was waiting on it).
- * The default case (no contention) will result in NO
- * jumps for both down() and up().
- */
-static inline void up(struct semaphore *sem)
-{
- if (atomic_inc_return(&sem->count) <= 0)
- __up(sem);
-}
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_SEMAPHORE_H */
+#include <linux/semaphore.h>
diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h
index 0250429b736a..87951d251458 100644
--- a/include/asm-blackfin/signal.h
+++ b/include/asm-blackfin/signal.h
@@ -143,7 +143,7 @@ struct sigaction {
#endif /* __KERNEL__ */
typedef struct sigaltstack {
- void *ss_sp;
+ void __user *ss_sp;
int ss_flags;
size_t ss_size;
} stack_t;
diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h
index 15b99cf4f50b..bc2fe5accf20 100644
--- a/include/asm-blackfin/thread_info.h
+++ b/include/asm-blackfin/thread_info.h
@@ -81,14 +81,11 @@ struct thread_info {
#define init_thread_info (init_thread_union.thread_info)
#define init_stack (init_thread_union.stack)
-/* How to get the thread information struct from C */
-
-static inline struct thread_info *current_thread_info(void)
- __attribute__ ((__const__));
-
-/* Given a task stack pointer, you can find it's task structure
- * just by masking it to the 8K boundary.
+/* Given a task stack pointer, you can find its corresponding
+ * thread_info structure just by masking it to the THREAD_SIZE
+ * boundary (currently 8K as you can see above).
*/
+__attribute_const__
static inline struct thread_info *current_thread_info(void)
{
struct thread_info *ti;
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h
new file mode 100644
index 000000000000..6e5859b6ea32
--- /dev/null
+++ b/include/asm-blackfin/time.h
@@ -0,0 +1,36 @@
+/*
+ * asm-blackfin/time.h:
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _ASM_BLACKFIN_TIME_H
+#define _ASM_BLACKFIN_TIME_H
+
+/*
+ * The way that the Blackfin core timer works is:
+ * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
+ * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
+ *
+ * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
+ * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
+ * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
+ * to use TSCALE, and program it to zero (which is pass CCLK through).
+ * If you feel like using it, try to keep HZ * TIMESCALE to some
+ * value that divides easy (like power of 2).
+ */
+
+#ifndef CONFIG_CPU_FREQ
+#define TIME_SCALE 1
+#else
+/*
+ * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
+ * Whenever we change the Core Clock frequency changes we immediately
+ * adjust the Core Timer Presale Register. This way we don't lose time.
+ */
+#define TIME_SCALE 4
+#endif
+
+#endif
diff --git a/include/asm-blackfin/timex.h b/include/asm-blackfin/timex.h
index 828590117f51..22b0806161bb 100644
--- a/include/asm-blackfin/timex.h
+++ b/include/asm-blackfin/timex.h
@@ -1,18 +1,23 @@
-/* blackfin architecture timex specifications: Lineo Inc. 2001
+/*
+ * asm-blackfin/timex.h: cpu cycles!
*
- * Based on: include/asm-m68knommu/timex.h
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
*/
-#ifndef _ASMBLACKFIN_TIMEX_H
-#define _ASMBLACKFIN_TIMEX_H
+#ifndef _ASM_BLACKFIN_TIMEX_H
+#define _ASM_BLACKFIN_TIMEX_H
#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
-typedef unsigned long cycles_t;
+typedef unsigned long long cycles_t;
static inline cycles_t get_cycles(void)
{
- return 0;
+ unsigned long tmp, tmp2;
+ __asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
+ return tmp | ((cycles_t)tmp2 << 32);
}
#endif
diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h
index ef18afbc2101..312b596b9731 100644
--- a/include/asm-blackfin/trace.h
+++ b/include/asm-blackfin/trace.h
@@ -62,14 +62,14 @@ extern unsigned long software_trace_buff[];
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = [preg]; \
- [sp++] = dreg; \
+ [--sp] = dreg; \
dreg = 0x1; \
[preg] = dreg;
#define trace_buffer_restore(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
- dreg = [sp--]; \
+ dreg = [sp++]; \
[preg] = dreg;
#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 22a410b8003b..d928b8099056 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -133,7 +133,7 @@ static inline int bad_user_access_length(void)
}
#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
- __FILE__, __LINE__, __FUNCTION__),\
+ __FILE__, __LINE__, __func__),\
bad_user_access_length(), (-EFAULT))
/*
@@ -177,7 +177,7 @@ static inline int bad_user_access_length(void)
default: \
x = 0; \
printk(KERN_INFO "get_user_bad: %s:%d %s\n", \
- __FILE__, __LINE__, __FUNCTION__); \
+ __FILE__, __LINE__, __func__); \
_err = __get_user_bad(); \
break; \
} \
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
index c18a399f6e3e..42955d0c439b 100644
--- a/include/asm-blackfin/unistd.h
+++ b/include/asm-blackfin/unistd.h
@@ -265,14 +265,14 @@
/* 258 __NR_remap_file_pages */
#define __NR_set_tid_address 259
#define __NR_timer_create 260
-#define __NR_timer_settime (__NR_timer_create+1)
-#define __NR_timer_gettime (__NR_timer_create+2)
-#define __NR_timer_getoverrun (__NR_timer_create+3)
-#define __NR_timer_delete (__NR_timer_create+4)
-#define __NR_clock_settime (__NR_timer_create+5)
-#define __NR_clock_gettime (__NR_timer_create+6)
-#define __NR_clock_getres (__NR_timer_create+7)
-#define __NR_clock_nanosleep (__NR_timer_create+8)
+#define __NR_timer_settime 261
+#define __NR_timer_gettime 262
+#define __NR_timer_getoverrun 263
+#define __NR_timer_delete 264
+#define __NR_clock_settime 265
+#define __NR_clock_gettime 266
+#define __NR_clock_getres 267
+#define __NR_clock_nanosleep 268
#define __NR_statfs64 269
#define __NR_fstatfs64 270
#define __NR_tgkill 271
@@ -283,11 +283,11 @@
/* 276 __NR_get_mempolicy */
/* 277 __NR_set_mempolicy */
#define __NR_mq_open 278
-#define __NR_mq_unlink (__NR_mq_open+1)
-#define __NR_mq_timedsend (__NR_mq_open+2)
-#define __NR_mq_timedreceive (__NR_mq_open+3)
-#define __NR_mq_notify (__NR_mq_open+4)
-#define __NR_mq_getsetattr (__NR_mq_open+5)
+#define __NR_mq_unlink 279
+#define __NR_mq_timedsend 280
+#define __NR_mq_timedreceive 281
+#define __NR_mq_notify 282
+#define __NR_mq_getsetattr 283
#define __NR_kexec_load 284
#define __NR_waitid 285
#define __NR_add_key 286