diff options
Diffstat (limited to 'drivers/staging')
| -rw-r--r-- | drivers/staging/dwc2/core.h | 34 | ||||
| -rw-r--r-- | drivers/staging/dwc2/hcd.h | 22 |
2 files changed, 28 insertions, 28 deletions
diff --git a/drivers/staging/dwc2/core.h b/drivers/staging/dwc2/core.h index e771e405453f..e5b4dc8948a3 100644 --- a/drivers/staging/dwc2/core.h +++ b/drivers/staging/dwc2/core.h @@ -74,6 +74,9 @@ enum dwc2_lx_state { * 0 - HNP and SRP capable (default) * 1 - SRP Only capable * 2 - No HNP/SRP capable + * @otg_ver: OTG version supported + * 0 - 1.3 + * 1 - 2.0 * @dma_enable: Specifies whether to use slave or DMA mode for accessing * the data FIFOs. The driver will automatically detect the * value for this parameter if none is specified. @@ -90,20 +93,10 @@ enum dwc2_lx_state { * the attached device and the value of phy_type. * 0 - High Speed (default) * 1 - Full Speed - * @host_support_fs_ls_low_power: Specifies whether low power mode is supported - * when attached to a Full Speed or Low Speed device in - * host mode. - * 0 - Don't support low power mode (default) - * 1 - Support low power mode - * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode - * when connected to a Low Speed device in host mode. This - * parameter is applicable only if - * host_support_fs_ls_low_power is enabled. If phy_type is - * set to FS then defaults to 6 MHZ otherwise 48 MHZ. - * 0 - 48 MHz - * 1 - 6 MHz * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters * 1 - Allow dynamic FIFO sizing (default) + * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs + * are enabled * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when * dynamic FIFO sizing is enabled * 16 to 32768 (default 1024) @@ -145,9 +138,19 @@ enum dwc2_lx_state { * 0 - No (default) * 1 - Yes * @ulpi_fs_ls: True to make ULPI phy operate in FS/LS mode only + * @host_support_fs_ls_low_power: Specifies whether low power mode is supported + * when attached to a Full Speed or Low Speed device in + * host mode. + * 0 - Don't support low power mode (default) + * 1 - Support low power mode + * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode + * when connected to a Low Speed device in host mode. This + * parameter is applicable only if + * host_support_fs_ls_low_power is enabled. If phy_type is + * set to FS then defaults to 6 MHZ otherwise 48 MHZ. + * 0 - 48 MHz + * 1 - 6 MHz * @ts_dline: True to enable Term Select Dline pulsing - * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs - * are enabled * @reload_ctl: True to allow dynamic reloading of HFIR register during * runtime * @ahbcfg: This field allows the default value of the GAHBCFG @@ -155,9 +158,6 @@ enum dwc2_lx_state { * -1 - GAHBCFG value will not be overridden * all others - GAHBCFG value will be overridden with * this value - * @otg_ver: OTG version supported - * 0 - 1.3 - * 1 - 2.0 * * The following parameters may be specified when starting the module. These * parameters define how the DWC_otg controller should be configured. diff --git a/drivers/staging/dwc2/hcd.h b/drivers/staging/dwc2/hcd.h index 933e8d1999bf..3b060247c7fc 100644 --- a/drivers/staging/dwc2/hcd.h +++ b/drivers/staging/dwc2/hcd.h @@ -232,16 +232,19 @@ enum dwc2_transaction_type { * - DWC2_HC_PID_DATA1 * @ping_state: Ping state * @do_split: Full/low speed endpoint on high-speed hub requires split - * @qtd_list: List of QTDs for this QH - * @channel: Host channel currently processing transfers for this QH + * @td_first: Index of first activated isochronous transfer descriptor + * @td_last: Index of last activated isochronous transfer descriptor * @usecs: Bandwidth in microseconds per (micro)frame * @interval: Interval between transfers in (micro)frames - * @sched_frame: (micro)frame to initialize a periodic transfer. + * @sched_frame: (Micro)frame to initialize a periodic transfer. * The transfer executes in the following (micro)frame. * @start_split_frame: (Micro)frame at which last start split was initialized + * @ntd: Actual number of transfer descriptors in a list * @dw_align_buf: Used instead of original buffer if its physical address * is not dword-aligned * @dw_align_buf_dma: DMA address for align_buf + * @qtd_list: List of QTDs for this QH + * @channel: Host channel currently processing transfers for this QH * @qh_list_entry: Entry for QH in either the periodic or non-periodic * schedule * @desc_list: List of transfer descriptors @@ -249,9 +252,6 @@ enum dwc2_transaction_type { * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer * descriptor and indicates original XferSize value for the * descriptor - * @ntd: Actual number of transfer descriptors in a list - * @td_first: Index of first activated isochronous transfer descriptor - * @td_last: Index of last activated isochronous transfer descriptor * @tt_buffer_dirty True if clear_tt_buffer_complete is pending * * A Queue Head (QH) holds the static characteristics of an endpoint and @@ -266,21 +266,21 @@ struct dwc2_qh { u8 data_toggle; u8 ping_state; u8 do_split; - struct list_head qtd_list; - struct dwc2_host_chan *channel; + u8 td_first; + u8 td_last; u16 usecs; u16 interval; u16 sched_frame; u16 start_split_frame; + u16 ntd; u8 *dw_align_buf; dma_addr_t dw_align_buf_dma; + struct list_head qtd_list; + struct dwc2_host_chan *channel; struct list_head qh_list_entry; struct dwc2_hcd_dma_desc *desc_list; dma_addr_t desc_list_dma; u32 *n_bytes; - u16 ntd; - u8 td_first; - u8 td_last; unsigned tt_buffer_dirty:1; }; |