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-rw-r--r--drivers/spi/omap2_mcspi.c18
-rw-r--r--drivers/spi/spi_s3c24xx.c2
2 files changed, 13 insertions, 7 deletions
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index 715c518b1b68..4dd786b99b8b 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -578,6 +578,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
struct spi_master *spi_cntrl;
u32 l = 0, div = 0;
u8 word_len = spi->bits_per_word;
+ u32 speed_hz = spi->max_speed_hz;
mcspi = spi_master_get_devdata(spi->master);
spi_cntrl = mcspi->master;
@@ -587,9 +588,12 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
cs->word_len = word_len;
- if (spi->max_speed_hz) {
+ if (t && t->speed_hz)
+ speed_hz = t->speed_hz;
+
+ if (speed_hz) {
while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
- > spi->max_speed_hz)
+ > speed_hz)
div++;
} else
div = 15;
@@ -751,11 +755,13 @@ static void omap2_mcspi_cleanup(struct spi_device *spi)
mcspi = spi_master_get_devdata(spi->master);
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
- /* Unlink controller state from context save list */
- cs = spi->controller_state;
- list_del(&cs->node);
+ if (spi->controller_state) {
+ /* Unlink controller state from context save list */
+ cs = spi->controller_state;
+ list_del(&cs->node);
- kfree(spi->controller_state);
+ kfree(spi->controller_state);
+ }
if (mcspi_dma->dma_rx_channel != -1) {
omap_free_dma(mcspi_dma->dma_rx_channel);
diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c
index c010733877ae..1fabede9e061 100644
--- a/drivers/spi/spi_s3c24xx.c
+++ b/drivers/spi/spi_s3c24xx.c
@@ -275,7 +275,7 @@ static inline u32 ack_bit(unsigned int irq)
* Claim the FIQ handler (only one can be active at any one time) and
* then setup the correct transfer code for this transfer.
*
- * This call updates all the necessary state information if sucessful,
+ * This call updates all the necessary state information if successful,
* so the caller does not need to do anything more than start the transfer
* as normal, since the IRQ will have been re-routed to the FIQ handler.
*/