diff options
Diffstat (limited to 'drivers/net/smc91x.h')
| -rw-r--r-- | drivers/net/smc91x.h | 331 |
1 files changed, 160 insertions, 171 deletions
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index 51d4134b37b1..69e97a1cb1c4 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -34,6 +34,7 @@ #ifndef _SMC91X_H_ #define _SMC91X_H_ +#include <linux/smc91x.h> /* * Define your architecture specific bus configuration parameters here. @@ -291,36 +292,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define SMC_insw(a, r, p, l) insw((a) + (r), p, l) #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) -#elif defined(CONFIG_SUPERH) - -#ifdef CONFIG_SOLUTION_ENGINE -#define SMC_IRQ_FLAGS (0) -#define SMC_CAN_USE_8BIT 0 -#define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 0 -#define SMC_IO_SHIFT 0 -#define SMC_NOWAIT 1 - -#define SMC_inw(a, r) inw((a) + (r)) -#define SMC_outw(v, a, r) outw(v, (a) + (r)) -#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) -#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) - -#else /* BOARDS */ - -#define SMC_CAN_USE_8BIT 1 -#define SMC_CAN_USE_16BIT 1 -#define SMC_CAN_USE_32BIT 0 - -#define SMC_inb(a, r) inb((a) + (r)) -#define SMC_inw(a, r) inw((a) + (r)) -#define SMC_outb(v, a, r) outb(v, (a) + (r)) -#define SMC_outw(v, a, r) outw(v, (a) + (r)) -#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) -#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) - -#endif /* BOARDS */ - #elif defined(CONFIG_M32R) #define SMC_CAN_USE_8BIT 0 @@ -475,12 +446,15 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r, #define SMC_outb(v, a, r) writeb(v, (a) + (r)) #define SMC_outw(v, a, r) writew(v, (a) + (r)) #define SMC_outl(v, a, r) writel(v, (a) + (r)) +#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) +#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) #define RPC_LSA_DEFAULT RPC_LED_100_10 #define RPC_LSB_DEFAULT RPC_LED_TX_RX +#define SMC_DYNAMIC_BUS_CONFIG #endif @@ -526,8 +500,19 @@ struct smc_local { #endif void __iomem *base; void __iomem *datacs; + + struct smc91x_platdata cfg; }; +#ifdef SMC_DYNAMIC_BUS_CONFIG +#define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT) +#define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT) +#define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT) +#else +#define SMC_8BIT(p) SMC_CAN_USE_8BIT +#define SMC_16BIT(p) SMC_CAN_USE_16BIT +#define SMC_32BIT(p) SMC_CAN_USE_32BIT +#endif #ifdef SMC_USE_PXA_DMA /* @@ -720,7 +705,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // Transmit Control Register /* BANK 0 */ -#define TCR_REG SMC_REG(0x0000, 0) +#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) #define TCR_ENABLE 0x0001 // When 1 we can transmit #define TCR_LOOP 0x0002 // Controls output pin LBK #define TCR_FORCOL 0x0004 // When 1 will force a collision @@ -739,7 +724,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // EPH Status Register /* BANK 0 */ -#define EPH_STATUS_REG SMC_REG(0x0002, 0) +#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) #define ES_TX_SUC 0x0001 // Last TX was successful #define ES_SNGL_COL 0x0002 // Single collision detected for last tx #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx @@ -758,7 +743,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // Receive Control Register /* BANK 0 */ -#define RCR_REG SMC_REG(0x0004, 0) +#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted #define RCR_PRMS 0x0002 // Enable promiscuous mode #define RCR_ALMUL 0x0004 // When set accepts all multicast frames @@ -775,17 +760,17 @@ smc_pxa_dma_irq(int dma, void *dummy) // Counter Register /* BANK 0 */ -#define COUNTER_REG SMC_REG(0x0006, 0) +#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) // Memory Information Register /* BANK 0 */ -#define MIR_REG SMC_REG(0x0008, 0) +#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) // Receive/Phy Control Register /* BANK 0 */ -#define RPC_REG SMC_REG(0x000A, 0) +#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode @@ -819,7 +804,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // Configuration Reg /* BANK 1 */ -#define CONFIG_REG SMC_REG(0x0000, 1) +#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus @@ -831,24 +816,24 @@ smc_pxa_dma_irq(int dma, void *dummy) // Base Address Register /* BANK 1 */ -#define BASE_REG SMC_REG(0x0002, 1) +#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) // Individual Address Registers /* BANK 1 */ -#define ADDR0_REG SMC_REG(0x0004, 1) -#define ADDR1_REG SMC_REG(0x0006, 1) -#define ADDR2_REG SMC_REG(0x0008, 1) +#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) +#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) +#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) // General Purpose Register /* BANK 1 */ -#define GP_REG SMC_REG(0x000A, 1) +#define GP_REG(lp) SMC_REG(lp, 0x000A, 1) // Control Register /* BANK 1 */ -#define CTL_REG SMC_REG(0x000C, 1) +#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt @@ -861,7 +846,7 @@ smc_pxa_dma_irq(int dma, void *dummy) // MMU Command Register /* BANK 2 */ -#define MMU_CMD_REG SMC_REG(0x0000, 2) +#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) #define MC_BUSY 1 // When 1 the last release has not completed #define MC_NOP (0<<5) // No Op #define MC_ALLOC (1<<5) // OR with number of 256 byte packets @@ -875,30 +860,30 @@ smc_pxa_dma_irq(int dma, void *dummy) // Packet Number Register /* BANK 2 */ -#define PN_REG SMC_REG(0x0002, 2) +#define PN_REG(lp) SMC_REG(lp, 0x0002, 2) // Allocation Result Register /* BANK 2 */ -#define AR_REG SMC_REG(0x0003, 2) +#define AR_REG(lp) SMC_REG(lp, 0x0003, 2) #define AR_FAILED 0x80 // Alocation Failed // TX FIFO Ports Register /* BANK 2 */ -#define TXFIFO_REG SMC_REG(0x0004, 2) +#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty // RX FIFO Ports Register /* BANK 2 */ -#define RXFIFO_REG SMC_REG(0x0005, 2) +#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) #define RXFIFO_REMPTY 0x80 // RX FIFO Empty -#define FIFO_REG SMC_REG(0x0004, 2) +#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) // Pointer Register /* BANK 2 */ -#define PTR_REG SMC_REG(0x0006, 2) +#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access #define PTR_READ 0x2000 // When 1 the operation is a read @@ -906,17 +891,17 @@ smc_pxa_dma_irq(int dma, void *dummy) // Data Register /* BANK 2 */ -#define DATA_REG SMC_REG(0x0008, 2) +#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) // Interrupt Status/Acknowledge Register /* BANK 2 */ -#define INT_REG SMC_REG(0x000C, 2) +#define INT_REG(lp) SMC_REG(lp, 0x000C, 2) // Interrupt Mask Register /* BANK 2 */ -#define IM_REG SMC_REG(0x000D, 2) +#define IM_REG(lp) SMC_REG(lp, 0x000D, 2) #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt #define IM_ERCV_INT 0x40 // Early Receive Interrupt #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section @@ -929,15 +914,15 @@ smc_pxa_dma_irq(int dma, void *dummy) // Multicast Table Registers /* BANK 3 */ -#define MCAST_REG1 SMC_REG(0x0000, 3) -#define MCAST_REG2 SMC_REG(0x0002, 3) -#define MCAST_REG3 SMC_REG(0x0004, 3) -#define MCAST_REG4 SMC_REG(0x0006, 3) +#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) +#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) +#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) +#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) // Management Interface Register (MII) /* BANK 3 */ -#define MII_REG SMC_REG(0x0008, 3) +#define MII_REG(lp) SMC_REG(lp, 0x0008, 3) #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup #define MII_MDOE 0x0008 // MII Output Enable #define MII_MCLK 0x0004 // MII Clock, pin MDCLK @@ -948,20 +933,20 @@ smc_pxa_dma_irq(int dma, void *dummy) // Revision Register /* BANK 3 */ /* ( hi: chip id low: rev # ) */ -#define REV_REG SMC_REG(0x000A, 3) +#define REV_REG(lp) SMC_REG(lp, 0x000A, 3) // Early RCV Register /* BANK 3 */ /* this is NOT on SMC9192 */ -#define ERCV_REG SMC_REG(0x000C, 3) +#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask // External Register /* BANK 7 */ -#define EXT_REG SMC_REG(0x0000, 7) +#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) #define CHIP_9192 3 @@ -1085,9 +1070,9 @@ static const char * chip_ids[ 16 ] = { */ #if SMC_DEBUG > 0 -#define SMC_REG(reg, bank) \ +#define SMC_REG(lp, reg, bank) \ ({ \ - int __b = SMC_CURRENT_BANK(); \ + int __b = SMC_CURRENT_BANK(lp); \ if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ printk( "%s: bank reg screwed (0x%04x)\n", \ CARDNAME, __b ); \ @@ -1096,7 +1081,7 @@ static const char * chip_ids[ 16 ] = { reg<<SMC_IO_SHIFT; \ }) #else -#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) +#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) #endif /* @@ -1108,212 +1093,215 @@ static const char * chip_ids[ 16 ] = { * * Enforce it on any 32-bit capable setup for now. */ -#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT +#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) -#define SMC_GET_PN() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \ - : (SMC_inw(ioaddr, PN_REG) & 0xFF) ) +#define SMC_GET_PN(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \ + : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF)) -#define SMC_SET_PN(x) \ +#define SMC_SET_PN(lp, x) \ do { \ - if (SMC_MUST_ALIGN_WRITE) \ - SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \ - else if (SMC_CAN_USE_8BIT) \ - SMC_outb(x, ioaddr, PN_REG); \ + if (SMC_MUST_ALIGN_WRITE(lp)) \ + SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \ + else if (SMC_8BIT(lp)) \ + SMC_outb(x, ioaddr, PN_REG(lp)); \ else \ - SMC_outw(x, ioaddr, PN_REG); \ + SMC_outw(x, ioaddr, PN_REG(lp)); \ } while (0) -#define SMC_GET_AR() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \ - : (SMC_inw(ioaddr, PN_REG) >> 8) ) +#define SMC_GET_AR(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \ + : (SMC_inw(ioaddr, PN_REG(lp)) >> 8)) -#define SMC_GET_TXFIFO() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ - : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) +#define SMC_GET_TXFIFO(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \ + : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF)) -#define SMC_GET_RXFIFO() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ - : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) +#define SMC_GET_RXFIFO(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \ + : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8)) -#define SMC_GET_INT() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ - : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) +#define SMC_GET_INT(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \ + : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF)) -#define SMC_ACK_INT(x) \ +#define SMC_ACK_INT(lp, x) \ do { \ - if (SMC_CAN_USE_8BIT) \ - SMC_outb(x, ioaddr, INT_REG); \ + if (SMC_8BIT(lp)) \ + SMC_outb(x, ioaddr, INT_REG(lp)); \ else { \ unsigned long __flags; \ int __mask; \ local_irq_save(__flags); \ - __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ - SMC_outw( __mask | (x), ioaddr, INT_REG ); \ + __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \ + SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \ local_irq_restore(__flags); \ } \ } while (0) -#define SMC_GET_INT_MASK() \ - ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ - : (SMC_inw( ioaddr, INT_REG ) >> 8) ) +#define SMC_GET_INT_MASK(lp) \ + (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \ + : (SMC_inw(ioaddr, INT_REG(lp)) >> 8)) -#define SMC_SET_INT_MASK(x) \ +#define SMC_SET_INT_MASK(lp, x) \ do { \ - if (SMC_CAN_USE_8BIT) \ - SMC_outb(x, ioaddr, IM_REG); \ + if (SMC_8BIT(lp)) \ + SMC_outb(x, ioaddr, IM_REG(lp)); \ else \ - SMC_outw((x) << 8, ioaddr, INT_REG); \ + SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \ } while (0) -#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) +#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) -#define SMC_SELECT_BANK(x) \ +#define SMC_SELECT_BANK(lp, x) \ do { \ - if (SMC_MUST_ALIGN_WRITE) \ + if (SMC_MUST_ALIGN_WRITE(lp)) \ SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ else \ SMC_outw(x, ioaddr, BANK_SELECT); \ } while (0) -#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG) +#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) -#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG) +#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp)) -#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG) +#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) -#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG) +#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp)) -#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG) +#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) -#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG) +#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) -#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG) +#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp)) -#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG) +#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) -#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG) +#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp)) -#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG) +#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) -#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG) +#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp)) -#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG) +#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) -#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG) +#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp)) -#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG) +#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) -#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG) +#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) -#define SMC_SET_PTR(x) \ +#define SMC_SET_PTR(lp, x) \ do { \ - if (SMC_MUST_ALIGN_WRITE) \ - SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \ + if (SMC_MUST_ALIGN_WRITE(lp)) \ + SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \ else \ - SMC_outw(x, ioaddr, PTR_REG); \ + SMC_outw(x, ioaddr, PTR_REG(lp)); \ } while (0) -#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG) +#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) -#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG) +#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) -#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG) +#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp)) -#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG) +#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) -#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG) +#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) -#define SMC_SET_RPC(x) \ +#define SMC_SET_RPC(lp, x) \ do { \ - if (SMC_MUST_ALIGN_WRITE) \ - SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \ + if (SMC_MUST_ALIGN_WRITE(lp)) \ + SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \ else \ - SMC_outw(x, ioaddr, RPC_REG); \ + SMC_outw(x, ioaddr, RPC_REG(lp)); \ } while (0) -#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG) +#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) -#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG) +#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp)) #ifndef SMC_GET_MAC_ADDR -#define SMC_GET_MAC_ADDR(addr) \ +#define SMC_GET_MAC_ADDR(lp, addr) \ do { \ unsigned int __v; \ - __v = SMC_inw( ioaddr, ADDR0_REG ); \ + __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \ addr[0] = __v; addr[1] = __v >> 8; \ - __v = SMC_inw( ioaddr, ADDR1_REG ); \ + __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ addr[2] = __v; addr[3] = __v >> 8; \ - __v = SMC_inw( ioaddr, ADDR2_REG ); \ + __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ addr[4] = __v; addr[5] = __v >> 8; \ } while (0) #endif -#define SMC_SET_MAC_ADDR(addr) \ +#define SMC_SET_MAC_ADDR(lp, addr) \ do { \ - SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ - SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ - SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ + SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ + SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ + SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ } while (0) -#define SMC_SET_MCAST(x) \ +#define SMC_SET_MCAST(lp, x) \ do { \ const unsigned char *mt = (x); \ - SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ - SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ - SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ - SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ + SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ + SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ + SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ + SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ } while (0) -#define SMC_PUT_PKT_HDR(status, length) \ +#define SMC_PUT_PKT_HDR(lp, status, length) \ do { \ - if (SMC_CAN_USE_32BIT) \ - SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ + if (SMC_32BIT(lp)) \ + SMC_outl((status) | (length)<<16, ioaddr, \ + DATA_REG(lp)); \ else { \ - SMC_outw(status, ioaddr, DATA_REG); \ - SMC_outw(length, ioaddr, DATA_REG); \ + SMC_outw(status, ioaddr, DATA_REG(lp)); \ + SMC_outw(length, ioaddr, DATA_REG(lp)); \ } \ } while (0) -#define SMC_GET_PKT_HDR(status, length) \ +#define SMC_GET_PKT_HDR(lp, status, length) \ do { \ - if (SMC_CAN_USE_32BIT) { \ - unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ + if (SMC_32BIT(lp)) { \ + unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \ (status) = __val & 0xffff; \ (length) = __val >> 16; \ } else { \ - (status) = SMC_inw(ioaddr, DATA_REG); \ - (length) = SMC_inw(ioaddr, DATA_REG); \ + (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ + (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ } \ } while (0) -#define SMC_PUSH_DATA(p, l) \ +#define SMC_PUSH_DATA(lp, p, l) \ do { \ - if (SMC_CAN_USE_32BIT) { \ + if (SMC_32BIT(lp)) { \ void *__ptr = (p); \ int __len = (l); \ void __iomem *__ioaddr = ioaddr; \ if (__len >= 2 && (unsigned long)__ptr & 2) { \ __len -= 2; \ - SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ + SMC_outw(*(u16 *)__ptr, ioaddr, \ + DATA_REG(lp)); \ __ptr += 2; \ } \ if (SMC_CAN_USE_DATACS && lp->datacs) \ __ioaddr = lp->datacs; \ - SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ + SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ if (__len & 2) { \ __ptr += (__len & ~3); \ - SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ + SMC_outw(*((u16 *)__ptr), ioaddr, \ + DATA_REG(lp)); \ } \ - } else if (SMC_CAN_USE_16BIT) \ - SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ - else if (SMC_CAN_USE_8BIT) \ - SMC_outsb(ioaddr, DATA_REG, p, l); \ + } else if (SMC_16BIT(lp)) \ + SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ + else if (SMC_8BIT(lp)) \ + SMC_outsb(ioaddr, DATA_REG(lp), p, l); \ } while (0) -#define SMC_PULL_DATA(p, l) \ +#define SMC_PULL_DATA(lp, p, l) \ do { \ - if (SMC_CAN_USE_32BIT) { \ + if (SMC_32BIT(lp)) { \ void *__ptr = (p); \ int __len = (l); \ void __iomem *__ioaddr = ioaddr; \ @@ -1333,16 +1321,17 @@ static const char * chip_ids[ 16 ] = { */ \ __ptr -= 2; \ __len += 2; \ - SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ + SMC_SET_PTR(lp, \ + 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ } \ if (SMC_CAN_USE_DATACS && lp->datacs) \ __ioaddr = lp->datacs; \ __len += 2; \ - SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ - } else if (SMC_CAN_USE_16BIT) \ - SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ - else if (SMC_CAN_USE_8BIT) \ - SMC_insb(ioaddr, DATA_REG, p, l); \ + SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ + } else if (SMC_16BIT(lp)) \ + SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ + else if (SMC_8BIT(lp)) \ + SMC_insb(ioaddr, DATA_REG(lp), p, l); \ } while (0) #endif /* _SMC91X_H_ */ |