summaryrefslogtreecommitdiff
path: root/drivers/media
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/Kconfig1
-rw-r--r--drivers/media/cec/core/cec-core.c4
-rw-r--r--drivers/media/common/cx2341x.c4
-rw-r--r--drivers/media/common/saa7146/saa7146_core.c39
-rw-r--r--drivers/media/common/saa7146/saa7146_fops.c9
-rw-r--r--drivers/media/common/saa7146/saa7146_vbi.c6
-rw-r--r--drivers/media/common/saa7146/saa7146_video.c6
-rw-r--r--drivers/media/common/siano/smsdvb-main.c5
-rw-r--r--drivers/media/dvb-core/dvbdev.c3
-rw-r--r--drivers/media/dvb-frontends/ascot2e.h2
-rw-r--r--drivers/media/dvb-frontends/cxd2820r.h2
-rw-r--r--drivers/media/dvb-frontends/drx39xyj/drxj.c7
-rw-r--r--drivers/media/dvb-frontends/drxd_hard.c1
-rw-r--r--drivers/media/dvb-frontends/drxk.h2
-rw-r--r--drivers/media/dvb-frontends/dvb-pll.h2
-rw-r--r--drivers/media/dvb-frontends/helene.h4
-rw-r--r--drivers/media/dvb-frontends/horus3a.h2
-rw-r--r--drivers/media/dvb-frontends/ix2505v.h4
-rw-r--r--drivers/media/dvb-frontends/m88ds3103.c6
-rw-r--r--drivers/media/dvb-frontends/m88ds3103.h2
-rw-r--r--drivers/media/dvb-frontends/mb86a20s.h2
-rw-r--r--drivers/media/dvb-frontends/nxt200x.c16
-rw-r--r--drivers/media/dvb-frontends/rtl2832.c14
-rw-r--r--drivers/media/dvb-frontends/si2165.c2
-rw-r--r--drivers/media/dvb-frontends/si2165.h2
-rw-r--r--drivers/media/dvb-frontends/si21xx.c2
-rw-r--r--drivers/media/dvb-frontends/stb6000.h2
-rw-r--r--drivers/media/dvb-frontends/tda826x.h2
-rw-r--r--drivers/media/dvb-frontends/ts2020.c10
-rw-r--r--drivers/media/dvb-frontends/zl10036.h4
-rw-r--r--drivers/media/i2c/Kconfig32
-rw-r--r--drivers/media/i2c/Makefile6
-rw-r--r--drivers/media/i2c/ad5820.c6
-rw-r--r--drivers/media/i2c/adp1653.c6
-rw-r--r--drivers/media/i2c/adv7180.c6
-rw-r--r--drivers/media/i2c/adv748x/adv748x-afe.c6
-rw-r--r--drivers/media/i2c/adv748x/adv748x-core.c34
-rw-r--r--drivers/media/i2c/adv748x/adv748x-csi2.c6
-rw-r--r--drivers/media/i2c/adv748x/adv748x.h2
-rw-r--r--drivers/media/i2c/ak7375.c7
-rw-r--r--drivers/media/i2c/ccs-pll.c886
-rw-r--r--drivers/media/i2c/ccs-pll.h214
-rw-r--r--drivers/media/i2c/ccs/Kconfig11
-rw-r--r--drivers/media/i2c/ccs/Makefile6
-rw-r--r--drivers/media/i2c/ccs/ccs-core.c3479
-rw-r--r--drivers/media/i2c/ccs/ccs-data-defs.h221
-rw-r--r--drivers/media/i2c/ccs/ccs-data.c953
-rw-r--r--drivers/media/i2c/ccs/ccs-data.h228
-rw-r--r--drivers/media/i2c/ccs/ccs-limits.c239
-rw-r--r--drivers/media/i2c/ccs/ccs-limits.h259
-rw-r--r--drivers/media/i2c/ccs/ccs-quirk.c (renamed from drivers/media/i2c/smiapp/smiapp-quirk.c)105
-rw-r--r--drivers/media/i2c/ccs/ccs-quirk.h (renamed from drivers/media/i2c/smiapp/smiapp-quirk.h)54
-rw-r--r--drivers/media/i2c/ccs/ccs-reg-access.c409
-rw-r--r--drivers/media/i2c/ccs/ccs-reg-access.h42
-rw-r--r--drivers/media/i2c/ccs/ccs-regs.h954
-rw-r--r--drivers/media/i2c/ccs/ccs.h (renamed from drivers/media/i2c/smiapp/smiapp.h)184
-rw-r--r--drivers/media/i2c/ccs/smiapp-reg-defs.h580
-rw-r--r--drivers/media/i2c/dw9768.c6
-rw-r--r--drivers/media/i2c/et8ek8/et8ek8_driver.c8
-rw-r--r--drivers/media/i2c/hi556.c6
-rw-r--r--drivers/media/i2c/imx214.c2
-rw-r--r--drivers/media/i2c/imx219.c38
-rw-r--r--drivers/media/i2c/imx258.c2
-rw-r--r--drivers/media/i2c/imx274.c280
-rw-r--r--drivers/media/i2c/imx290.c10
-rw-r--r--drivers/media/i2c/imx319.c8
-rw-r--r--drivers/media/i2c/imx355.c8
-rw-r--r--drivers/media/i2c/max2175.c2
-rw-r--r--drivers/media/i2c/max9271.c8
-rw-r--r--drivers/media/i2c/msp3400-kthreads.c12
-rw-r--r--drivers/media/i2c/mt9p031.c3
-rw-r--r--drivers/media/i2c/ov02a10.c1015
-rw-r--r--drivers/media/i2c/ov13858.c6
-rw-r--r--drivers/media/i2c/ov2680.c6
-rw-r--r--drivers/media/i2c/ov2685.c6
-rw-r--r--drivers/media/i2c/ov2740.c214
-rw-r--r--drivers/media/i2c/ov5640.c108
-rw-r--r--drivers/media/i2c/ov5670.c6
-rw-r--r--drivers/media/i2c/ov5675.c6
-rw-r--r--drivers/media/i2c/ov5695.c6
-rw-r--r--drivers/media/i2c/ov7670.c96
-rw-r--r--drivers/media/i2c/ov772x.c71
-rw-r--r--drivers/media/i2c/ov7740.c6
-rw-r--r--drivers/media/i2c/ov8856.c6
-rw-r--r--drivers/media/i2c/ov9734.c1020
-rw-r--r--drivers/media/i2c/rdacm20.c13
-rw-r--r--drivers/media/i2c/smiapp-pll.c482
-rw-r--r--drivers/media/i2c/smiapp-pll.h99
-rw-r--r--drivers/media/i2c/smiapp/Kconfig10
-rw-r--r--drivers/media/i2c/smiapp/Makefile6
-rw-r--r--drivers/media/i2c/smiapp/smiapp-core.c3175
-rw-r--r--drivers/media/i2c/smiapp/smiapp-limits.c118
-rw-r--r--drivers/media/i2c/smiapp/smiapp-limits.h114
-rw-r--r--drivers/media/i2c/smiapp/smiapp-reg-defs.h489
-rw-r--r--drivers/media/i2c/smiapp/smiapp-reg.h116
-rw-r--r--drivers/media/i2c/smiapp/smiapp-regs.c261
-rw-r--r--drivers/media/i2c/smiapp/smiapp-regs.h36
-rw-r--r--drivers/media/i2c/tvp5150.c7
-rw-r--r--drivers/media/pci/b2c2/flexcop-dma.c6
-rw-r--r--drivers/media/pci/bt8xx/bt878.c16
-rw-r--r--drivers/media/pci/bt8xx/btcx-risc.c5
-rw-r--r--drivers/media/pci/bt8xx/bttv-cards.c6
-rw-r--r--drivers/media/pci/bt8xx/bttv-driver.c78
-rw-r--r--drivers/media/pci/bt8xx/bttv-risc.c1
-rw-r--r--drivers/media/pci/cx23885/cx23885-core.c5
-rw-r--r--drivers/media/pci/cx25821/cx25821-core.c1
-rw-r--r--drivers/media/pci/cx88/cx88-mpeg.c3
-rw-r--r--drivers/media/pci/dm1105/dm1105.c14
-rw-r--r--drivers/media/pci/intel/ipu3/ipu3-cio2.c119
-rw-r--r--drivers/media/pci/intel/ipu3/ipu3-cio2.h157
-rw-r--r--drivers/media/pci/mantis/hopper_vp3028.c2
-rw-r--r--drivers/media/pci/saa7134/saa7134-video.c30
-rw-r--r--drivers/media/pci/saa7146/mxb.c19
-rw-r--r--drivers/media/pci/saa7164/saa7164-core.c17
-rw-r--r--drivers/media/pci/solo6x10/solo6x10-g723.c13
-rw-r--r--drivers/media/pci/solo6x10/solo6x10-p2m.c10
-rw-r--r--drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c35
-rw-r--r--drivers/media/pci/ttpci/av7110.c13
-rw-r--r--drivers/media/platform/Kconfig33
-rw-r--r--drivers/media/platform/Makefile3
-rw-r--r--drivers/media/platform/coda/coda-bit.c73
-rw-r--r--drivers/media/platform/coda/coda-common.c62
-rw-r--r--drivers/media/platform/coda/coda.h11
-rw-r--r--drivers/media/platform/davinci/isif.c11
-rw-r--r--drivers/media/platform/exynos4-is/fimc-capture.c6
-rw-r--r--drivers/media/platform/exynos4-is/fimc-core.c34
-rw-r--r--drivers/media/platform/exynos4-is/fimc-core.h18
-rw-r--r--drivers/media/platform/exynos4-is/fimc-is.c20
-rw-r--r--drivers/media/platform/exynos4-is/fimc-is.h6
-rw-r--r--drivers/media/platform/exynos4-is/fimc-lite-reg.c4
-rw-r--r--drivers/media/platform/exynos4-is/fimc-lite.c2
-rw-r--r--drivers/media/platform/exynos4-is/fimc-lite.h4
-rw-r--r--drivers/media/platform/exynos4-is/fimc-m2m.c8
-rw-r--r--drivers/media/platform/exynos4-is/fimc-reg.c18
-rw-r--r--drivers/media/platform/exynos4-is/fimc-reg.h4
-rw-r--r--drivers/media/platform/fsl-viu.c121
-rw-r--r--drivers/media/platform/marvell-ccic/mmp-driver.c6
-rw-r--r--drivers/media/platform/meson/ge2d/Makefile3
-rw-r--r--drivers/media/platform/meson/ge2d/ge2d-regs.h360
-rw-r--r--drivers/media/platform/meson/ge2d/ge2d.c1067
-rw-r--r--drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c9
-rw-r--r--drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c9
-rw-r--r--drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c19
-rw-r--r--drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c9
-rw-r--r--drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c28
-rw-r--r--drivers/media/platform/mtk-vpu/mtk_vpu.c101
-rw-r--r--drivers/media/platform/omap3isp/ispccdc.c5
-rw-r--r--drivers/media/platform/pxa_camera.c4
-rw-r--r--drivers/media/platform/qcom/camss/camss-csid.c9
-rw-r--r--drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c7
-rw-r--r--drivers/media/platform/qcom/camss/camss-csiphy.c25
-rw-r--r--drivers/media/platform/qcom/camss/camss-csiphy.h1
-rw-r--r--drivers/media/platform/qcom/camss/camss-ispif.c100
-rw-r--r--drivers/media/platform/qcom/camss/camss-ispif.h2
-rw-r--r--drivers/media/platform/qcom/camss/camss-vfe-4-7.c131
-rw-r--r--drivers/media/platform/qcom/camss/camss-vfe.c19
-rw-r--r--drivers/media/platform/qcom/camss/camss-vfe.h1
-rw-r--r--drivers/media/platform/qcom/camss/camss-video.c90
-rw-r--r--drivers/media/platform/qcom/camss/camss.c206
-rw-r--r--drivers/media/platform/qcom/camss/camss.h1
-rw-r--r--drivers/media/platform/qcom/venus/core.c41
-rw-r--r--drivers/media/platform/qcom/venus/core.h1
-rw-r--r--drivers/media/platform/qcom/venus/firmware.c17
-rw-r--r--drivers/media/platform/qcom/venus/hfi.c12
-rw-r--r--drivers/media/platform/qcom/venus/pm_helpers.c12
-rw-r--r--drivers/media/platform/qcom/venus/vdec.c32
-rw-r--r--drivers/media/platform/qcom/venus/venc.c2
-rw-r--r--drivers/media/platform/rcar-vin/rcar-core.c221
-rw-r--r--drivers/media/platform/rcar-vin/rcar-csi2.c18
-rw-r--r--drivers/media/platform/rcar-vin/rcar-dma.c171
-rw-r--r--drivers/media/platform/rcar-vin/rcar-v4l2.c12
-rw-r--r--drivers/media/platform/rcar-vin/rcar-vin.h23
-rw-r--r--drivers/media/platform/rockchip/rkisp1/Makefile10
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c1431
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-common.c37
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-common.h485
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c577
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c1160
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-params.c1572
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h1262
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c846
-rw-r--r--drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c415
-rw-r--r--drivers/media/platform/s3c-camif/camif-core.c6
-rw-r--r--drivers/media/platform/s5p-jpeg/jpeg-core.c2
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_dec.c2
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_enc.c2
-rw-r--r--drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c23
-rw-r--r--drivers/media/platform/stm32/stm32-dcmi.c63
-rw-r--r--drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c2
-rw-r--r--drivers/media/radio/radio-sf16fmr2.c2
-rw-r--r--drivers/media/radio/si4713/si4713.c2
-rw-r--r--drivers/media/rc/keymaps/Makefile2
-rw-r--r--drivers/media/rc/keymaps/rc-khamsin.c75
-rw-r--r--drivers/media/rc/keymaps/rc-pine64.c65
-rw-r--r--drivers/media/rc/lirc_dev.c3
-rw-r--r--drivers/media/rc/sunxi-cir.c50
-rw-r--r--drivers/media/test-drivers/vicodec/codec-fwht.c13
-rw-r--r--drivers/media/test-drivers/vicodec/codec-fwht.h32
-rw-r--r--drivers/media/test-drivers/vicodec/codec-v4l2-fwht.c88
-rw-r--r--drivers/media/test-drivers/vicodec/vicodec-core.c46
-rw-r--r--drivers/media/test-drivers/vim2m.c20
-rw-r--r--drivers/media/test-drivers/vivid/vivid-core.c66
-rw-r--r--drivers/media/test-drivers/vivid/vivid-core.h1
-rw-r--r--drivers/media/test-drivers/vivid/vivid-ctrls.c29
-rw-r--r--drivers/media/test-drivers/vivid/vivid-kthread-cap.c6
-rw-r--r--drivers/media/test-drivers/vivid/vivid-kthread-out.c6
-rw-r--r--drivers/media/test-drivers/vivid/vivid-kthread-touch.c6
-rw-r--r--drivers/media/test-drivers/vivid/vivid-sdr-cap.c6
-rw-r--r--drivers/media/test-drivers/vivid/vivid-vid-cap.c18
-rw-r--r--drivers/media/test-drivers/vivid/vivid-vid-out.c18
-rw-r--r--drivers/media/tuners/mt2060.c2
-rw-r--r--drivers/media/tuners/mt2063.c1
-rw-r--r--drivers/media/tuners/mxl5005s.c20
-rw-r--r--drivers/media/usb/au0828/au0828-video.c7
-rw-r--r--drivers/media/usb/cx231xx/cx231xx-audio.c2
-rw-r--r--drivers/media/usb/cx231xx/cx231xx-core.c10
-rw-r--r--drivers/media/usb/cx231xx/cx231xx-vbi.c5
-rw-r--r--drivers/media/usb/dvb-usb-v2/dvbsky.c22
-rw-r--r--drivers/media/usb/dvb-usb-v2/rtl28xxu.c4
-rw-r--r--drivers/media/usb/dvb-usb-v2/zd1301.c2
-rw-r--r--drivers/media/usb/dvb-usb/dib0700_devices.c4
-rw-r--r--drivers/media/usb/dvb-usb/dw2102.c8
-rw-r--r--drivers/media/usb/dvb-usb/gp8psk.c2
-rw-r--r--drivers/media/usb/em28xx/em28xx-audio.c14
-rw-r--r--drivers/media/usb/gspca/gspca.c1
-rw-r--r--drivers/media/usb/gspca/ov534.c12
-rw-r--r--drivers/media/usb/msi2500/msi2500.c4
-rw-r--r--drivers/media/usb/pvrusb2/pvrusb2-devattr.c2
-rw-r--r--drivers/media/usb/tm6000/tm6000-video.c7
-rw-r--r--drivers/media/usb/uvc/uvc_ctrl.c4
-rw-r--r--drivers/media/usb/zr364xx/zr364xx.c33
-rw-r--r--drivers/media/v4l2-core/v4l2-common.c33
-rw-r--r--drivers/media/v4l2-core/v4l2-compat-ioctl32.c1793
-rw-r--r--drivers/media/v4l2-core/v4l2-ctrls.c235
-rw-r--r--drivers/media/v4l2-core/v4l2-device.c3
-rw-r--r--drivers/media/v4l2-core/v4l2-fwnode.c32
-rw-r--r--drivers/media/v4l2-core/v4l2-ioctl.c184
-rw-r--r--drivers/media/v4l2-core/v4l2-subdev.c48
238 files changed, 23754 insertions, 7944 deletions
diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig
index a6d073f2e036..6222b3ae220b 100644
--- a/drivers/media/Kconfig
+++ b/drivers/media/Kconfig
@@ -24,7 +24,6 @@ if MEDIA_SUPPORT
config MEDIA_SUPPORT_FILTER
bool "Filter media drivers"
- depends on MEDIA_SUPPORT
default y if !EMBEDDED && !EXPERT
help
Configuring the media subsystem can be complex, as there are
diff --git a/drivers/media/cec/core/cec-core.c b/drivers/media/cec/core/cec-core.c
index ece236291f35..551689d371a7 100644
--- a/drivers/media/cec/core/cec-core.c
+++ b/drivers/media/cec/core/cec-core.c
@@ -166,12 +166,12 @@ static void cec_devnode_unregister(struct cec_adapter *adap)
mutex_unlock(&devnode->lock);
return;
}
+ devnode->registered = false;
+ devnode->unregistered = true;
list_for_each_entry(fh, &devnode->fhs, list)
wake_up_interruptible(&fh->wait);
- devnode->registered = false;
- devnode->unregistered = true;
mutex_unlock(&devnode->lock);
mutex_lock(&adap->lock);
diff --git a/drivers/media/common/cx2341x.c b/drivers/media/common/cx2341x.c
index 1f67e021138f..1392bd6b0026 100644
--- a/drivers/media/common/cx2341x.c
+++ b/drivers/media/common/cx2341x.c
@@ -166,7 +166,7 @@ static void cx2341x_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *ty
/* Must be sorted from low to high control ID! */
const u32 cx2341x_mpeg_ctrls[] = {
- V4L2_CID_MPEG_CLASS,
+ V4L2_CID_CODEC_CLASS,
V4L2_CID_MPEG_STREAM_TYPE,
V4L2_CID_MPEG_STREAM_VBI_FMT,
V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
@@ -574,7 +574,7 @@ int cx2341x_ctrl_query(const struct cx2341x_mpeg_params *params,
int err;
switch (qctrl->id) {
- case V4L2_CID_MPEG_CLASS:
+ case V4L2_CID_CODEC_CLASS:
return v4l2_ctrl_query_fill(qctrl, 0, 0, 0, 0);
case V4L2_CID_MPEG_STREAM_TYPE:
return v4l2_ctrl_query_fill(qctrl,
diff --git a/drivers/media/common/saa7146/saa7146_core.c b/drivers/media/common/saa7146/saa7146_core.c
index 21fb16cc5ca1..f2d13b71416c 100644
--- a/drivers/media/common/saa7146/saa7146_core.c
+++ b/drivers/media/common/saa7146/saa7146_core.c
@@ -177,7 +177,7 @@ void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa
goto err_free_slist;
pt->nents = pages;
- slen = pci_map_sg(pci,pt->slist,pt->nents,PCI_DMA_FROMDEVICE);
+ slen = dma_map_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE);
if (0 == slen)
goto err_free_pgtable;
@@ -187,7 +187,7 @@ void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa
return mem;
err_unmap_sg:
- pci_unmap_sg(pci, pt->slist, pt->nents, PCI_DMA_FROMDEVICE);
+ dma_unmap_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE);
err_free_pgtable:
saa7146_pgtable_free(pci, pt);
err_free_slist:
@@ -201,7 +201,7 @@ err_null:
void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt)
{
- pci_unmap_sg(pci, pt->slist, pt->nents, PCI_DMA_FROMDEVICE);
+ dma_unmap_sg(&pci->dev, pt->slist, pt->nents, DMA_FROM_DEVICE);
saa7146_pgtable_free(pci, pt);
kfree(pt->slist);
pt->slist = NULL;
@@ -212,7 +212,7 @@ void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt)
{
if (NULL == pt->cpu)
return;
- pci_free_consistent(pci, pt->size, pt->cpu, pt->dma);
+ dma_free_coherent(&pci->dev, pt->size, pt->cpu, pt->dma);
pt->cpu = NULL;
}
@@ -221,7 +221,7 @@ int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt)
__le32 *cpu;
dma_addr_t dma_addr = 0;
- cpu = pci_alloc_consistent(pci, PAGE_SIZE, &dma_addr);
+ cpu = dma_alloc_coherent(&pci->dev, PAGE_SIZE, &dma_addr, GFP_KERNEL);
if (NULL == cpu) {
return -ENOMEM;
}
@@ -412,18 +412,20 @@ static int saa7146_init_one(struct pci_dev *pci, const struct pci_device_id *ent
err = -ENOMEM;
/* get memory for various stuff */
- dev->d_rps0.cpu_addr = pci_zalloc_consistent(pci, SAA7146_RPS_MEM,
- &dev->d_rps0.dma_handle);
+ dev->d_rps0.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM,
+ &dev->d_rps0.dma_handle,
+ GFP_KERNEL);
if (!dev->d_rps0.cpu_addr)
goto err_free_irq;
- dev->d_rps1.cpu_addr = pci_zalloc_consistent(pci, SAA7146_RPS_MEM,
- &dev->d_rps1.dma_handle);
+ dev->d_rps1.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM,
+ &dev->d_rps1.dma_handle,
+ GFP_KERNEL);
if (!dev->d_rps1.cpu_addr)
goto err_free_rps0;
- dev->d_i2c.cpu_addr = pci_zalloc_consistent(pci, SAA7146_RPS_MEM,
- &dev->d_i2c.dma_handle);
+ dev->d_i2c.cpu_addr = dma_alloc_coherent(&pci->dev, SAA7146_RPS_MEM,
+ &dev->d_i2c.dma_handle, GFP_KERNEL);
if (!dev->d_i2c.cpu_addr)
goto err_free_rps1;
@@ -471,14 +473,14 @@ out:
return err;
err_free_i2c:
- pci_free_consistent(pci, SAA7146_RPS_MEM, dev->d_i2c.cpu_addr,
- dev->d_i2c.dma_handle);
+ dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_i2c.cpu_addr,
+ dev->d_i2c.dma_handle);
err_free_rps1:
- pci_free_consistent(pci, SAA7146_RPS_MEM, dev->d_rps1.cpu_addr,
- dev->d_rps1.dma_handle);
+ dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_rps1.cpu_addr,
+ dev->d_rps1.dma_handle);
err_free_rps0:
- pci_free_consistent(pci, SAA7146_RPS_MEM, dev->d_rps0.cpu_addr,
- dev->d_rps0.dma_handle);
+ dma_free_coherent(&pci->dev, SAA7146_RPS_MEM, dev->d_rps0.cpu_addr,
+ dev->d_rps0.dma_handle);
err_free_irq:
free_irq(pci->irq, (void *)dev);
err_unmap:
@@ -519,7 +521,8 @@ static void saa7146_remove_one(struct pci_dev *pdev)
free_irq(pdev->irq, dev);
for (p = dev_map; p->addr; p++)
- pci_free_consistent(pdev, SAA7146_RPS_MEM, p->addr, p->dma);
+ dma_free_coherent(&pdev->dev, SAA7146_RPS_MEM, p->addr,
+ p->dma);
iounmap(dev->mem);
pci_release_region(pdev, 0);
diff --git a/drivers/media/common/saa7146/saa7146_fops.c b/drivers/media/common/saa7146/saa7146_fops.c
index d6531874faa6..baf5772c52a9 100644
--- a/drivers/media/common/saa7146/saa7146_fops.c
+++ b/drivers/media/common/saa7146/saa7146_fops.c
@@ -55,8 +55,6 @@ void saa7146_dma_free(struct saa7146_dev *dev,struct videobuf_queue *q,
struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb);
DEB_EE("dev:%p, buf:%p\n", dev, buf);
- BUG_ON(in_interrupt());
-
videobuf_waiton(q, &buf->vb, 0, 0);
videobuf_dma_unmap(q->dev, dma);
videobuf_dma_free(dma);
@@ -517,8 +515,8 @@ int saa7146_vv_init(struct saa7146_dev* dev, struct saa7146_ext_vv *ext_vv)
dev->ext_vv_data = ext_vv;
vv->d_clipping.cpu_addr =
- pci_zalloc_consistent(dev->pci, SAA7146_CLIPPING_MEM,
- &vv->d_clipping.dma_handle);
+ dma_alloc_coherent(&dev->pci->dev, SAA7146_CLIPPING_MEM,
+ &vv->d_clipping.dma_handle, GFP_KERNEL);
if( NULL == vv->d_clipping.cpu_addr ) {
ERR("out of memory. aborting.\n");
kfree(vv);
@@ -576,7 +574,8 @@ int saa7146_vv_release(struct saa7146_dev* dev)
DEB_EE("dev:%p\n", dev);
v4l2_device_unregister(&dev->v4l2_dev);
- pci_free_consistent(dev->pci, SAA7146_CLIPPING_MEM, vv->d_clipping.cpu_addr, vv->d_clipping.dma_handle);
+ dma_free_coherent(&dev->pci->dev, SAA7146_CLIPPING_MEM,
+ vv->d_clipping.cpu_addr, vv->d_clipping.dma_handle);
v4l2_ctrl_handler_free(&dev->ctrl_handler);
kfree(vv);
dev->vv_data = NULL;
diff --git a/drivers/media/common/saa7146/saa7146_vbi.c b/drivers/media/common/saa7146/saa7146_vbi.c
index e1d369b976ed..bd442b984423 100644
--- a/drivers/media/common/saa7146/saa7146_vbi.c
+++ b/drivers/media/common/saa7146/saa7146_vbi.c
@@ -22,7 +22,7 @@ static int vbi_workaround(struct saa7146_dev *dev)
as specified. there is this workaround, but please
don't let me explain it. ;-) */
- cpu = pci_alloc_consistent(dev->pci, 4096, &dma_addr);
+ cpu = dma_alloc_coherent(&dev->pci->dev, 4096, &dma_addr, GFP_KERNEL);
if (NULL == cpu)
return -ENOMEM;
@@ -123,12 +123,12 @@ static int vbi_workaround(struct saa7146_dev *dev)
/* stop rps1 for sure */
saa7146_write(dev, MC1, MASK_29);
- pci_free_consistent(dev->pci, 4096, cpu, dma_addr);
+ dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr);
return -EINTR;
}
}
- pci_free_consistent(dev->pci, 4096, cpu, dma_addr);
+ dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr);
return 0;
}
diff --git a/drivers/media/common/saa7146/saa7146_video.c b/drivers/media/common/saa7146/saa7146_video.c
index ccd15b4d4920..7b8795eca589 100644
--- a/drivers/media/common/saa7146/saa7146_video.c
+++ b/drivers/media/common/saa7146/saa7146_video.c
@@ -771,10 +771,8 @@ static int vidioc_s_fmt_vid_overlay(struct file *file, void *__fh, struct v4l2_f
vv->ov.nclips = f->fmt.win.clipcount;
if (vv->ov.nclips > 16)
vv->ov.nclips = 16;
- if (copy_from_user(vv->ov.clips, f->fmt.win.clips,
- sizeof(struct v4l2_clip) * vv->ov.nclips)) {
- return -EFAULT;
- }
+ memcpy(vv->ov.clips, f->fmt.win.clips,
+ sizeof(struct v4l2_clip) * vv->ov.nclips);
/* vv->ov.fh is used to indicate that we have valid overlay information, too */
vv->ov.fh = fh;
diff --git a/drivers/media/common/siano/smsdvb-main.c b/drivers/media/common/siano/smsdvb-main.c
index 88f90dfd368b..ae17407e477a 100644
--- a/drivers/media/common/siano/smsdvb-main.c
+++ b/drivers/media/common/siano/smsdvb-main.c
@@ -1169,12 +1169,15 @@ static int smsdvb_hotplug(struct smscore_device_t *coredev,
rc = dvb_create_media_graph(&client->adapter, true);
if (rc < 0) {
pr_err("dvb_create_media_graph failed %d\n", rc);
- goto client_error;
+ goto media_graph_error;
}
pr_info("DVB interface registered.\n");
return 0;
+media_graph_error:
+ smsdvb_debugfs_release(client);
+
client_error:
dvb_unregister_frontend(&client->frontend);
diff --git a/drivers/media/dvb-core/dvbdev.c b/drivers/media/dvb-core/dvbdev.c
index 959fa2820259..5ff7bedee247 100644
--- a/drivers/media/dvb-core/dvbdev.c
+++ b/drivers/media/dvb-core/dvbdev.c
@@ -539,6 +539,9 @@ int dvb_register_device(struct dvb_adapter *adap, struct dvb_device **pdvbdev,
if (IS_ERR(clsdev)) {
pr_err("%s: failed to create device dvb%d.%s%d (%ld)\n",
__func__, adap->num, dnames[type], id, PTR_ERR(clsdev));
+ dvb_media_device_free(dvbdev);
+ kfree(dvbdevfops);
+ kfree(dvbdev);
return PTR_ERR(clsdev);
}
dprintk("DVB: register adapter%d/%s%d @ minor: %i (0x%02x)\n",
diff --git a/drivers/media/dvb-frontends/ascot2e.h b/drivers/media/dvb-frontends/ascot2e.h
index f886fab1283f..d86b3de85c6a 100644
--- a/drivers/media/dvb-frontends/ascot2e.h
+++ b/drivers/media/dvb-frontends/ascot2e.h
@@ -33,7 +33,7 @@ struct ascot2e_config {
#if IS_REACHABLE(CONFIG_DVB_ASCOT2E)
/**
- * Attach an ascot2e tuner
+ * ascot2e_attach - Attach an ascot2e tuner
*
* @fe: frontend to be attached
* @config: pointer to &struct ascot2e_config with tuner configuration.
diff --git a/drivers/media/dvb-frontends/cxd2820r.h b/drivers/media/dvb-frontends/cxd2820r.h
index a28b8754932b..4aa6cf4fb913 100644
--- a/drivers/media/dvb-frontends/cxd2820r.h
+++ b/drivers/media/dvb-frontends/cxd2820r.h
@@ -96,7 +96,7 @@ struct cxd2820r_config {
#if IS_REACHABLE(CONFIG_DVB_CXD2820R)
/**
- * Attach a cxd2820r demod
+ * cxd2820r_attach - Attach a cxd2820r demod
*
* @config: pointer to &struct cxd2820r_config with demod configuration.
* @i2c: i2c adapter to use.
diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c
index 237b9d04c076..37b32d9b398d 100644
--- a/drivers/media/dvb-frontends/drx39xyj/drxj.c
+++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c
@@ -2325,7 +2325,6 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16
default:
return -EINVAL;
- break;
}
/* Write command */
@@ -3594,7 +3593,6 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg
break;
default:
return -EINVAL;
- break;
} /* switch ( uio_cfg->mode ) */
break;
/*====================================================================*/
@@ -3618,7 +3616,6 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg
break;
default:
return -EINVAL;
- break;
} /* switch ( uio_cfg->mode ) */
break;
/*====================================================================*/
@@ -3642,7 +3639,6 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg
case DRX_UIO_MODE_FIRMWARE0:
default:
return -EINVAL;
- break;
} /* switch ( uio_cfg->mode ) */
break;
/*====================================================================*/
@@ -10953,7 +10949,6 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
default:
ext_attr->standard = DRX_STANDARD_UNKNOWN;
return -EINVAL;
- break;
}
return 0;
@@ -11074,7 +11069,6 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
default:
/* Unknow sleep mode */
return -EINVAL;
- break;
}
/* Check if device needs to be powered up */
@@ -11896,7 +11890,6 @@ static int drx_ctrl_u_code(struct drx_demod_instance *demod,
}
default:
return -EINVAL;
- break;
}
mc_data += mc_block_nr_bytes;
diff --git a/drivers/media/dvb-frontends/drxd_hard.c b/drivers/media/dvb-frontends/drxd_hard.c
index 45f982863904..a7eb81df88c2 100644
--- a/drivers/media/dvb-frontends/drxd_hard.c
+++ b/drivers/media/dvb-frontends/drxd_hard.c
@@ -1622,7 +1622,6 @@ static int CorrectSysClockDeviation(struct drxd_state *state)
break;
default:
return -1;
- break;
}
/* Compute new sysclock value
diff --git a/drivers/media/dvb-frontends/drxk.h b/drivers/media/dvb-frontends/drxk.h
index ee06e89187e4..69fdca00f364 100644
--- a/drivers/media/dvb-frontends/drxk.h
+++ b/drivers/media/dvb-frontends/drxk.h
@@ -54,7 +54,7 @@ struct drxk_config {
#if IS_REACHABLE(CONFIG_DVB_DRXK)
/**
- * Attach a drxk demod
+ * drxk_attach - Attach a drxk demod
*
* @config: pointer to &struct drxk_config with demod configuration.
* @i2c: i2c adapter to use.
diff --git a/drivers/media/dvb-frontends/dvb-pll.h b/drivers/media/dvb-frontends/dvb-pll.h
index 973a66a82e27..71838888743b 100644
--- a/drivers/media/dvb-frontends/dvb-pll.h
+++ b/drivers/media/dvb-frontends/dvb-pll.h
@@ -38,7 +38,7 @@ struct dvb_pll_config {
#if IS_REACHABLE(CONFIG_DVB_PLL)
/**
- * Attach a dvb-pll to the supplied frontend structure.
+ * dvb_pll_attach - Attach a dvb-pll to the supplied frontend structure.
*
* @fe: Frontend to attach to.
* @pll_addr: i2c address of the PLL (if used).
diff --git a/drivers/media/dvb-frontends/helene.h b/drivers/media/dvb-frontends/helene.h
index c026bdcf548d..32e0b1fb268c 100644
--- a/drivers/media/dvb-frontends/helene.h
+++ b/drivers/media/dvb-frontends/helene.h
@@ -44,7 +44,7 @@ struct helene_config {
#if IS_REACHABLE(CONFIG_DVB_HELENE)
/**
- * Attach a helene tuner (terrestrial and cable standards)
+ * helene_attach - Attach a helene tuner (terrestrial and cable standards)
*
* @fe: frontend to be attached
* @config: pointer to &struct helene_config with tuner configuration.
@@ -57,7 +57,7 @@ extern struct dvb_frontend *helene_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c);
/**
- * Attach a helene tuner (satellite standards)
+ * helene_attach_s - Attach a helene tuner (satellite standards)
*
* @fe: frontend to be attached
* @config: pointer to &struct helene_config with tuner configuration.
diff --git a/drivers/media/dvb-frontends/horus3a.h b/drivers/media/dvb-frontends/horus3a.h
index 366c399e3329..91dbe20169cd 100644
--- a/drivers/media/dvb-frontends/horus3a.h
+++ b/drivers/media/dvb-frontends/horus3a.h
@@ -33,7 +33,7 @@ struct horus3a_config {
#if IS_REACHABLE(CONFIG_DVB_HORUS3A)
/**
- * Attach a horus3a tuner
+ * horus3a_attach - Attach a horus3a tuner
*
* @fe: frontend to be attached
* @config: pointer to &struct helene_config with tuner configuration.
diff --git a/drivers/media/dvb-frontends/ix2505v.h b/drivers/media/dvb-frontends/ix2505v.h
index 671c0e0959f7..175569131365 100644
--- a/drivers/media/dvb-frontends/ix2505v.h
+++ b/drivers/media/dvb-frontends/ix2505v.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/**
+/*
* Driver for Sharp IX2505V (marked B0017) DVB-S silicon tuner
*
* Copyright (C) 2010 Malcolm Priestley
@@ -31,7 +31,7 @@ struct ix2505v_config {
#if IS_REACHABLE(CONFIG_DVB_IX2505V)
/**
- * Attach a ix2505v tuner to the supplied frontend structure.
+ * ix2505v_attach - Attach a ix2505v tuner to the supplied frontend structure.
*
* @fe: Frontend to attach to.
* @config: pointer to &struct ix2505v_config
diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c
index ad6d9d564a87..cfa4cdde99d8 100644
--- a/drivers/media/dvb-frontends/m88ds3103.c
+++ b/drivers/media/dvb-frontends/m88ds3103.c
@@ -1793,9 +1793,9 @@ static int m88ds3103_probe(struct i2c_client *client,
dev->config.lnb_en_pol = pdata->lnb_en_pol;
dev->cfg = &dev->config;
/* create regmap */
- dev->regmap_config.reg_bits = 8,
- dev->regmap_config.val_bits = 8,
- dev->regmap_config.lock_arg = dev,
+ dev->regmap_config.reg_bits = 8;
+ dev->regmap_config.val_bits = 8;
+ dev->regmap_config.lock_arg = dev;
dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
diff --git a/drivers/media/dvb-frontends/m88ds3103.h b/drivers/media/dvb-frontends/m88ds3103.h
index 46b722495e4c..e32b68c0df70 100644
--- a/drivers/media/dvb-frontends/m88ds3103.h
+++ b/drivers/media/dvb-frontends/m88ds3103.h
@@ -128,7 +128,7 @@ struct m88ds3103_config {
#if defined(CONFIG_DVB_M88DS3103) || \
(defined(CONFIG_DVB_M88DS3103_MODULE) && defined(MODULE))
/**
- * Attach a m88ds3103 demod
+ * m88ds3103_attach - Attach a m88ds3103 demod
*
* @config: pointer to &struct m88ds3103_config with demod configuration.
* @i2c: i2c adapter to use.
diff --git a/drivers/media/dvb-frontends/mb86a20s.h b/drivers/media/dvb-frontends/mb86a20s.h
index 00a6b6e9b5e4..d20d22bf7580 100644
--- a/drivers/media/dvb-frontends/mb86a20s.h
+++ b/drivers/media/dvb-frontends/mb86a20s.h
@@ -26,7 +26,7 @@ struct mb86a20s_config {
#if IS_REACHABLE(CONFIG_DVB_MB86A20S)
/**
- * Attach a mb86a20s demod
+ * mb86a20s_attach - Attach a mb86a20s demod
*
* @config: pointer to &struct mb86a20s_config with demod configuration.
* @i2c: i2c adapter to use.
diff --git a/drivers/media/dvb-frontends/nxt200x.c b/drivers/media/dvb-frontends/nxt200x.c
index 35b83b1dd82c..200b6dbc75f8 100644
--- a/drivers/media/dvb-frontends/nxt200x.c
+++ b/drivers/media/dvb-frontends/nxt200x.c
@@ -168,7 +168,6 @@ static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8*
break;
default:
return -EINVAL;
- break;
}
/* set multi register length */
@@ -190,7 +189,6 @@ static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8*
break;
default:
return -EINVAL;
- break;
}
pr_warn("Error writing multireg register 0x%02X\n", reg);
@@ -216,7 +214,6 @@ static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* d
/* read the actual data */
nxt200x_readbytes(state, reg, data, len);
return 0;
- break;
case NXT2004:
/* probably not right, but gives correct values */
attr = 0x02;
@@ -239,10 +236,8 @@ static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* d
nxt200x_readbytes(state, 0x36 + i, &data[i], 1);
}
return 0;
- break;
default:
return -EINVAL;
- break;
}
}
@@ -374,7 +369,6 @@ static int nxt200x_writetuner (struct nxt200x_state* state, u8* data)
break;
default:
return -EINVAL;
- break;
}
return 0;
}
@@ -555,7 +549,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
if (fe->ops.tuner_ops.calc_regs) {
@@ -580,7 +573,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
nxt200x_writebytes(state, 0x42, buf, 1);
@@ -594,7 +586,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
nxt200x_writebytes(state, 0x57, buf, 1);
@@ -610,7 +601,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
/* write sdmx input */
@@ -626,7 +616,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
buf[1] = 0x00;
switch (state->demod_chip) {
@@ -638,7 +627,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
/* write adc power lpf fc */
@@ -664,7 +652,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
/* write kg1 */
@@ -720,7 +707,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
nxt200x_writebytes(state, 0x30, buf, 1);
@@ -742,7 +728,6 @@ static int nxt200x_setup_frontend_parameters(struct dvb_frontend *fe)
break;
default:
return -EINVAL;
- break;
}
/* write agc control reg */
@@ -1114,7 +1099,6 @@ static int nxt200x_init(struct dvb_frontend* fe)
break;
default:
return -EINVAL;
- break;
}
state->initialised = 1;
}
diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c
index e5bffaaeed38..01dcc7f1b9b2 100644
--- a/drivers/media/dvb-frontends/rtl2832.c
+++ b/drivers/media/dvb-frontends/rtl2832.c
@@ -1056,13 +1056,13 @@ static int rtl2832_probe(struct i2c_client *client,
dev->sleeping = true;
INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
/* create regmap */
- dev->regmap_config.reg_bits = 8,
- dev->regmap_config.val_bits = 8,
- dev->regmap_config.volatile_reg = rtl2832_volatile_reg,
- dev->regmap_config.max_register = 5 * 0x100,
- dev->regmap_config.ranges = regmap_range_cfg,
- dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg),
- dev->regmap_config.cache_type = REGCACHE_NONE,
+ dev->regmap_config.reg_bits = 8;
+ dev->regmap_config.val_bits = 8;
+ dev->regmap_config.volatile_reg = rtl2832_volatile_reg;
+ dev->regmap_config.max_register = 5 * 0x100;
+ dev->regmap_config.ranges = regmap_range_cfg;
+ dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg);
+ dev->regmap_config.cache_type = REGCACHE_NONE;
dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
diff --git a/drivers/media/dvb-frontends/si2165.c b/drivers/media/dvb-frontends/si2165.c
index 3fdaef1935ef..ebee230afb7b 100644
--- a/drivers/media/dvb-frontends/si2165.c
+++ b/drivers/media/dvb-frontends/si2165.c
@@ -5,7 +5,7 @@
* Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
*
* References:
- * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
+ * https://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
*/
#include <linux/delay.h>
diff --git a/drivers/media/dvb-frontends/si2165.h b/drivers/media/dvb-frontends/si2165.h
index 0b19317f3a31..adc5e18754ad 100644
--- a/drivers/media/dvb-frontends/si2165.h
+++ b/drivers/media/dvb-frontends/si2165.h
@@ -5,7 +5,7 @@
* Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
*
* References:
- * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
+ * https://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
*/
#ifndef _DVB_SI2165_H
diff --git a/drivers/media/dvb-frontends/si21xx.c b/drivers/media/dvb-frontends/si21xx.c
index a116eff417f2..e31eb2c5cc4c 100644
--- a/drivers/media/dvb-frontends/si21xx.c
+++ b/drivers/media/dvb-frontends/si21xx.c
@@ -464,10 +464,8 @@ static int si21xx_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage volt)
switch (volt) {
case SEC_VOLTAGE_18:
return si21_writereg(state, LNB_CTRL_REG_1, val | 0x40);
- break;
case SEC_VOLTAGE_13:
return si21_writereg(state, LNB_CTRL_REG_1, (val & ~0x40));
- break;
default:
return -EINVAL;
}
diff --git a/drivers/media/dvb-frontends/stb6000.h b/drivers/media/dvb-frontends/stb6000.h
index 570a4b1d07d6..38da55af7ea9 100644
--- a/drivers/media/dvb-frontends/stb6000.h
+++ b/drivers/media/dvb-frontends/stb6000.h
@@ -15,7 +15,7 @@
#if IS_REACHABLE(CONFIG_DVB_STB6000)
/**
- * Attach a stb6000 tuner to the supplied frontend structure.
+ * stb6000_attach - Attach a stb6000 tuner to the supplied frontend structure.
*
* @fe: Frontend to attach to.
* @addr: i2c address of the tuner.
diff --git a/drivers/media/dvb-frontends/tda826x.h b/drivers/media/dvb-frontends/tda826x.h
index bb575a251b04..e1d33edbb8ec 100644
--- a/drivers/media/dvb-frontends/tda826x.h
+++ b/drivers/media/dvb-frontends/tda826x.h
@@ -14,7 +14,7 @@
#include <media/dvb_frontend.h>
/**
- * Attach a tda826x tuner to the supplied frontend structure.
+ * tda826x_attach - Attach a tda826x tuner to the supplied frontend structure.
*
* @fe: Frontend to attach to.
* @addr: i2c address of the tuner.
diff --git a/drivers/media/dvb-frontends/ts2020.c b/drivers/media/dvb-frontends/ts2020.c
index 234607b02edb..3e383912bcfd 100644
--- a/drivers/media/dvb-frontends/ts2020.c
+++ b/drivers/media/dvb-frontends/ts2020.c
@@ -569,11 +569,11 @@ static int ts2020_probe(struct i2c_client *client,
/* create regmap */
mutex_init(&dev->regmap_mutex);
- dev->regmap_config.reg_bits = 8,
- dev->regmap_config.val_bits = 8,
- dev->regmap_config.lock = ts2020_regmap_lock,
- dev->regmap_config.unlock = ts2020_regmap_unlock,
- dev->regmap_config.lock_arg = dev,
+ dev->regmap_config.reg_bits = 8;
+ dev->regmap_config.val_bits = 8;
+ dev->regmap_config.lock = ts2020_regmap_lock;
+ dev->regmap_config.unlock = ts2020_regmap_unlock;
+ dev->regmap_config.lock_arg = dev;
dev->regmap = regmap_init_i2c(client, &dev->regmap_config);
if (IS_ERR(dev->regmap)) {
ret = PTR_ERR(dev->regmap);
diff --git a/drivers/media/dvb-frontends/zl10036.h b/drivers/media/dvb-frontends/zl10036.h
index 91eea777eaf1..ad83e6344e7f 100644
--- a/drivers/media/dvb-frontends/zl10036.h
+++ b/drivers/media/dvb-frontends/zl10036.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/**
+/*
* Driver for Zarlink ZL10036 DVB-S silicon tuner
*
* Copyright (C) 2006 Tino Reichardt
@@ -19,7 +19,7 @@ struct zl10036_config {
#if IS_REACHABLE(CONFIG_DVB_ZL10036)
/**
- * Attach a zl10036 tuner to the supplied frontend structure.
+ * zl10036_attach - Attach a zl10036 tuner to the supplied frontend structure.
*
* @fe: Frontend to attach to.
* @config: zl10036_config structure.
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 878f66ef2719..2b9d81e4794a 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -722,7 +722,7 @@ menu "Camera sensor devices"
config VIDEO_APTINA_PLL
tristate
-config VIDEO_SMIAPP_PLL
+config VIDEO_CCS_PLL
tristate
config VIDEO_HI556
@@ -825,6 +825,19 @@ config VIDEO_IMX355
To compile this driver as a module, choose M here: the
module will be called imx355.
+config VIDEO_OV02A10
+ tristate "OmniVision OV02A10 sensor support"
+ depends on VIDEO_V4L2 && I2C
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ This is a Video4Linux2 sensor driver for the OmniVision
+ OV02A10 camera.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ov02a10.
+
config VIDEO_OV2640
tristate "OmniVision OV2640 sensor support"
depends on VIDEO_V4L2 && I2C
@@ -877,6 +890,7 @@ config VIDEO_OV2740
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
+ select REGMAP_I2C
help
This is a Video4Linux2 sensor driver for the OmniVision
OV2740 camera.
@@ -1050,6 +1064,20 @@ config VIDEO_OV9650
This is a V4L2 sensor driver for the Omnivision
OV9650 and OV9652 camera sensors.
+config VIDEO_OV9734
+ tristate "OmniVision OV9734 sensor support"
+ depends on VIDEO_V4L2 && I2C
+ depends on ACPI || COMPILE_TEST
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ This is a Video4Linux2 sensor driver for the OmniVision
+ OV9734 camera.
+
+ To compile this driver as a module, choose M here: the
+ module's name is ov9734.
+
config VIDEO_OV13858
tristate "OmniVision OV13858 sensor support"
depends on I2C && VIDEO_V4L2
@@ -1232,7 +1260,7 @@ config VIDEO_S5K5BAF
This is a V4L2 sensor driver for Samsung S5K5BAF 2M
camera sensor with an embedded SoC image signal processor.
-source "drivers/media/i2c/smiapp/Kconfig"
+source "drivers/media/i2c/ccs/Kconfig"
source "drivers/media/i2c/et8ek8/Kconfig"
config VIDEO_S5C73M3
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index f0a77473979d..a3149dce21bb 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -2,7 +2,7 @@
msp3400-objs := msp3400-driver.o msp3400-kthreads.o
obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o
-obj-$(CONFIG_VIDEO_SMIAPP) += smiapp/
+obj-$(CONFIG_VIDEO_CCS) += ccs/
obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/
obj-$(CONFIG_VIDEO_CX25840) += cx25840/
obj-$(CONFIG_VIDEO_M5MOLS) += m5mols/
@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o
obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o
obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o
+obj-$(CONFIG_VIDEO_OV02A10) += ov02a10.o
obj-$(CONFIG_VIDEO_OV2640) += ov2640.o
obj-$(CONFIG_VIDEO_OV2680) += ov2680.o
obj-$(CONFIG_VIDEO_OV2685) += ov2685.o
@@ -83,6 +84,7 @@ obj-$(CONFIG_VIDEO_OV7740) += ov7740.o
obj-$(CONFIG_VIDEO_OV8856) += ov8856.o
obj-$(CONFIG_VIDEO_OV9640) += ov9640.o
obj-$(CONFIG_VIDEO_OV9650) += ov9650.o
+obj-$(CONFIG_VIDEO_OV9734) += ov9734.o
obj-$(CONFIG_VIDEO_OV13858) += ov13858.o
obj-$(CONFIG_VIDEO_MT9M001) += mt9m001.o
obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o
@@ -104,7 +106,7 @@ obj-$(CONFIG_VIDEO_S5C73M3) += s5c73m3/
obj-$(CONFIG_VIDEO_ADP1653) += adp1653.o
obj-$(CONFIG_VIDEO_LM3560) += lm3560.o
obj-$(CONFIG_VIDEO_LM3646) += lm3646.o
-obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o
+obj-$(CONFIG_VIDEO_CCS_PLL) += ccs-pll.o
obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
obj-$(CONFIG_VIDEO_I2C) += video-i2c.o
diff --git a/drivers/media/i2c/ad5820.c b/drivers/media/i2c/ad5820.c
index 19c74db0649f..2958a4694461 100644
--- a/drivers/media/i2c/ad5820.c
+++ b/drivers/media/i2c/ad5820.c
@@ -270,8 +270,7 @@ static const struct v4l2_subdev_internal_ops ad5820_internal_ops = {
*/
static int __maybe_unused ad5820_suspend(struct device *dev)
{
- struct i2c_client *client = container_of(dev, struct i2c_client, dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
struct ad5820_device *coil = to_ad5820_device(subdev);
if (!coil->power_count)
@@ -282,8 +281,7 @@ static int __maybe_unused ad5820_suspend(struct device *dev)
static int __maybe_unused ad5820_resume(struct device *dev)
{
- struct i2c_client *client = container_of(dev, struct i2c_client, dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
struct ad5820_device *coil = to_ad5820_device(subdev);
if (!coil->power_count)
diff --git a/drivers/media/i2c/adp1653.c b/drivers/media/i2c/adp1653.c
index 694125a59f64..522a0b10e415 100644
--- a/drivers/media/i2c/adp1653.c
+++ b/drivers/media/i2c/adp1653.c
@@ -379,8 +379,7 @@ static const struct v4l2_subdev_internal_ops adp1653_internal_ops = {
static int adp1653_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
struct adp1653_flash *flash = to_adp1653_flash(subdev);
if (!flash->power_count)
@@ -391,8 +390,7 @@ static int adp1653_suspend(struct device *dev)
static int adp1653_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
struct adp1653_flash *flash = to_adp1653_flash(subdev);
if (!flash->power_count)
diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c
index 4498d14d3429..44bb6fe85644 100644
--- a/drivers/media/i2c/adv7180.c
+++ b/drivers/media/i2c/adv7180.c
@@ -1454,8 +1454,7 @@ MODULE_DEVICE_TABLE(i2c, adv7180_id);
#ifdef CONFIG_PM_SLEEP
static int adv7180_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct adv7180_state *state = to_state(sd);
return adv7180_set_power(state, false);
@@ -1463,8 +1462,7 @@ static int adv7180_suspend(struct device *dev)
static int adv7180_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct adv7180_state *state = to_state(sd);
int ret;
diff --git a/drivers/media/i2c/adv748x/adv748x-afe.c b/drivers/media/i2c/adv748x/adv748x-afe.c
index dbbb1e4d6363..4052cf67bf16 100644
--- a/drivers/media/i2c/adv748x/adv748x-afe.c
+++ b/drivers/media/i2c/adv748x/adv748x-afe.c
@@ -154,7 +154,7 @@ static void adv748x_afe_set_video_standard(struct adv748x_state *state,
(sdpstd & 0xf) << ADV748X_SDP_VID_SEL_SHIFT);
}
-static int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input)
+int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input)
{
struct adv748x_state *state = adv748x_afe_to_state(afe);
@@ -520,10 +520,6 @@ int adv748x_afe_init(struct adv748x_afe *afe)
}
}
- adv748x_afe_s_input(afe, afe->input);
-
- adv_dbg(state, "AFE Default input set to %d\n", afe->input);
-
/* Entity pads and sinks are 0-indexed to match the pads */
for (i = ADV748X_AFE_SINK_AIN0; i <= ADV748X_AFE_SINK_AIN7; i++)
afe->pads[i].flags = MEDIA_PAD_FL_SINK;
diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
index 1fe7f97c6d52..4e54148147b9 100644
--- a/drivers/media/i2c/adv748x/adv748x-core.c
+++ b/drivers/media/i2c/adv748x/adv748x-core.c
@@ -198,7 +198,7 @@ static int adv748x_initialise_clients(struct adv748x_state *state)
return ret;
}
- return adv748x_set_slave_addresses(state);
+ return 0;
}
/**
@@ -516,6 +516,10 @@ static int adv748x_reset(struct adv748x_state *state)
if (ret)
return ret;
+ adv748x_afe_s_input(&state->afe, state->afe.input);
+
+ adv_dbg(state, "AFE Default input set to %d\n", state->afe.input);
+
/* Reset TXA and TXB */
adv748x_tx_power(&state->txa, 1);
adv748x_tx_power(&state->txa, 0);
@@ -526,10 +530,14 @@ static int adv748x_reset(struct adv748x_state *state)
io_write(state, ADV748X_IO_PD, ADV748X_IO_PD_RX_EN);
/* Conditionally enable TXa and TXb. */
- if (is_tx_enabled(&state->txa))
+ if (is_tx_enabled(&state->txa)) {
regval |= ADV748X_IO_10_CSI4_EN;
- if (is_tx_enabled(&state->txb))
+ adv748x_csi2_set_virtual_channel(&state->txa, 0);
+ }
+ if (is_tx_enabled(&state->txb)) {
regval |= ADV748X_IO_10_CSI1_EN;
+ adv748x_csi2_set_virtual_channel(&state->txb, 0);
+ }
io_write(state, ADV748X_IO_10, regval);
/* Use vid_std and v_freq as freerun resolution for CP */
@@ -558,6 +566,18 @@ static int adv748x_identify_chip(struct adv748x_state *state)
}
/* -----------------------------------------------------------------------------
+ * Suspend / Resume
+ */
+
+static int __maybe_unused adv748x_resume_early(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct adv748x_state *state = i2c_get_clientdata(client);
+
+ return adv748x_reset(state);
+}
+
+/* -----------------------------------------------------------------------------
* i2c driver
*/
@@ -589,14 +609,13 @@ static int adv748x_parse_csi2_lanes(struct adv748x_state *state,
unsigned int port,
struct device_node *ep)
{
- struct v4l2_fwnode_endpoint vep;
+ struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY };
unsigned int num_lanes;
int ret;
if (port != ADV748X_PORT_TXA && port != ADV748X_PORT_TXB)
return 0;
- vep.bus_type = V4L2_MBUS_CSI2_DPHY;
ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &vep);
if (ret)
return ret;
@@ -820,10 +839,15 @@ static const struct of_device_id adv748x_of_table[] = {
};
MODULE_DEVICE_TABLE(of, adv748x_of_table);
+static const struct dev_pm_ops adv748x_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, adv748x_resume_early)
+};
+
static struct i2c_driver adv748x_driver = {
.driver = {
.name = "adv748x",
.of_match_table = adv748x_of_table,
+ .pm = &adv748x_pm_ops,
},
.probe_new = adv748x_probe,
.remove = adv748x_remove,
diff --git a/drivers/media/i2c/adv748x/adv748x-csi2.c b/drivers/media/i2c/adv748x/adv748x-csi2.c
index 99bb63d05eef..fa9278a08fde 100644
--- a/drivers/media/i2c/adv748x/adv748x-csi2.c
+++ b/drivers/media/i2c/adv748x/adv748x-csi2.c
@@ -14,8 +14,7 @@
#include "adv748x.h"
-static int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx,
- unsigned int vc)
+int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc)
{
return tx_write(tx, ADV748X_CSI_VC_REF, vc << ADV748X_CSI_VC_REF_SHIFT);
}
@@ -313,9 +312,6 @@ int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx)
if (!is_tx_enabled(tx))
return 0;
- /* Initialise the virtual channel */
- adv748x_csi2_set_virtual_channel(tx, 0);
-
adv748x_subdev_init(&tx->sd, state, &adv748x_csi2_ops,
MEDIA_ENT_F_VID_IF_BRIDGE,
is_txa(tx) ? "txa" : "txb");
diff --git a/drivers/media/i2c/adv748x/adv748x.h b/drivers/media/i2c/adv748x/adv748x.h
index 1061f425ece5..56256c1e8b0d 100644
--- a/drivers/media/i2c/adv748x/adv748x.h
+++ b/drivers/media/i2c/adv748x/adv748x.h
@@ -435,9 +435,11 @@ int adv748x_tx_power(struct adv748x_csi2 *tx, bool on);
int adv748x_afe_init(struct adv748x_afe *afe);
void adv748x_afe_cleanup(struct adv748x_afe *afe);
+int adv748x_afe_s_input(struct adv748x_afe *afe, unsigned int input);
int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
+int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, unsigned int vc);
int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
diff --git a/drivers/media/i2c/ak7375.c b/drivers/media/i2c/ak7375.c
index 7b14b11605ca..e1f94ee0f48f 100644
--- a/drivers/media/i2c/ak7375.c
+++ b/drivers/media/i2c/ak7375.c
@@ -196,9 +196,7 @@ static int ak7375_remove(struct i2c_client *client)
*/
static int __maybe_unused ak7375_vcm_suspend(struct device *dev)
{
-
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ak7375_device *ak7375_dev = sd_to_ak7375_vcm(sd);
int ret, val;
@@ -233,8 +231,7 @@ static int __maybe_unused ak7375_vcm_suspend(struct device *dev)
*/
static int __maybe_unused ak7375_vcm_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ak7375_device *ak7375_dev = sd_to_ak7375_vcm(sd);
int ret, val;
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
new file mode 100644
index 000000000000..eb7b6f01f623
--- /dev/null
+++ b/drivers/media/i2c/ccs-pll.c
@@ -0,0 +1,886 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * drivers/media/i2c/ccs-pll.c
+ *
+ * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#include <linux/device.h>
+#include <linux/gcd.h>
+#include <linux/lcm.h>
+#include <linux/module.h>
+
+#include "ccs-pll.h"
+
+/* Return an even number or one. */
+static inline uint32_t clk_div_even(uint32_t a)
+{
+ return max_t(uint32_t, 1, a & ~1);
+}
+
+/* Return an even number or one. */
+static inline uint32_t clk_div_even_up(uint32_t a)
+{
+ if (a == 1)
+ return 1;
+ return (a + 1) & ~1;
+}
+
+static inline uint32_t is_one_or_even(uint32_t a)
+{
+ if (a == 1)
+ return 1;
+ if (a & 1)
+ return 0;
+
+ return 1;
+}
+
+static inline uint32_t one_or_more(uint32_t a)
+{
+ return a ?: 1;
+}
+
+static int bounds_check(struct device *dev, uint32_t val,
+ uint32_t min, uint32_t max, const char *prefix,
+ char *str)
+{
+ if (val >= min && val <= max)
+ return 0;
+
+ dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix,
+ str, val, min, max);
+
+ return -EINVAL;
+}
+
+#define PLL_OP 1
+#define PLL_VT 2
+
+static const char *pll_string(unsigned int which)
+{
+ switch (which) {
+ case PLL_OP:
+ return "op";
+ case PLL_VT:
+ return "vt";
+ }
+
+ return NULL;
+}
+
+#define PLL_FL(f) CCS_PLL_FLAG_##f
+
+static void print_pll(struct device *dev, struct ccs_pll *pll)
+{
+ const struct {
+ struct ccs_pll_branch_fr *fr;
+ struct ccs_pll_branch_bk *bk;
+ unsigned int which;
+ } branches[] = {
+ { &pll->vt_fr, &pll->vt_bk, PLL_VT },
+ { &pll->op_fr, &pll->op_bk, PLL_OP }
+ }, *br;
+ unsigned int i;
+
+ dev_dbg(dev, "ext_clk_freq_hz\t\t%u\n", pll->ext_clk_freq_hz);
+
+ for (i = 0, br = branches; i < ARRAY_SIZE(branches); i++, br++) {
+ const char *s = pll_string(br->which);
+
+ if (pll->flags & CCS_PLL_FLAG_DUAL_PLL ||
+ br->which == PLL_VT) {
+ dev_dbg(dev, "%s_pre_pll_clk_div\t\t%u\n", s,
+ br->fr->pre_pll_clk_div);
+ dev_dbg(dev, "%s_pll_multiplier\t\t%u\n", s,
+ br->fr->pll_multiplier);
+
+ dev_dbg(dev, "%s_pll_ip_clk_freq_hz\t%u\n", s,
+ br->fr->pll_ip_clk_freq_hz);
+ dev_dbg(dev, "%s_pll_op_clk_freq_hz\t%u\n", s,
+ br->fr->pll_op_clk_freq_hz);
+ }
+
+ if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) ||
+ br->which == PLL_VT) {
+ dev_dbg(dev, "%s_sys_clk_div\t\t%u\n", s,
+ br->bk->sys_clk_div);
+ dev_dbg(dev, "%s_pix_clk_div\t\t%u\n", s,
+ br->bk->pix_clk_div);
+
+ dev_dbg(dev, "%s_sys_clk_freq_hz\t%u\n", s,
+ br->bk->sys_clk_freq_hz);
+ dev_dbg(dev, "%s_pix_clk_freq_hz\t%u\n", s,
+ br->bk->pix_clk_freq_hz);
+ }
+ }
+
+ dev_dbg(dev, "pixel rate in pixel array:\t%u\n",
+ pll->pixel_rate_pixel_array);
+ dev_dbg(dev, "pixel rate on CSI-2 bus:\t%u\n",
+ pll->pixel_rate_csi);
+
+ dev_dbg(dev, "flags%s%s%s%s%s%s%s%s%s\n",
+ pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
+ pll->flags & PLL_FL(LINK_DECOUPLED) ? " link-decoupled" : "",
+ pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
+ " ext-ip-pll-divider" : "",
+ pll->flags & PLL_FL(FLEXIBLE_OP_PIX_CLK_DIV) ?
+ " flexible-op-pix-div" : "",
+ pll->flags & PLL_FL(FIFO_DERATING) ? " fifo-derating" : "",
+ pll->flags & PLL_FL(FIFO_OVERRATING) ? " fifo-overrating" : "",
+ pll->flags & PLL_FL(DUAL_PLL) ? " dual-pll" : "",
+ pll->flags & PLL_FL(OP_SYS_DDR) ? " op-sys-ddr" : "",
+ pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : "");
+}
+
+static uint32_t op_sys_ddr(uint32_t flags)
+{
+ return flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0;
+}
+
+static uint32_t op_pix_ddr(uint32_t flags)
+{
+ return flags & CCS_PLL_FLAG_OP_PIX_DDR ? 1 : 0;
+}
+
+static int check_fr_bounds(struct device *dev,
+ const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll, unsigned int which)
+{
+ const struct ccs_pll_branch_limits_fr *lim_fr;
+ struct ccs_pll_branch_fr *pll_fr;
+ const char *s = pll_string(which);
+ int rval;
+
+ if (which == PLL_OP) {
+ lim_fr = &lim->op_fr;
+ pll_fr = &pll->op_fr;
+ } else {
+ lim_fr = &lim->vt_fr;
+ pll_fr = &pll->vt_fr;
+ }
+
+ rval = bounds_check(dev, pll_fr->pre_pll_clk_div,
+ lim_fr->min_pre_pll_clk_div,
+ lim_fr->max_pre_pll_clk_div, s, "pre_pll_clk_div");
+
+ if (!rval)
+ rval = bounds_check(dev, pll_fr->pll_ip_clk_freq_hz,
+ lim_fr->min_pll_ip_clk_freq_hz,
+ lim_fr->max_pll_ip_clk_freq_hz,
+ s, "pll_ip_clk_freq_hz");
+ if (!rval)
+ rval = bounds_check(dev, pll_fr->pll_multiplier,
+ lim_fr->min_pll_multiplier,
+ lim_fr->max_pll_multiplier,
+ s, "pll_multiplier");
+ if (!rval)
+ rval = bounds_check(dev, pll_fr->pll_op_clk_freq_hz,
+ lim_fr->min_pll_op_clk_freq_hz,
+ lim_fr->max_pll_op_clk_freq_hz,
+ s, "pll_op_clk_freq_hz");
+
+ return rval;
+}
+
+static int check_bk_bounds(struct device *dev,
+ const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll, unsigned int which)
+{
+ const struct ccs_pll_branch_limits_bk *lim_bk;
+ struct ccs_pll_branch_bk *pll_bk;
+ const char *s = pll_string(which);
+ int rval;
+
+ if (which == PLL_OP) {
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
+ return 0;
+
+ lim_bk = &lim->op_bk;
+ pll_bk = &pll->op_bk;
+ } else {
+ lim_bk = &lim->vt_bk;
+ pll_bk = &pll->vt_bk;
+ }
+
+ rval = bounds_check(dev, pll_bk->sys_clk_div,
+ lim_bk->min_sys_clk_div,
+ lim_bk->max_sys_clk_div, s, "op_sys_clk_div");
+ if (!rval)
+ rval = bounds_check(dev, pll_bk->sys_clk_freq_hz,
+ lim_bk->min_sys_clk_freq_hz,
+ lim_bk->max_sys_clk_freq_hz,
+ s, "sys_clk_freq_hz");
+ if (!rval)
+ rval = bounds_check(dev, pll_bk->sys_clk_div,
+ lim_bk->min_sys_clk_div,
+ lim_bk->max_sys_clk_div,
+ s, "sys_clk_div");
+ if (!rval)
+ rval = bounds_check(dev, pll_bk->pix_clk_freq_hz,
+ lim_bk->min_pix_clk_freq_hz,
+ lim_bk->max_pix_clk_freq_hz,
+ s, "pix_clk_freq_hz");
+
+ return rval;
+}
+
+static int check_ext_bounds(struct device *dev, struct ccs_pll *pll)
+{
+ if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING) &&
+ pll->pixel_rate_pixel_array > pll->pixel_rate_csi) {
+ dev_dbg(dev, "device does not support derating\n");
+ return -EINVAL;
+ }
+
+ if (!(pll->flags & CCS_PLL_FLAG_FIFO_OVERRATING) &&
+ pll->pixel_rate_pixel_array < pll->pixel_rate_csi) {
+ dev_dbg(dev, "device does not support overrating\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void
+ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
+ uint16_t min_vt_div, uint16_t max_vt_div,
+ uint16_t *min_sys_div, uint16_t *max_sys_div)
+{
+ /*
+ * Find limits for sys_clk_div. Not all values are possible with all
+ * values of pix_clk_div.
+ */
+ *min_sys_div = lim->vt_bk.min_sys_clk_div;
+ dev_dbg(dev, "min_sys_div: %u\n", *min_sys_div);
+ *min_sys_div = max_t(uint16_t, *min_sys_div,
+ DIV_ROUND_UP(min_vt_div,
+ lim->vt_bk.max_pix_clk_div));
+ dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", *min_sys_div);
+ *min_sys_div = max_t(uint16_t, *min_sys_div,
+ pll_fr->pll_op_clk_freq_hz
+ / lim->vt_bk.max_sys_clk_freq_hz);
+ dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", *min_sys_div);
+ *min_sys_div = clk_div_even_up(*min_sys_div);
+ dev_dbg(dev, "min_sys_div: one or even: %u\n", *min_sys_div);
+
+ *max_sys_div = lim->vt_bk.max_sys_clk_div;
+ dev_dbg(dev, "max_sys_div: %u\n", *max_sys_div);
+ *max_sys_div = min_t(uint16_t, *max_sys_div,
+ DIV_ROUND_UP(max_vt_div,
+ lim->vt_bk.min_pix_clk_div));
+ dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", *max_sys_div);
+ *max_sys_div = min_t(uint16_t, *max_sys_div,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.min_pix_clk_freq_hz));
+ dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", *max_sys_div);
+}
+
+#define CPHY_CONST 7
+#define DPHY_CONST 16
+#define PHY_CONST_DIV 16
+
+static inline int
+__ccs_pll_calculate_vt_tree(struct device *dev,
+ const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll, uint32_t mul, uint32_t div)
+{
+ const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
+ const struct ccs_pll_branch_limits_bk *lim_bk = &lim->vt_bk;
+ struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
+ struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk;
+ uint32_t more_mul;
+ uint16_t best_pix_div = SHRT_MAX >> 1, best_div;
+ uint16_t vt_div, min_sys_div, max_sys_div, sys_div;
+
+ pll_fr->pll_ip_clk_freq_hz =
+ pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div;
+
+ dev_dbg(dev, "vt_pll_ip_clk_freq_hz %u\n", pll_fr->pll_ip_clk_freq_hz);
+
+ more_mul = one_or_more(DIV_ROUND_UP(lim_fr->min_pll_op_clk_freq_hz,
+ pll_fr->pll_ip_clk_freq_hz * mul));
+
+ dev_dbg(dev, "more_mul: %u\n", more_mul);
+ more_mul *= DIV_ROUND_UP(lim_fr->min_pll_multiplier, mul * more_mul);
+ dev_dbg(dev, "more_mul2: %u\n", more_mul);
+
+ pll_fr->pll_multiplier = mul * more_mul;
+
+ if (pll_fr->pll_multiplier * pll_fr->pll_ip_clk_freq_hz >
+ lim_fr->max_pll_op_clk_freq_hz)
+ return -EINVAL;
+
+ pll_fr->pll_op_clk_freq_hz =
+ pll_fr->pll_ip_clk_freq_hz * pll_fr->pll_multiplier;
+
+ vt_div = div * more_mul;
+
+ ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, vt_div, vt_div,
+ &min_sys_div, &max_sys_div);
+
+ max_sys_div = (vt_div & 1) ? 1 : max_sys_div;
+
+ dev_dbg(dev, "vt min/max_sys_div: %u,%u\n", min_sys_div, max_sys_div);
+
+ for (sys_div = min_sys_div; sys_div <= max_sys_div;
+ sys_div += 2 - (sys_div & 1)) {
+ uint16_t pix_div;
+
+ if (vt_div % sys_div)
+ continue;
+
+ pix_div = vt_div / sys_div;
+
+ if (pix_div < lim_bk->min_pix_clk_div ||
+ pix_div > lim_bk->max_pix_clk_div) {
+ dev_dbg(dev,
+ "pix_div %u too small or too big (%u--%u)\n",
+ pix_div,
+ lim_bk->min_pix_clk_div,
+ lim_bk->max_pix_clk_div);
+ continue;
+ }
+
+ dev_dbg(dev, "sys/pix/best_pix: %u,%u,%u\n", sys_div, pix_div,
+ best_pix_div);
+
+ if (pix_div * sys_div <= best_pix_div) {
+ best_pix_div = pix_div;
+ best_div = pix_div * sys_div;
+ }
+ }
+ if (best_pix_div == SHRT_MAX >> 1)
+ return -EINVAL;
+
+ pll_bk->sys_clk_div = best_div / best_pix_div;
+ pll_bk->pix_clk_div = best_pix_div;
+
+ pll_bk->sys_clk_freq_hz =
+ pll_fr->pll_op_clk_freq_hz / pll_bk->sys_clk_div;
+ pll_bk->pix_clk_freq_hz =
+ pll_bk->sys_clk_freq_hz / pll_bk->pix_clk_div;
+
+ pll->pixel_rate_pixel_array =
+ pll_bk->pix_clk_freq_hz * pll->vt_lanes;
+
+ return 0;
+}
+
+static int ccs_pll_calculate_vt_tree(struct device *dev,
+ const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll)
+{
+ const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr;
+ struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr;
+ uint16_t min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div;
+ uint16_t max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div;
+ uint32_t pre_mul, pre_div;
+
+ pre_div = gcd(pll->pixel_rate_csi,
+ pll->ext_clk_freq_hz * pll->vt_lanes);
+ pre_mul = pll->pixel_rate_csi / pre_div;
+ pre_div = pll->ext_clk_freq_hz * pll->vt_lanes / pre_div;
+
+ /* Make sure PLL input frequency is within limits */
+ max_pre_pll_clk_div =
+ min_t(uint16_t, max_pre_pll_clk_div,
+ DIV_ROUND_UP(pll->ext_clk_freq_hz,
+ lim_fr->min_pll_ip_clk_freq_hz));
+
+ min_pre_pll_clk_div = max_t(uint16_t, min_pre_pll_clk_div,
+ pll->ext_clk_freq_hz /
+ lim_fr->max_pll_ip_clk_freq_hz);
+
+ dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n",
+ min_pre_pll_clk_div, max_pre_pll_clk_div);
+
+ for (pll_fr->pre_pll_clk_div = min_pre_pll_clk_div;
+ pll_fr->pre_pll_clk_div <= max_pre_pll_clk_div;
+ pll_fr->pre_pll_clk_div +=
+ (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
+ 2 - (pll_fr->pre_pll_clk_div & 1)) {
+ uint32_t mul, div;
+ int rval;
+
+ div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div);
+ mul = pre_mul * pll_fr->pre_pll_clk_div / div;
+ div = pre_div / div;
+
+ dev_dbg(dev, "vt pre-div/mul/div: %u,%u,%u\n",
+ pll_fr->pre_pll_clk_div, mul, div);
+
+ rval = __ccs_pll_calculate_vt_tree(dev, lim, pll,
+ mul, div);
+ if (rval)
+ continue;
+
+ rval = check_fr_bounds(dev, lim, pll, PLL_VT);
+ if (rval)
+ continue;
+
+ rval = check_bk_bounds(dev, lim, pll, PLL_VT);
+ if (rval)
+ continue;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static void
+ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
+ const struct ccs_pll_branch_limits_bk *op_lim_bk,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
+ struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
+ uint32_t phy_const)
+{
+ uint16_t sys_div;
+ uint16_t best_pix_div = SHRT_MAX >> 1;
+ uint16_t vt_op_binning_div;
+ uint16_t min_vt_div, max_vt_div, vt_div;
+ uint16_t min_sys_div, max_sys_div;
+
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
+ goto out_calc_pixel_rate;
+
+ /*
+ * Find out whether a sensor supports derating. If it does not, VT and
+ * OP domains are required to run at the same pixel rate.
+ */
+ if (!(pll->flags & CCS_PLL_FLAG_FIFO_DERATING)) {
+ min_vt_div =
+ op_pll_bk->sys_clk_div * op_pll_bk->pix_clk_div
+ * pll->vt_lanes * phy_const / pll->op_lanes
+ / (PHY_CONST_DIV << op_pix_ddr(pll->flags));
+ } else {
+ /*
+ * Some sensors perform analogue binning and some do this
+ * digitally. The ones doing this digitally can be roughly be
+ * found out using this formula. The ones doing this digitally
+ * should run at higher clock rate, so smaller divisor is used
+ * on video timing side.
+ */
+ if (lim->min_line_length_pck_bin > lim->min_line_length_pck
+ / pll->binning_horizontal)
+ vt_op_binning_div = pll->binning_horizontal;
+ else
+ vt_op_binning_div = 1;
+ dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
+
+ /*
+ * Profile 2 supports vt_pix_clk_div E [4, 10]
+ *
+ * Horizontal binning can be used as a base for difference in
+ * divisors. One must make sure that horizontal blanking is
+ * enough to accommodate the CSI-2 sync codes.
+ *
+ * Take scaling factor and number of VT lanes into account as well.
+ *
+ * Find absolute limits for the factor of vt divider.
+ */
+ dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
+ min_vt_div =
+ DIV_ROUND_UP(pll->bits_per_pixel
+ * op_pll_bk->sys_clk_div * pll->scale_n
+ * pll->vt_lanes * phy_const,
+ (pll->flags &
+ CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ pll->csi2.lanes : 1)
+ * vt_op_binning_div * pll->scale_m
+ * PHY_CONST_DIV << op_pix_ddr(pll->flags));
+ }
+
+ /* Find smallest and biggest allowed vt divisor. */
+ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
+ min_vt_div = max_t(uint16_t, min_vt_div,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.max_pix_clk_freq_hz));
+ dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
+ min_vt_div);
+ min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div
+ * lim->vt_bk.min_sys_clk_div);
+ dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
+
+ max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div;
+ dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
+ max_vt_div = min_t(uint16_t, max_vt_div,
+ DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz,
+ lim->vt_bk.min_pix_clk_freq_hz));
+ dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
+ max_vt_div);
+
+ ccs_pll_find_vt_sys_div(dev, lim, pll, pll_fr, min_vt_div,
+ max_vt_div, &min_sys_div, &max_sys_div);
+
+ /*
+ * Find pix_div such that a legal pix_div * sys_div results
+ * into a value which is not smaller than div, the desired
+ * divisor.
+ */
+ for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) {
+ uint16_t __max_sys_div = vt_div & 1 ? 1 : max_sys_div;
+
+ for (sys_div = min_sys_div; sys_div <= __max_sys_div;
+ sys_div += 2 - (sys_div & 1)) {
+ uint16_t pix_div;
+ uint16_t rounded_div;
+
+ pix_div = DIV_ROUND_UP(vt_div, sys_div);
+
+ if (pix_div < lim->vt_bk.min_pix_clk_div
+ || pix_div > lim->vt_bk.max_pix_clk_div) {
+ dev_dbg(dev,
+ "pix_div %u too small or too big (%u--%u)\n",
+ pix_div,
+ lim->vt_bk.min_pix_clk_div,
+ lim->vt_bk.max_pix_clk_div);
+ continue;
+ }
+
+ rounded_div = roundup(vt_div, best_pix_div);
+
+ /* Check if this one is better. */
+ if (pix_div * sys_div <= rounded_div)
+ best_pix_div = pix_div;
+
+ /* Bail out if we've already found the best value. */
+ if (vt_div == rounded_div)
+ break;
+ }
+ if (best_pix_div < SHRT_MAX >> 1)
+ break;
+ }
+
+ pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
+ pll->vt_bk.pix_clk_div = best_pix_div;
+
+ pll->vt_bk.sys_clk_freq_hz =
+ pll_fr->pll_op_clk_freq_hz / pll->vt_bk.sys_clk_div;
+ pll->vt_bk.pix_clk_freq_hz =
+ pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
+
+out_calc_pixel_rate:
+ pll->pixel_rate_pixel_array =
+ pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
+}
+
+/*
+ * Heuristically guess the PLL tree for a given common multiplier and
+ * divisor. Begin with the operational timing and continue to video
+ * timing once operational timing has been verified.
+ *
+ * @mul is the PLL multiplier and @div is the common divisor
+ * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
+ * multiplier will be a multiple of @mul.
+ *
+ * @return Zero on success, error code on error.
+ */
+static int
+ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
+ const struct ccs_pll_branch_limits_fr *op_lim_fr,
+ const struct ccs_pll_branch_limits_bk *op_lim_bk,
+ struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
+ struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
+ uint32_t div, uint32_t op_sys_clk_freq_hz_sdr, uint32_t l,
+ bool cphy, uint32_t phy_const)
+{
+ /*
+ * Higher multipliers (and divisors) are often required than
+ * necessitated by the external clock and the output clocks.
+ * There are limits for all values in the clock tree. These
+ * are the minimum and maximum multiplier for mul.
+ */
+ uint32_t more_mul_min, more_mul_max;
+ uint32_t more_mul_factor;
+ uint32_t i;
+
+ /*
+ * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
+ * too high.
+ */
+ dev_dbg(dev, "op_pre_pll_clk_div %u\n", op_pll_fr->pre_pll_clk_div);
+
+ /* Don't go above max pll multiplier. */
+ more_mul_max = op_lim_fr->max_pll_multiplier / mul;
+ dev_dbg(dev, "more_mul_max: max_op_pll_multiplier check: %u\n",
+ more_mul_max);
+ /* Don't go above max pll op frequency. */
+ more_mul_max =
+ min_t(uint32_t,
+ more_mul_max,
+ op_lim_fr->max_pll_op_clk_freq_hz
+ / (pll->ext_clk_freq_hz /
+ op_pll_fr->pre_pll_clk_div * mul));
+ dev_dbg(dev, "more_mul_max: max_pll_op_clk_freq_hz check: %u\n",
+ more_mul_max);
+ /* Don't go above the division capability of op sys clock divider. */
+ more_mul_max = min(more_mul_max,
+ op_lim_bk->max_sys_clk_div * op_pll_fr->pre_pll_clk_div
+ / div);
+ dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
+ more_mul_max);
+ /* Ensure we won't go above max_pll_multiplier. */
+ more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul);
+ dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
+ more_mul_max);
+
+ /* Ensure we won't go below min_pll_op_clk_freq_hz. */
+ more_mul_min = DIV_ROUND_UP(op_lim_fr->min_pll_op_clk_freq_hz,
+ pll->ext_clk_freq_hz /
+ op_pll_fr->pre_pll_clk_div * mul);
+ dev_dbg(dev, "more_mul_min: min_op_pll_op_clk_freq_hz check: %u\n",
+ more_mul_min);
+ /* Ensure we won't go below min_pll_multiplier. */
+ more_mul_min = max(more_mul_min,
+ DIV_ROUND_UP(op_lim_fr->min_pll_multiplier, mul));
+ dev_dbg(dev, "more_mul_min: min_op_pll_multiplier check: %u\n",
+ more_mul_min);
+
+ if (more_mul_min > more_mul_max) {
+ dev_dbg(dev,
+ "unable to compute more_mul_min and more_mul_max\n");
+ return -EINVAL;
+ }
+
+ more_mul_factor = lcm(div, op_pll_fr->pre_pll_clk_div) / div;
+ dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
+ more_mul_factor = lcm(more_mul_factor, op_lim_bk->min_sys_clk_div);
+ dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
+ more_mul_factor);
+ i = roundup(more_mul_min, more_mul_factor);
+ if (!is_one_or_even(i))
+ i <<= 1;
+
+ dev_dbg(dev, "final more_mul: %u\n", i);
+ if (i > more_mul_max) {
+ dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
+ return -EINVAL;
+ }
+
+ op_pll_fr->pll_multiplier = mul * i;
+ op_pll_bk->sys_clk_div = div * i / op_pll_fr->pre_pll_clk_div;
+ dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll_bk->sys_clk_div);
+
+ op_pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
+ / op_pll_fr->pre_pll_clk_div;
+
+ op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
+ * op_pll_fr->pll_multiplier;
+
+ if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
+ op_pll_bk->pix_clk_div =
+ (pll->bits_per_pixel
+ * pll->op_lanes * (phy_const << op_sys_ddr(pll->flags))
+ / PHY_CONST_DIV / pll->csi2.lanes / l)
+ >> op_pix_ddr(pll->flags);
+ else
+ op_pll_bk->pix_clk_div =
+ (pll->bits_per_pixel
+ * (phy_const << op_sys_ddr(pll->flags))
+ / PHY_CONST_DIV / l) >> op_pix_ddr(pll->flags);
+
+ op_pll_bk->pix_clk_freq_hz =
+ (op_sys_clk_freq_hz_sdr >> op_pix_ddr(pll->flags))
+ / op_pll_bk->pix_clk_div;
+ op_pll_bk->sys_clk_freq_hz =
+ op_sys_clk_freq_hz_sdr >> op_sys_ddr(pll->flags);
+
+ dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
+
+ return 0;
+}
+
+int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
+ struct ccs_pll *pll)
+{
+ const struct ccs_pll_branch_limits_fr *op_lim_fr;
+ const struct ccs_pll_branch_limits_bk *op_lim_bk;
+ struct ccs_pll_branch_fr *op_pll_fr;
+ struct ccs_pll_branch_bk *op_pll_bk;
+ bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY;
+ uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST;
+ uint32_t op_sys_clk_freq_hz_sdr;
+ uint16_t min_op_pre_pll_clk_div;
+ uint16_t max_op_pre_pll_clk_div;
+ uint32_t mul, div;
+ uint32_t l = (!pll->op_bits_per_lane ||
+ pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2;
+ uint32_t i;
+ int rval = -EINVAL;
+
+ if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) {
+ pll->op_lanes = 1;
+ pll->vt_lanes = 1;
+ }
+
+ if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
+ op_lim_fr = &lim->op_fr;
+ op_lim_bk = &lim->op_bk;
+ op_pll_fr = &pll->op_fr;
+ op_pll_bk = &pll->op_bk;
+ } else if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
+ /*
+ * If there's no OP PLL at all, use the VT values
+ * instead. The OP values are ignored for the rest of
+ * the PLL calculation.
+ */
+ op_lim_fr = &lim->vt_fr;
+ op_lim_bk = &lim->vt_bk;
+ op_pll_fr = &pll->vt_fr;
+ op_pll_bk = &pll->vt_bk;
+ } else {
+ op_lim_fr = &lim->vt_fr;
+ op_lim_bk = &lim->op_bk;
+ op_pll_fr = &pll->vt_fr;
+ op_pll_bk = &pll->op_bk;
+ }
+
+ if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel ||
+ !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m ||
+ !op_lim_fr->min_pll_ip_clk_freq_hz ||
+ !op_lim_fr->max_pll_ip_clk_freq_hz ||
+ !op_lim_fr->min_pll_op_clk_freq_hz ||
+ !op_lim_fr->max_pll_op_clk_freq_hz ||
+ !op_lim_bk->max_sys_clk_div || !op_lim_fr->max_pll_multiplier)
+ return -EINVAL;
+
+ /*
+ * Make sure op_pix_clk_div will be integer --- unless flexible
+ * op_pix_clk_div is supported
+ */
+ if (!(pll->flags & CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV) &&
+ (pll->bits_per_pixel * pll->op_lanes) %
+ (pll->csi2.lanes * l << op_pix_ddr(pll->flags))) {
+ dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n",
+ pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
+ dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
+
+ dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
+ pll->binning_vertical);
+
+ switch (pll->bus_type) {
+ case CCS_PLL_BUS_TYPE_CSI2_DPHY:
+ /* CSI transfers 2 bits per clock per lane; thus times 2 */
+ op_sys_clk_freq_hz_sdr = pll->link_freq * 2
+ * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ 1 : pll->csi2.lanes);
+ break;
+ case CCS_PLL_BUS_TYPE_CSI2_CPHY:
+ op_sys_clk_freq_hz_sdr =
+ pll->link_freq
+ * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ 1 : pll->csi2.lanes);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ pll->pixel_rate_csi =
+ div_u64((uint64_t)op_sys_clk_freq_hz_sdr
+ * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ pll->csi2.lanes : 1) * PHY_CONST_DIV,
+ phy_const * pll->bits_per_pixel * l);
+
+ /* Figure out limits for OP pre-pll divider based on extclk */
+ dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
+ op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
+ max_op_pre_pll_clk_div =
+ min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div,
+ clk_div_even(pll->ext_clk_freq_hz /
+ op_lim_fr->min_pll_ip_clk_freq_hz));
+ min_op_pre_pll_clk_div =
+ max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div,
+ clk_div_even_up(
+ DIV_ROUND_UP(pll->ext_clk_freq_hz,
+ op_lim_fr->max_pll_ip_clk_freq_hz)));
+ dev_dbg(dev, "pre-pll check: min / max op_pre_pll_clk_div: %u / %u\n",
+ min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
+
+ i = gcd(op_sys_clk_freq_hz_sdr,
+ pll->ext_clk_freq_hz << op_pix_ddr(pll->flags));
+ mul = op_sys_clk_freq_hz_sdr / i;
+ div = (pll->ext_clk_freq_hz << op_pix_ddr(pll->flags)) / i;
+ dev_dbg(dev, "mul %u / div %u\n", mul, div);
+
+ min_op_pre_pll_clk_div =
+ max_t(uint16_t, min_op_pre_pll_clk_div,
+ clk_div_even_up(
+ mul /
+ one_or_more(
+ DIV_ROUND_UP(op_lim_fr->max_pll_op_clk_freq_hz,
+ pll->ext_clk_freq_hz))));
+ dev_dbg(dev, "pll_op check: min / max op_pre_pll_clk_div: %u / %u\n",
+ min_op_pre_pll_clk_div, max_op_pre_pll_clk_div);
+
+ for (op_pll_fr->pre_pll_clk_div = min_op_pre_pll_clk_div;
+ op_pll_fr->pre_pll_clk_div <= max_op_pre_pll_clk_div;
+ op_pll_fr->pre_pll_clk_div +=
+ (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
+ 2 - (op_pll_fr->pre_pll_clk_div & 1)) {
+ rval = ccs_pll_calculate_op(dev, lim, op_lim_fr, op_lim_bk, pll,
+ op_pll_fr, op_pll_bk, mul, div,
+ op_sys_clk_freq_hz_sdr, l, cphy,
+ phy_const);
+ if (rval)
+ continue;
+
+ rval = check_fr_bounds(dev, lim, pll,
+ pll->flags & CCS_PLL_FLAG_DUAL_PLL ?
+ PLL_OP : PLL_VT);
+ if (rval)
+ continue;
+
+ rval = check_bk_bounds(dev, lim, pll, PLL_OP);
+ if (rval)
+ continue;
+
+ if (pll->flags & CCS_PLL_FLAG_DUAL_PLL)
+ break;
+
+ ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
+ op_pll_bk, cphy, phy_const);
+
+ rval = check_bk_bounds(dev, lim, pll, PLL_VT);
+ if (rval)
+ continue;
+ rval = check_ext_bounds(dev, pll);
+ if (rval)
+ continue;
+
+ break;
+ }
+
+ if (rval) {
+ dev_dbg(dev, "unable to compute pre_pll divisor\n");
+
+ return rval;
+ }
+
+ if (pll->flags & CCS_PLL_FLAG_DUAL_PLL) {
+ rval = ccs_pll_calculate_vt_tree(dev, lim, pll);
+
+ if (rval)
+ return rval;
+ }
+
+ print_pll(dev, pll);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ccs_pll_calculate);
+
+MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
+MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
new file mode 100644
index 000000000000..b97d7ff50ea5
--- /dev/null
+++ b/drivers/media/i2c/ccs-pll.h
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * drivers/media/i2c/ccs-pll.h
+ *
+ * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#ifndef CCS_PLL_H
+#define CCS_PLL_H
+
+#include <linux/bits.h>
+
+/* CSI-2 or CCP-2 */
+#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00
+#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01
+
+/* Old SMIA and implementation specific flags */
+/* op pix clock is for all lanes in total normally */
+#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
+#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
+/* CCS PLL flags */
+#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
+#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)
+#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
+#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)
+#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)
+#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)
+#define CCS_PLL_FLAG_DUAL_PLL BIT(8)
+#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9)
+#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10)
+
+/**
+ * struct ccs_pll_branch_fr - CCS PLL configuration (front)
+ *
+ * A single branch front-end of the CCS PLL tree.
+ *
+ * @pre_pll_clk_div: Pre-PLL clock divisor
+ * @pll_multiplier: PLL multiplier
+ * @pll_ip_clk_freq_hz: PLL input clock frequency
+ * @pll_op_clk_freq_hz: PLL output clock frequency
+ */
+struct ccs_pll_branch_fr {
+ uint16_t pre_pll_clk_div;
+ uint16_t pll_multiplier;
+ uint32_t pll_ip_clk_freq_hz;
+ uint32_t pll_op_clk_freq_hz;
+};
+
+/**
+ * struct ccs_pll_branch_bk - CCS PLL configuration (back)
+ *
+ * A single branch back-end of the CCS PLL tree.
+ *
+ * @sys_clk_div: System clock divider
+ * @pix_clk_div: Pixel clock divider
+ * @sys_clk_freq_hz: System clock frequency
+ * @pix_clk_freq_hz: Pixel clock frequency
+ */
+struct ccs_pll_branch_bk {
+ uint16_t sys_clk_div;
+ uint16_t pix_clk_div;
+ uint32_t sys_clk_freq_hz;
+ uint32_t pix_clk_freq_hz;
+};
+
+/**
+ * struct ccs_pll - Full CCS PLL configuration
+ *
+ * All information required to calculate CCS PLL configuration.
+ *
+ * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
+ * @op_lanes: Number of operational lanes (input)
+ * @vt_lanes: Number of video timing lanes (input)
+ * @csi2: CSI-2 related parameters
+ * @csi2.lanes: The number of the CSI-2 data lanes (input)
+ * @binning_vertical: Vertical binning factor (input)
+ * @binning_horizontal: Horizontal binning factor (input)
+ * @scale_m: Downscaling factor, M component, [16, max] (input)
+ * @scale_n: Downscaling factor, N component, typically 16 (input)
+ * @bits_per_pixel: Bits per pixel on the output data bus (input)
+ * @op_bits_per_lane: Number of bits per OP lane (input)
+ * @flags: CCS_PLL_FLAG_* (input)
+ * @link_freq: Chosen link frequency (input)
+ * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
+ * (input)
+ * @vt_fr: Video timing front-end configuration (output)
+ * @vt_bk: Video timing back-end configuration (output)
+ * @op_fr: Operational timing front-end configuration (output)
+ * @op_bk: Operational timing back-end configuration (output)
+ * @pixel_rate_csi: Pixel rate on the output data bus (output)
+ * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array
+ * (output)
+ */
+struct ccs_pll {
+ /* input values */
+ uint8_t bus_type;
+ uint8_t op_lanes;
+ uint8_t vt_lanes;
+ struct {
+ uint8_t lanes;
+ } csi2;
+ uint8_t binning_horizontal;
+ uint8_t binning_vertical;
+ uint8_t scale_m;
+ uint8_t scale_n;
+ uint8_t bits_per_pixel;
+ uint8_t op_bits_per_lane;
+ uint16_t flags;
+ uint32_t link_freq;
+ uint32_t ext_clk_freq_hz;
+
+ /* output values */
+ struct ccs_pll_branch_fr vt_fr;
+ struct ccs_pll_branch_bk vt_bk;
+ struct ccs_pll_branch_fr op_fr;
+ struct ccs_pll_branch_bk op_bk;
+
+ uint32_t pixel_rate_csi;
+ uint32_t pixel_rate_pixel_array;
+};
+
+/**
+ * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits
+ *
+ * @min_pre_pll_clk_div: Minimum pre-PLL clock divider
+ * @max_pre_pll_clk_div: Maximum pre-PLL clock divider
+ * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency
+ * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency
+ * @min_pll_multiplier: Minimum PLL multiplier
+ * @max_pll_multiplier: Maximum PLL multiplier
+ * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency
+ * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency
+ */
+struct ccs_pll_branch_limits_fr {
+ uint16_t min_pre_pll_clk_div;
+ uint16_t max_pre_pll_clk_div;
+ uint32_t min_pll_ip_clk_freq_hz;
+ uint32_t max_pll_ip_clk_freq_hz;
+ uint16_t min_pll_multiplier;
+ uint16_t max_pll_multiplier;
+ uint32_t min_pll_op_clk_freq_hz;
+ uint32_t max_pll_op_clk_freq_hz;
+};
+
+/**
+ * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits
+ *
+ * @min_sys_clk_div: Minimum system clock divider
+ * @max_sys_clk_div: Maximum system clock divider
+ * @min_sys_clk_freq_hz: Minimum system clock frequency
+ * @max_sys_clk_freq_hz: Maximum system clock frequency
+ * @min_pix_clk_div: Minimum pixel clock divider
+ * @max_pix_clk_div: Maximum pixel clock divider
+ * @min_pix_clk_freq_hz: Minimum pixel clock frequency
+ * @max_pix_clk_freq_hz: Maximum pixel clock frequency
+ */
+struct ccs_pll_branch_limits_bk {
+ uint16_t min_sys_clk_div;
+ uint16_t max_sys_clk_div;
+ uint32_t min_sys_clk_freq_hz;
+ uint32_t max_sys_clk_freq_hz;
+ uint16_t min_pix_clk_div;
+ uint16_t max_pix_clk_div;
+ uint32_t min_pix_clk_freq_hz;
+ uint32_t max_pix_clk_freq_hz;
+};
+
+/**
+ * struct ccs_pll_limits - CCS PLL limits
+ *
+ * @min_ext_clk_freq_hz: Minimum external clock frequency
+ * @max_ext_clk_freq_hz: Maximum external clock frequency
+ * @vt_fr: Video timing front-end limits
+ * @vt_bk: Video timing back-end limits
+ * @op_fr: Operational timing front-end limits
+ * @op_bk: Operational timing back-end limits
+ * @min_line_length_pck_bin: Minimum line length in pixels, with binning
+ * @min_line_length_pck: Minimum line length in pixels without binning
+ */
+struct ccs_pll_limits {
+ /* Strict PLL limits */
+ uint32_t min_ext_clk_freq_hz;
+ uint32_t max_ext_clk_freq_hz;
+
+ struct ccs_pll_branch_limits_fr vt_fr;
+ struct ccs_pll_branch_limits_bk vt_bk;
+ struct ccs_pll_branch_limits_fr op_fr;
+ struct ccs_pll_branch_limits_bk op_bk;
+
+ /* Other relevant limits */
+ uint32_t min_line_length_pck_bin;
+ uint32_t min_line_length_pck;
+};
+
+struct device;
+
+/**
+ * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters
+ *
+ * @dev: Device pointer, used for printing messages
+ * @limits: Limits specific to the sensor
+ * @pll: Given PLL configuration
+ *
+ * Calculate the CCS PLL configuration based on the limits as well as given
+ * device specific, system specific or user configured input data.
+ */
+int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
+ struct ccs_pll *pll);
+
+#endif /* CCS_PLL_H */
diff --git a/drivers/media/i2c/ccs/Kconfig b/drivers/media/i2c/ccs/Kconfig
new file mode 100644
index 000000000000..59f35b33ddc1
--- /dev/null
+++ b/drivers/media/i2c/ccs/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_CCS
+ tristate "MIPI CCS/SMIA++/SMIA sensor support"
+ depends on I2C && VIDEO_V4L2 && HAVE_CLK
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select VIDEO_CCS_PLL
+ select V4L2_FWNODE
+ help
+ This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant
+ camera sensors.
diff --git a/drivers/media/i2c/ccs/Makefile b/drivers/media/i2c/ccs/Makefile
new file mode 100644
index 000000000000..44601ba8cd53
--- /dev/null
+++ b/drivers/media/i2c/ccs/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+ccs-objs += ccs-core.o ccs-reg-access.o \
+ ccs-quirk.o ccs-limits.o ccs-data.o
+obj-$(CONFIG_VIDEO_CCS) += ccs.o
+
+ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
new file mode 100644
index 000000000000..b39ae5f8446b
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -0,0 +1,3479 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * drivers/media/i2c/ccs/ccs-core.c
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2010--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ *
+ * Based on smiapp driver by Vimarsh Zutshi
+ * Based on jt8ev1.c by Vimarsh Zutshi
+ * Based on smia-sensor.c by Tuukka Toivonen <tuukkat76@gmail.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/firmware.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/smiapp.h>
+#include <linux/v4l2-mediabus.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-device.h>
+
+#include "ccs.h"
+
+#define CCS_ALIGN_DIM(dim, flags) \
+ ((flags) & V4L2_SEL_FLAG_GE \
+ ? ALIGN((dim), 2) \
+ : (dim) & ~1)
+
+static struct ccs_limit_offset {
+ u16 lim;
+ u16 info;
+} ccs_limit_offsets[CCS_L_LAST + 1];
+
+/*
+ * ccs_module_idents - supported camera modules
+ */
+static const struct ccs_module_ident ccs_module_idents[] = {
+ CCS_IDENT_L(0x01, 0x022b, -1, "vs6555"),
+ CCS_IDENT_L(0x01, 0x022e, -1, "vw6558"),
+ CCS_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
+ CCS_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"),
+ CCS_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"),
+ CCS_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk),
+ CCS_IDENT_L(0x0c, 0x213e, -1, "et8en2"),
+ CCS_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"),
+ CCS_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk),
+ CCS_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk),
+ CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
+};
+
+#define CCS_DEVICE_FLAG_IS_SMIA BIT(0)
+
+struct ccs_device {
+ unsigned char flags;
+};
+
+static const char * const ccs_regulators[] = { "vcore", "vio", "vana" };
+
+/*
+ *
+ * Dynamic Capability Identification
+ *
+ */
+
+static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
+{
+ switch (width) {
+ case sizeof(u8):
+ *(u8 *)ptr = val;
+ break;
+ case sizeof(u16):
+ *(u16 *)ptr = val;
+ break;
+ case sizeof(u32):
+ *(u32 *)ptr = val;
+ break;
+ }
+}
+
+static int ccs_limit_ptr(struct ccs_sensor *sensor, unsigned int limit,
+ unsigned int offset, void **__ptr)
+{
+ const struct ccs_limit *linfo;
+
+ if (WARN_ON(limit >= CCS_L_LAST))
+ return -EINVAL;
+
+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
+
+ if (WARN_ON(!sensor->ccs_limits) ||
+ WARN_ON(offset + ccs_reg_width(linfo->reg) >
+ ccs_limit_offsets[limit + 1].lim))
+ return -EINVAL;
+
+ *__ptr = sensor->ccs_limits + ccs_limit_offsets[limit].lim + offset;
+
+ return 0;
+}
+
+void ccs_replace_limit(struct ccs_sensor *sensor,
+ unsigned int limit, unsigned int offset, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ const struct ccs_limit *linfo;
+ void *ptr;
+ int ret;
+
+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
+ if (ret)
+ return;
+
+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
+
+ dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %d, 0x%x\n",
+ linfo->reg, linfo->name, offset, val, val);
+
+ ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
+}
+
+u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,
+ unsigned int offset)
+{
+ void *ptr;
+ u32 val;
+ int ret;
+
+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
+ if (ret)
+ return 0;
+
+ switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) {
+ case sizeof(u8):
+ val = *(u8 *)ptr;
+ break;
+ case sizeof(u16):
+ val = *(u16 *)ptr;
+ break;
+ case sizeof(u32):
+ val = *(u32 *)ptr;
+ break;
+ default:
+ WARN_ON(1);
+ return 0;
+ }
+
+ return ccs_reg_conv(sensor, ccs_limits[limit].reg, val);
+}
+
+static int ccs_read_all_limits(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ void *ptr, *alloc, *end;
+ unsigned int i, l;
+ int ret;
+
+ kfree(sensor->ccs_limits);
+ sensor->ccs_limits = NULL;
+
+ alloc = kzalloc(ccs_limit_offsets[CCS_L_LAST].lim, GFP_KERNEL);
+ if (!alloc)
+ return -ENOMEM;
+
+ end = alloc + ccs_limit_offsets[CCS_L_LAST].lim;
+
+ for (i = 0, l = 0, ptr = alloc; ccs_limits[i].size; i++) {
+ u32 reg = ccs_limits[i].reg;
+ unsigned int width = ccs_reg_width(reg);
+ unsigned int j;
+
+ if (l == CCS_L_LAST) {
+ dev_err(&client->dev,
+ "internal error --- end of limit array\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ for (j = 0; j < ccs_limits[i].size / width;
+ j++, reg += width, ptr += width) {
+ u32 val;
+
+ ret = ccs_read_addr_noconv(sensor, reg, &val);
+ if (ret)
+ goto out_err;
+
+ if (ptr + width > end) {
+ dev_err(&client->dev,
+ "internal error --- no room for regs\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ if (!val && j)
+ break;
+
+ ccs_assign_limit(ptr, width, val);
+
+ dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
+ reg, ccs_limits[i].name, val, val);
+ }
+
+ if (ccs_limits[i].flags & CCS_L_FL_SAME_REG)
+ continue;
+
+ l++;
+ ptr = alloc + ccs_limit_offsets[l].lim;
+ }
+
+ if (l != CCS_L_LAST) {
+ dev_err(&client->dev,
+ "internal error --- insufficient limits\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ sensor->ccs_limits = alloc;
+
+ if (CCS_LIM(sensor, SCALER_N_MIN) < 16)
+ ccs_replace_limit(sensor, CCS_L_SCALER_N_MIN, 0, 16);
+
+ return 0;
+
+out_err:
+ kfree(alloc);
+
+ return ret;
+}
+
+static int ccs_read_frame_fmt(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
+ unsigned int i;
+ int pixel_count = 0;
+ int line_count = 0;
+
+ fmt_model_type = CCS_LIM(sensor, FRAME_FORMAT_MODEL_TYPE);
+ fmt_model_subtype = CCS_LIM(sensor, FRAME_FORMAT_MODEL_SUBTYPE);
+
+ ncol_desc = (fmt_model_subtype
+ & CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK)
+ >> CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT;
+ nrow_desc = fmt_model_subtype
+ & CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK;
+
+ dev_dbg(&client->dev, "format_model_type %s\n",
+ fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE
+ ? "2 byte" :
+ fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE
+ ? "4 byte" : "is simply bad");
+
+ dev_dbg(&client->dev, "%u column and %u row descriptors\n",
+ ncol_desc, nrow_desc);
+
+ for (i = 0; i < ncol_desc + nrow_desc; i++) {
+ u32 desc;
+ u32 pixelcode;
+ u32 pixels;
+ char *which;
+ char *what;
+
+ if (fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE) {
+ desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR, i);
+
+ pixelcode =
+ (desc
+ & CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK)
+ >> CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT;
+ pixels = desc & CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK;
+ } else if (fmt_model_type
+ == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE) {
+ desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR_4, i);
+
+ pixelcode =
+ (desc
+ & CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK)
+ >> CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT;
+ pixels = desc &
+ CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK;
+ } else {
+ dev_dbg(&client->dev,
+ "invalid frame format model type %d\n",
+ fmt_model_type);
+ return -EINVAL;
+ }
+
+ if (i < ncol_desc)
+ which = "columns";
+ else
+ which = "rows";
+
+ switch (pixelcode) {
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
+ what = "embedded";
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL:
+ what = "dummy";
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL:
+ what = "black";
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL:
+ what = "dark";
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
+ what = "visible";
+ break;
+ default:
+ what = "invalid";
+ break;
+ }
+
+ dev_dbg(&client->dev,
+ "%s pixels: %d %s (pixelcode %u)\n",
+ what, pixels, which, pixelcode);
+
+ if (i < ncol_desc) {
+ if (pixelcode ==
+ CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL)
+ sensor->visible_pixel_start = pixel_count;
+ pixel_count += pixels;
+ continue;
+ }
+
+ /* Handle row descriptors */
+ switch (pixelcode) {
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
+ if (sensor->embedded_end)
+ break;
+ sensor->embedded_start = line_count;
+ sensor->embedded_end = line_count + pixels;
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
+ sensor->image_start = line_count;
+ break;
+ }
+ line_count += pixels;
+ }
+
+ if (sensor->embedded_end > sensor->image_start) {
+ dev_dbg(&client->dev,
+ "adjusting image start line to %u (was %u)\n",
+ sensor->embedded_end, sensor->image_start);
+ sensor->image_start = sensor->embedded_end;
+ }
+
+ dev_dbg(&client->dev, "embedded data from lines %d to %d\n",
+ sensor->embedded_start, sensor->embedded_end);
+ dev_dbg(&client->dev, "image data starts at line %d\n",
+ sensor->image_start);
+
+ return 0;
+}
+
+static int ccs_pll_configure(struct ccs_sensor *sensor)
+{
+ struct ccs_pll *pll = &sensor->pll;
+ int rval;
+
+ rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt_bk.pix_clk_div);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt_bk.sys_clk_div);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->vt_fr.pre_pll_clk_div);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, PLL_MULTIPLIER, pll->vt_fr.pll_multiplier);
+ if (rval < 0)
+ return rval;
+
+ /* Lane op clock ratio does not apply here. */
+ rval = ccs_write(sensor, REQUESTED_LINK_RATE,
+ DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz,
+ 1000000 / 256 / 256) *
+ (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ sensor->pll.csi2.lanes : 1) <<
+ (pll->flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0));
+ if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
+ return rval;
+
+ rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op_bk.pix_clk_div);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div);
+ if (rval < 0)
+ return rval;
+
+ if (!(pll->flags & CCS_PLL_FLAG_DUAL_PLL))
+ return 0;
+
+ rval = ccs_write(sensor, PLL_MODE, CCS_PLL_MODE_DUAL);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, OP_PRE_PLL_CLK_DIV,
+ pll->op_fr.pre_pll_clk_div);
+ if (rval < 0)
+ return rval;
+
+ return ccs_write(sensor, OP_PLL_MULTIPLIER, pll->op_fr.pll_multiplier);
+}
+
+static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct ccs_pll_limits lim = {
+ .vt_fr = {
+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
+ .min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
+ .max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ),
+ .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER),
+ .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER),
+ .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
+ .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
+ },
+ .op_fr = {
+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_OP_PRE_PLL_CLK_DIV),
+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_OP_PRE_PLL_CLK_DIV),
+ .min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_IP_CLK_FREQ_MHZ),
+ .max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_IP_CLK_FREQ_MHZ),
+ .min_pll_multiplier = CCS_LIM(sensor, MIN_OP_PLL_MULTIPLIER),
+ .max_pll_multiplier = CCS_LIM(sensor, MAX_OP_PLL_MULTIPLIER),
+ .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_OP_CLK_FREQ_MHZ),
+ .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_OP_CLK_FREQ_MHZ),
+ },
+ .op_bk = {
+ .min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
+ .max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
+ .min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV),
+ .max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV),
+ .min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ),
+ .max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ),
+ .min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ),
+ .max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ),
+ },
+ .vt_bk = {
+ .min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV),
+ .max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV),
+ .min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV),
+ .max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV),
+ .min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ),
+ .max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ),
+ .min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ),
+ .max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ),
+ },
+ .min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
+ .min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
+ };
+
+ return ccs_pll_calculate(&client->dev, &lim, pll);
+}
+
+static int ccs_pll_update(struct ccs_sensor *sensor)
+{
+ struct ccs_pll *pll = &sensor->pll;
+ int rval;
+
+ pll->binning_horizontal = sensor->binning_horizontal;
+ pll->binning_vertical = sensor->binning_vertical;
+ pll->link_freq =
+ sensor->link_freq->qmenu_int[sensor->link_freq->val];
+ pll->scale_m = sensor->scale_m;
+ pll->bits_per_pixel = sensor->csi_format->compressed;
+
+ rval = ccs_pll_try(sensor, pll);
+ if (rval < 0)
+ return rval;
+
+ __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_parray,
+ pll->pixel_rate_pixel_array);
+ __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_csi, pll->pixel_rate_csi);
+
+ return 0;
+}
+
+
+/*
+ *
+ * V4L2 Controls handling
+ *
+ */
+
+static void __ccs_update_exposure_limits(struct ccs_sensor *sensor)
+{
+ struct v4l2_ctrl *ctrl = sensor->exposure;
+ int max;
+
+ max = sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
+ + sensor->vblank->val
+ - CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
+
+ __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, ctrl->step, max);
+}
+
+/*
+ * Order matters.
+ *
+ * 1. Bits-per-pixel, descending.
+ * 2. Bits-per-pixel compressed, descending.
+ * 3. Pixel order, same as in pixel_order_str. Formats for all four pixel
+ * orders must be defined.
+ */
+static const struct ccs_csi_data_format ccs_csi_data_formats[] = {
+ { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, CCS_PIXEL_ORDER_GBRG, },
+};
+
+static const char *pixel_order_str[] = { "GRBG", "RGGB", "BGGR", "GBRG" };
+
+#define to_csi_format_idx(fmt) (((unsigned long)(fmt) \
+ - (unsigned long)ccs_csi_data_formats) \
+ / sizeof(*ccs_csi_data_formats))
+
+static u32 ccs_pixel_order(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int flip = 0;
+
+ if (sensor->hflip) {
+ if (sensor->hflip->val)
+ flip |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
+
+ if (sensor->vflip->val)
+ flip |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
+ }
+
+ flip ^= sensor->hvflip_inv_mask;
+
+ dev_dbg(&client->dev, "flip %d\n", flip);
+ return sensor->default_pixel_order ^ flip;
+}
+
+static void ccs_update_mbus_formats(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ unsigned int csi_format_idx =
+ to_csi_format_idx(sensor->csi_format) & ~3;
+ unsigned int internal_csi_format_idx =
+ to_csi_format_idx(sensor->internal_csi_format) & ~3;
+ unsigned int pixel_order = ccs_pixel_order(sensor);
+
+ if (WARN_ON_ONCE(max(internal_csi_format_idx, csi_format_idx) +
+ pixel_order >= ARRAY_SIZE(ccs_csi_data_formats)))
+ return;
+
+ sensor->mbus_frame_fmts =
+ sensor->default_mbus_frame_fmts << pixel_order;
+ sensor->csi_format =
+ &ccs_csi_data_formats[csi_format_idx + pixel_order];
+ sensor->internal_csi_format =
+ &ccs_csi_data_formats[internal_csi_format_idx
+ + pixel_order];
+
+ dev_dbg(&client->dev, "new pixel order %s\n",
+ pixel_order_str[pixel_order]);
+}
+
+static const char * const ccs_test_patterns[] = {
+ "Disabled",
+ "Solid Colour",
+ "Eight Vertical Colour Bars",
+ "Colour Bars With Fade to Grey",
+ "Pseudorandom Sequence (PN9)",
+};
+
+static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ccs_sensor *sensor =
+ container_of(ctrl->handler, struct ccs_subdev, ctrl_handler)
+ ->sensor;
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int pm_status;
+ u32 orient = 0;
+ unsigned int i;
+ int exposure;
+ int rval;
+
+ switch (ctrl->id) {
+ case V4L2_CID_HFLIP:
+ case V4L2_CID_VFLIP:
+ if (sensor->streaming)
+ return -EBUSY;
+
+ if (sensor->hflip->val)
+ orient |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
+
+ if (sensor->vflip->val)
+ orient |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
+
+ orient ^= sensor->hvflip_inv_mask;
+
+ ccs_update_mbus_formats(sensor);
+
+ break;
+ case V4L2_CID_VBLANK:
+ exposure = sensor->exposure->val;
+
+ __ccs_update_exposure_limits(sensor);
+
+ if (exposure > sensor->exposure->maximum) {
+ sensor->exposure->val = sensor->exposure->maximum;
+ rval = ccs_set_ctrl(sensor->exposure);
+ if (rval < 0)
+ return rval;
+ }
+
+ break;
+ case V4L2_CID_LINK_FREQ:
+ if (sensor->streaming)
+ return -EBUSY;
+
+ rval = ccs_pll_update(sensor);
+ if (rval)
+ return rval;
+
+ return 0;
+ case V4L2_CID_TEST_PATTERN:
+ for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++)
+ v4l2_ctrl_activate(
+ sensor->test_data[i],
+ ctrl->val ==
+ V4L2_SMIAPP_TEST_PATTERN_MODE_SOLID_COLOUR);
+
+ break;
+ }
+
+ pm_status = pm_runtime_get_if_active(&client->dev, true);
+ if (!pm_status)
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_ANALOGUE_GAIN:
+ rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val);
+
+ break;
+ case V4L2_CID_EXPOSURE:
+ rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val);
+
+ break;
+ case V4L2_CID_HFLIP:
+ case V4L2_CID_VFLIP:
+ rval = ccs_write(sensor, IMAGE_ORIENTATION, orient);
+
+ break;
+ case V4L2_CID_VBLANK:
+ rval = ccs_write(sensor, FRAME_LENGTH_LINES,
+ sensor->pixel_array->crop[
+ CCS_PA_PAD_SRC].height
+ + ctrl->val);
+
+ break;
+ case V4L2_CID_HBLANK:
+ rval = ccs_write(sensor, LINE_LENGTH_PCK,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
+ + ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN:
+ rval = ccs_write(sensor, TEST_PATTERN_MODE, ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN_RED:
+ rval = ccs_write(sensor, TEST_DATA_RED, ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN_GREENR:
+ rval = ccs_write(sensor, TEST_DATA_GREENR, ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN_BLUE:
+ rval = ccs_write(sensor, TEST_DATA_BLUE, ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN_GREENB:
+ rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
+
+ break;
+ case V4L2_CID_PIXEL_RATE:
+ /* For v4l2_ctrl_s_ctrl_int64() used internally. */
+ rval = 0;
+
+ break;
+ default:
+ rval = -EINVAL;
+ }
+
+ if (pm_status > 0) {
+ pm_runtime_mark_last_busy(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+ }
+
+ return rval;
+}
+
+static const struct v4l2_ctrl_ops ccs_ctrl_ops = {
+ .s_ctrl = ccs_set_ctrl,
+};
+
+static int ccs_init_controls(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 12);
+ if (rval)
+ return rval;
+
+ sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
+
+ sensor->analog_gain = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_ANALOGUE_GAIN,
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
+ max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
+
+ /* Exposure limits will be updated soon, use just something here. */
+ sensor->exposure = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_EXPOSURE, 0, 0, 1, 0);
+
+ sensor->hflip = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_HFLIP, 0, 1, 1, 0);
+ sensor->vflip = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_VFLIP, 0, 1, 1, 0);
+
+ sensor->vblank = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_VBLANK, 0, 1, 1, 0);
+
+ if (sensor->vblank)
+ sensor->vblank->flags |= V4L2_CTRL_FLAG_UPDATE;
+
+ sensor->hblank = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_HBLANK, 0, 1, 1, 0);
+
+ if (sensor->hblank)
+ sensor->hblank->flags |= V4L2_CTRL_FLAG_UPDATE;
+
+ sensor->pixel_rate_parray = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
+
+ v4l2_ctrl_new_std_menu_items(&sensor->pixel_array->ctrl_handler,
+ &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ccs_test_patterns) - 1,
+ 0, 0, ccs_test_patterns);
+
+ if (sensor->pixel_array->ctrl_handler.error) {
+ dev_err(&client->dev,
+ "pixel array controls initialization failed (%d)\n",
+ sensor->pixel_array->ctrl_handler.error);
+ return sensor->pixel_array->ctrl_handler.error;
+ }
+
+ sensor->pixel_array->sd.ctrl_handler =
+ &sensor->pixel_array->ctrl_handler;
+
+ v4l2_ctrl_cluster(2, &sensor->hflip);
+
+ rval = v4l2_ctrl_handler_init(&sensor->src->ctrl_handler, 0);
+ if (rval)
+ return rval;
+
+ sensor->src->ctrl_handler.lock = &sensor->mutex;
+
+ sensor->pixel_rate_csi = v4l2_ctrl_new_std(
+ &sensor->src->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
+
+ if (sensor->src->ctrl_handler.error) {
+ dev_err(&client->dev,
+ "src controls initialization failed (%d)\n",
+ sensor->src->ctrl_handler.error);
+ return sensor->src->ctrl_handler.error;
+ }
+
+ sensor->src->sd.ctrl_handler = &sensor->src->ctrl_handler;
+
+ return 0;
+}
+
+/*
+ * For controls that require information on available media bus codes
+ * and linke frequencies.
+ */
+static int ccs_init_late_controls(struct ccs_sensor *sensor)
+{
+ unsigned long *valid_link_freqs = &sensor->valid_link_freqs[
+ sensor->csi_format->compressed - sensor->compressed_min_bpp];
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++) {
+ int max_value = (1 << sensor->csi_format->width) - 1;
+
+ sensor->test_data[i] = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler,
+ &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i,
+ 0, max_value, 1, max_value);
+ }
+
+ sensor->link_freq = v4l2_ctrl_new_int_menu(
+ &sensor->src->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs),
+ __ffs(*valid_link_freqs), sensor->hwcfg.op_sys_clock);
+
+ return sensor->src->ctrl_handler.error;
+}
+
+static void ccs_free_controls(struct ccs_sensor *sensor)
+{
+ unsigned int i;
+
+ for (i = 0; i < sensor->ssds_used; i++)
+ v4l2_ctrl_handler_free(&sensor->ssds[i].ctrl_handler);
+}
+
+static int ccs_get_mbus_formats(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct ccs_pll *pll = &sensor->pll;
+ u8 compressed_max_bpp = 0;
+ unsigned int type, n;
+ unsigned int i, pixel_order;
+ int rval;
+
+ type = CCS_LIM(sensor, DATA_FORMAT_MODEL_TYPE);
+
+ dev_dbg(&client->dev, "data_format_model_type %d\n", type);
+
+ rval = ccs_read(sensor, PIXEL_ORDER, &pixel_order);
+ if (rval)
+ return rval;
+
+ if (pixel_order >= ARRAY_SIZE(pixel_order_str)) {
+ dev_dbg(&client->dev, "bad pixel order %d\n", pixel_order);
+ return -EINVAL;
+ }
+
+ dev_dbg(&client->dev, "pixel order %d (%s)\n", pixel_order,
+ pixel_order_str[pixel_order]);
+
+ switch (type) {
+ case CCS_DATA_FORMAT_MODEL_TYPE_NORMAL:
+ n = SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N;
+ break;
+ case CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED:
+ n = CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N + 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ sensor->default_pixel_order = pixel_order;
+ sensor->mbus_frame_fmts = 0;
+
+ for (i = 0; i < n; i++) {
+ unsigned int fmt, j;
+
+ fmt = CCS_LIM_AT(sensor, DATA_FORMAT_DESCRIPTOR, i);
+
+ dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n",
+ i, fmt >> 8, (u8)fmt);
+
+ for (j = 0; j < ARRAY_SIZE(ccs_csi_data_formats); j++) {
+ const struct ccs_csi_data_format *f =
+ &ccs_csi_data_formats[j];
+
+ if (f->pixel_order != CCS_PIXEL_ORDER_GRBG)
+ continue;
+
+ if (f->width != fmt >>
+ CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT ||
+ f->compressed !=
+ (fmt & CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK))
+ continue;
+
+ dev_dbg(&client->dev, "jolly good! %d\n", j);
+
+ sensor->default_mbus_frame_fmts |= 1 << j;
+ }
+ }
+
+ /* Figure out which BPP values can be used with which formats. */
+ pll->binning_horizontal = 1;
+ pll->binning_vertical = 1;
+ pll->scale_m = sensor->scale_m;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ sensor->compressed_min_bpp =
+ min(ccs_csi_data_formats[i].compressed,
+ sensor->compressed_min_bpp);
+ compressed_max_bpp =
+ max(ccs_csi_data_formats[i].compressed,
+ compressed_max_bpp);
+ }
+
+ sensor->valid_link_freqs = devm_kcalloc(
+ &client->dev,
+ compressed_max_bpp - sensor->compressed_min_bpp + 1,
+ sizeof(*sensor->valid_link_freqs), GFP_KERNEL);
+ if (!sensor->valid_link_freqs)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ const struct ccs_csi_data_format *f =
+ &ccs_csi_data_formats[i];
+ unsigned long *valid_link_freqs =
+ &sensor->valid_link_freqs[
+ f->compressed - sensor->compressed_min_bpp];
+ unsigned int j;
+
+ if (!(sensor->default_mbus_frame_fmts & 1 << i))
+ continue;
+
+ pll->bits_per_pixel = f->compressed;
+
+ for (j = 0; sensor->hwcfg.op_sys_clock[j]; j++) {
+ pll->link_freq = sensor->hwcfg.op_sys_clock[j];
+
+ rval = ccs_pll_try(sensor, pll);
+ dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n",
+ pll->link_freq, pll->bits_per_pixel,
+ rval ? "not ok" : "ok");
+ if (rval)
+ continue;
+
+ set_bit(j, valid_link_freqs);
+ }
+
+ if (!*valid_link_freqs) {
+ dev_info(&client->dev,
+ "no valid link frequencies for %u bpp\n",
+ f->compressed);
+ sensor->default_mbus_frame_fmts &= ~BIT(i);
+ continue;
+ }
+
+ if (!sensor->csi_format
+ || f->width > sensor->csi_format->width
+ || (f->width == sensor->csi_format->width
+ && f->compressed > sensor->csi_format->compressed)) {
+ sensor->csi_format = f;
+ sensor->internal_csi_format = f;
+ }
+ }
+
+ if (!sensor->csi_format) {
+ dev_err(&client->dev, "no supported mbus code found\n");
+ return -EINVAL;
+ }
+
+ ccs_update_mbus_formats(sensor);
+
+ return 0;
+}
+
+static void ccs_update_blanking(struct ccs_sensor *sensor)
+{
+ struct v4l2_ctrl *vblank = sensor->vblank;
+ struct v4l2_ctrl *hblank = sensor->hblank;
+ uint16_t min_fll, max_fll, min_llp, max_llp, min_lbp;
+ int min, max;
+
+ if (sensor->binning_vertical > 1 || sensor->binning_horizontal > 1) {
+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
+ } else {
+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES);
+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES);
+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK);
+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK);
+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK);
+ }
+
+ min = max_t(int,
+ CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
+ min_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height);
+ max = max_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height;
+
+ __v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min);
+
+ min = max_t(int,
+ min_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width,
+ min_lbp);
+ max = max_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width;
+
+ __v4l2_ctrl_modify_range(hblank, min, max, hblank->step, min);
+
+ __ccs_update_exposure_limits(sensor);
+}
+
+static int ccs_pll_blanking_update(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ rval = ccs_pll_update(sensor);
+ if (rval < 0)
+ return rval;
+
+ /* Output from pixel array, including blanking */
+ ccs_update_blanking(sensor);
+
+ dev_dbg(&client->dev, "vblank\t\t%d\n", sensor->vblank->val);
+ dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val);
+
+ dev_dbg(&client->dev, "real timeperframe\t100/%d\n",
+ sensor->pll.pixel_rate_pixel_array /
+ ((sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
+ + sensor->hblank->val) *
+ (sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
+ + sensor->vblank->val) / 100));
+
+ return 0;
+}
+
+/*
+ *
+ * SMIA++ NVM handling
+ *
+ */
+
+static int ccs_read_nvm_page(struct ccs_sensor *sensor, u32 p, u8 *nvm,
+ u8 *status)
+{
+ unsigned int i;
+ int rval;
+ u32 s;
+
+ *status = 0;
+
+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_PAGE_SELECT, p);
+ if (rval)
+ return rval;
+
+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL,
+ CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE);
+ if (rval)
+ return rval;
+
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
+ if (rval)
+ return rval;
+
+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE) {
+ *status = s;
+ return -ENODATA;
+ }
+
+ if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
+ CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
+ for (i = 1000; i > 0; i--) {
+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY)
+ break;
+
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
+ if (rval)
+ return rval;
+ }
+
+ if (!i)
+ return -ETIMEDOUT;
+ }
+
+ for (i = 0; i <= CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P; i++) {
+ u32 v;
+
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_DATA(i), &v);
+ if (rval)
+ return rval;
+
+ *nvm++ = v;
+ }
+
+ return 0;
+}
+
+static int ccs_read_nvm(struct ccs_sensor *sensor, unsigned char *nvm,
+ size_t nvm_size)
+{
+ u8 status = 0;
+ u32 p;
+ int rval = 0, rval2;
+
+ for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1)
+ && !rval; p++) {
+ rval = ccs_read_nvm_page(sensor, p, nvm, &status);
+ nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1;
+ }
+
+ if (rval == -ENODATA &&
+ status & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE)
+ rval = 0;
+
+ rval2 = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL, 0);
+ if (rval < 0)
+ return rval;
+ else
+ return rval2 ?: p * (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1);
+}
+
+/*
+ *
+ * SMIA++ CCI address control
+ *
+ */
+static int ccs_change_cci_addr(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+ u32 val;
+
+ client->addr = sensor->hwcfg.i2c_addr_dfl;
+
+ rval = ccs_write(sensor, CCI_ADDRESS_CTRL,
+ sensor->hwcfg.i2c_addr_alt << 1);
+ if (rval)
+ return rval;
+
+ client->addr = sensor->hwcfg.i2c_addr_alt;
+
+ /* verify addr change went ok */
+ rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val);
+ if (rval)
+ return rval;
+
+ if (val != sensor->hwcfg.i2c_addr_alt << 1)
+ return -ENODEV;
+
+ return 0;
+}
+
+/*
+ *
+ * SMIA++ Mode Control
+ *
+ */
+static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
+{
+ struct ccs_flash_strobe_parms *strobe_setup;
+ unsigned int ext_freq = sensor->hwcfg.ext_clk;
+ u32 tmp;
+ u32 strobe_adjustment;
+ u32 strobe_width_high_rs;
+ int rval;
+
+ strobe_setup = sensor->hwcfg.strobe_setup;
+
+ /*
+ * How to calculate registers related to strobe length. Please
+ * do not change, or if you do at least know what you're
+ * doing. :-)
+ *
+ * Sakari Ailus <sakari.ailus@linux.intel.com> 2010-10-25
+ *
+ * flash_strobe_length [us] / 10^6 = (tFlash_strobe_width_ctrl
+ * / EXTCLK freq [Hz]) * flash_strobe_adjustment
+ *
+ * tFlash_strobe_width_ctrl E N, [1 - 0xffff]
+ * flash_strobe_adjustment E N, [1 - 0xff]
+ *
+ * The formula above is written as below to keep it on one
+ * line:
+ *
+ * l / 10^6 = w / e * a
+ *
+ * Let's mark w * a by x:
+ *
+ * x = w * a
+ *
+ * Thus, we get:
+ *
+ * x = l * e / 10^6
+ *
+ * The strobe width must be at least as long as requested,
+ * thus rounding upwards is needed.
+ *
+ * x = (l * e + 10^6 - 1) / 10^6
+ * -----------------------------
+ *
+ * Maximum possible accuracy is wanted at all times. Thus keep
+ * a as small as possible.
+ *
+ * Calculate a, assuming maximum w, with rounding upwards:
+ *
+ * a = (x + (2^16 - 1) - 1) / (2^16 - 1)
+ * -------------------------------------
+ *
+ * Thus, we also get w, with that a, with rounding upwards:
+ *
+ * w = (x + a - 1) / a
+ * -------------------
+ *
+ * To get limits:
+ *
+ * x E [1, (2^16 - 1) * (2^8 - 1)]
+ *
+ * Substituting maximum x to the original formula (with rounding),
+ * the maximum l is thus
+ *
+ * (2^16 - 1) * (2^8 - 1) * 10^6 = l * e + 10^6 - 1
+ *
+ * l = (10^6 * (2^16 - 1) * (2^8 - 1) - 10^6 + 1) / e
+ * --------------------------------------------------
+ *
+ * flash_strobe_length must be clamped between 1 and
+ * (10^6 * (2^16 - 1) * (2^8 - 1) - 10^6 + 1) / EXTCLK freq.
+ *
+ * Then,
+ *
+ * flash_strobe_adjustment = ((flash_strobe_length *
+ * EXTCLK freq + 10^6 - 1) / 10^6 + (2^16 - 1) - 1) / (2^16 - 1)
+ *
+ * tFlash_strobe_width_ctrl = ((flash_strobe_length *
+ * EXTCLK freq + 10^6 - 1) / 10^6 +
+ * flash_strobe_adjustment - 1) / flash_strobe_adjustment
+ */
+ tmp = div_u64(1000000ULL * ((1 << 16) - 1) * ((1 << 8) - 1) -
+ 1000000 + 1, ext_freq);
+ strobe_setup->strobe_width_high_us =
+ clamp_t(u32, strobe_setup->strobe_width_high_us, 1, tmp);
+
+ tmp = div_u64(((u64)strobe_setup->strobe_width_high_us * (u64)ext_freq +
+ 1000000 - 1), 1000000ULL);
+ strobe_adjustment = (tmp + (1 << 16) - 1 - 1) / ((1 << 16) - 1);
+ strobe_width_high_rs = (tmp + strobe_adjustment - 1) /
+ strobe_adjustment;
+
+ rval = ccs_write(sensor, FLASH_MODE_RS, strobe_setup->mode);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, FLASH_STROBE_ADJUSTMENT, strobe_adjustment);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
+ strobe_width_high_rs);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, TFLASH_STROBE_DELAY_RS_CTRL,
+ strobe_setup->strobe_delay);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, FLASH_STROBE_START_POINT,
+ strobe_setup->stobe_start_point);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger);
+
+out:
+ sensor->hwcfg.strobe_setup->trigger = 0;
+
+ return rval;
+}
+
+/* -----------------------------------------------------------------------------
+ * Power management
+ */
+
+static int ccs_write_msr_regs(struct ccs_sensor *sensor)
+{
+ int rval;
+
+ rval = ccs_write_data_regs(sensor,
+ sensor->sdata.sensor_manufacturer_regs,
+ sensor->sdata.num_sensor_manufacturer_regs);
+ if (rval)
+ return rval;
+
+ return ccs_write_data_regs(sensor,
+ sensor->mdata.module_manufacturer_regs,
+ sensor->mdata.num_module_manufacturer_regs);
+}
+
+static int ccs_power_on(struct device *dev)
+{
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ /*
+ * The sub-device related to the I2C device is always the
+ * source one, i.e. ssds[0].
+ */
+ struct ccs_sensor *sensor =
+ container_of(ssd, struct ccs_sensor, ssds[0]);
+ const struct ccs_device *ccsdev = device_get_match_data(dev);
+ unsigned int sleep;
+ int rval;
+
+ rval = regulator_bulk_enable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+ if (rval) {
+ dev_err(dev, "failed to enable vana regulator\n");
+ return rval;
+ }
+
+ rval = clk_prepare_enable(sensor->ext_clk);
+ if (rval < 0) {
+ dev_dbg(dev, "failed to enable xclk\n");
+ goto out_xclk_fail;
+ }
+
+ gpiod_set_value(sensor->reset, 0);
+ gpiod_set_value(sensor->xshutdown, 1);
+
+ if (ccsdev->flags & CCS_DEVICE_FLAG_IS_SMIA)
+ sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk);
+ else
+ sleep = 5000;
+
+ usleep_range(sleep, sleep);
+
+ /*
+ * Failures to respond to the address change command have been noticed.
+ * Those failures seem to be caused by the sensor requiring a longer
+ * boot time than advertised. An additional 10ms delay seems to work
+ * around the issue, but the SMIA++ I2C write retry hack makes the delay
+ * unnecessary. The failures need to be investigated to find a proper
+ * fix, and a delay will likely need to be added here if the I2C write
+ * retry hack is reverted before the root cause of the boot time issue
+ * is found.
+ */
+
+ if (sensor->hwcfg.i2c_addr_alt) {
+ rval = ccs_change_cci_addr(sensor);
+ if (rval) {
+ dev_err(dev, "cci address change error\n");
+ goto out_cci_addr_fail;
+ }
+ }
+
+ rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
+ if (rval < 0) {
+ dev_err(dev, "software reset failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ if (sensor->hwcfg.i2c_addr_alt) {
+ rval = ccs_change_cci_addr(sensor);
+ if (rval) {
+ dev_err(dev, "cci address change error\n");
+ goto out_cci_addr_fail;
+ }
+ }
+
+ rval = ccs_write(sensor, COMPRESSION_MODE,
+ CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE);
+ if (rval) {
+ dev_err(dev, "compression mode set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ,
+ sensor->hwcfg.ext_clk / (1000000 / (1 << 8)));
+ if (rval) {
+ dev_err(dev, "extclk frequency set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg.lanes - 1);
+ if (rval) {
+ dev_err(dev, "csi lane mode set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_write(sensor, FAST_STANDBY_CTRL,
+ CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION);
+ if (rval) {
+ dev_err(dev, "fast standby set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_write(sensor, CSI_SIGNALING_MODE,
+ sensor->hwcfg.csi_signalling_mode);
+ if (rval) {
+ dev_err(dev, "csi signalling mode set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ /* DPHY control done by sensor based on requested link rate */
+ rval = ccs_write(sensor, PHY_CTRL, CCS_PHY_CTRL_UI);
+ if (rval < 0)
+ goto out_cci_addr_fail;
+
+ rval = ccs_write_msr_regs(sensor);
+ if (rval)
+ goto out_cci_addr_fail;
+
+ rval = ccs_call_quirk(sensor, post_poweron);
+ if (rval) {
+ dev_err(dev, "post_poweron quirks failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ return 0;
+
+out_cci_addr_fail:
+ gpiod_set_value(sensor->reset, 1);
+ gpiod_set_value(sensor->xshutdown, 0);
+ clk_disable_unprepare(sensor->ext_clk);
+
+out_xclk_fail:
+ regulator_bulk_disable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+
+ return rval;
+}
+
+static int ccs_power_off(struct device *dev)
+{
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct ccs_sensor *sensor =
+ container_of(ssd, struct ccs_sensor, ssds[0]);
+
+ /*
+ * Currently power/clock to lens are enable/disabled separately
+ * but they are essentially the same signals. So if the sensor is
+ * powered off while the lens is powered on the sensor does not
+ * really see a power off and next time the cci address change
+ * will fail. So do a soft reset explicitly here.
+ */
+ if (sensor->hwcfg.i2c_addr_alt)
+ ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
+
+ gpiod_set_value(sensor->reset, 1);
+ gpiod_set_value(sensor->xshutdown, 0);
+ clk_disable_unprepare(sensor->ext_clk);
+ usleep_range(5000, 5000);
+ regulator_bulk_disable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+ sensor->streaming = false;
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Video stream management
+ */
+
+static int ccs_start_streaming(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ unsigned int binning_mode;
+ int rval;
+
+ mutex_lock(&sensor->mutex);
+
+ rval = ccs_write(sensor, CSI_DATA_FORMAT,
+ (sensor->csi_format->width << 8) |
+ sensor->csi_format->compressed);
+ if (rval)
+ goto out;
+
+ /* Binning configuration */
+ if (sensor->binning_horizontal == 1 &&
+ sensor->binning_vertical == 1) {
+ binning_mode = 0;
+ } else {
+ u8 binning_type =
+ (sensor->binning_horizontal << 4)
+ | sensor->binning_vertical;
+
+ rval = ccs_write(sensor, BINNING_TYPE, binning_type);
+ if (rval < 0)
+ goto out;
+
+ binning_mode = 1;
+ }
+ rval = ccs_write(sensor, BINNING_MODE, binning_mode);
+ if (rval < 0)
+ goto out;
+
+ /* Set up PLL */
+ rval = ccs_pll_configure(sensor);
+ if (rval)
+ goto out;
+
+ /* Analog crop start coordinates */
+ rval = ccs_write(sensor, X_ADDR_START,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].left);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, Y_ADDR_START,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].top);
+ if (rval < 0)
+ goto out;
+
+ /* Analog crop end coordinates */
+ rval = ccs_write(
+ sensor, X_ADDR_END,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].left
+ + sensor->pixel_array->crop[CCS_PA_PAD_SRC].width - 1);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(
+ sensor, Y_ADDR_END,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].top
+ + sensor->pixel_array->crop[CCS_PA_PAD_SRC].height - 1);
+ if (rval < 0)
+ goto out;
+
+ /*
+ * Output from pixel array, including blanking, is set using
+ * controls below. No need to set here.
+ */
+
+ /* Digital crop */
+ if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_X_OFFSET,
+ sensor->scaler->crop[CCS_PAD_SINK].left);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_Y_OFFSET,
+ sensor->scaler->crop[CCS_PAD_SINK].top);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_IMAGE_WIDTH,
+ sensor->scaler->crop[CCS_PAD_SINK].width);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_IMAGE_HEIGHT,
+ sensor->scaler->crop[CCS_PAD_SINK].height);
+ if (rval < 0)
+ goto out;
+ }
+
+ /* Scaling */
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE) {
+ rval = ccs_write(sensor, SCALING_MODE, sensor->scaling_mode);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, SCALE_M, sensor->scale_m);
+ if (rval < 0)
+ goto out;
+ }
+
+ /* Output size from sensor */
+ rval = ccs_write(sensor, X_OUTPUT_SIZE,
+ sensor->src->crop[CCS_PAD_SRC].width);
+ if (rval < 0)
+ goto out;
+ rval = ccs_write(sensor, Y_OUTPUT_SIZE,
+ sensor->src->crop[CCS_PAD_SRC].height);
+ if (rval < 0)
+ goto out;
+
+ if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) &
+ (CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
+ SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
+ sensor->hwcfg.strobe_setup != NULL &&
+ sensor->hwcfg.strobe_setup->trigger != 0) {
+ rval = ccs_setup_flash_strobe(sensor);
+ if (rval)
+ goto out;
+ }
+
+ rval = ccs_call_quirk(sensor, pre_streamon);
+ if (rval) {
+ dev_err(&client->dev, "pre_streamon quirks failed\n");
+ goto out;
+ }
+
+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_STREAMING);
+
+out:
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+}
+
+static int ccs_stop_streaming(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ mutex_lock(&sensor->mutex);
+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_SOFTWARE_STANDBY);
+ if (rval)
+ goto out;
+
+ rval = ccs_call_quirk(sensor, post_streamoff);
+ if (rval)
+ dev_err(&client->dev, "post_streamoff quirks failed\n");
+
+out:
+ mutex_unlock(&sensor->mutex);
+ return rval;
+}
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev video operations
+ */
+
+static int ccs_pm_get_init(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ rval = pm_runtime_get_sync(&client->dev);
+ if (rval < 0) {
+ pm_runtime_put_noidle(&client->dev);
+
+ return rval;
+ } else if (!rval) {
+ rval = v4l2_ctrl_handler_setup(&sensor->pixel_array->
+ ctrl_handler);
+ if (rval)
+ return rval;
+
+ return v4l2_ctrl_handler_setup(&sensor->src->ctrl_handler);
+ }
+
+ return 0;
+}
+
+static int ccs_set_stream(struct v4l2_subdev *subdev, int enable)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ if (sensor->streaming == enable)
+ return 0;
+
+ if (!enable) {
+ ccs_stop_streaming(sensor);
+ sensor->streaming = false;
+ pm_runtime_mark_last_busy(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+
+ return 0;
+ }
+
+ rval = ccs_pm_get_init(sensor);
+ if (rval)
+ return rval;
+
+ sensor->streaming = true;
+
+ rval = ccs_start_streaming(sensor);
+ if (rval < 0) {
+ sensor->streaming = false;
+ pm_runtime_mark_last_busy(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+ }
+
+ return rval;
+}
+
+static int ccs_enum_mbus_code(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ unsigned int i;
+ int idx = -1;
+ int rval = -EINVAL;
+
+ mutex_lock(&sensor->mutex);
+
+ dev_err(&client->dev, "subdev %s, pad %d, index %d\n",
+ subdev->name, code->pad, code->index);
+
+ if (subdev != &sensor->src->sd || code->pad != CCS_PAD_SRC) {
+ if (code->index)
+ goto out;
+
+ code->code = sensor->internal_csi_format->code;
+ rval = 0;
+ goto out;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ if (sensor->mbus_frame_fmts & (1 << i))
+ idx++;
+
+ if (idx == code->index) {
+ code->code = ccs_csi_data_formats[i].code;
+ dev_err(&client->dev, "found index %d, i %d, code %x\n",
+ code->index, i, code->code);
+ rval = 0;
+ break;
+ }
+ }
+
+out:
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+}
+
+static u32 __ccs_get_mbus_code(struct v4l2_subdev *subdev, unsigned int pad)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+
+ if (subdev == &sensor->src->sd && pad == CCS_PAD_SRC)
+ return sensor->csi_format->code;
+ else
+ return sensor->internal_csi_format->code;
+}
+
+static int __ccs_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+ fmt->format = *v4l2_subdev_get_try_format(subdev, cfg,
+ fmt->pad);
+ } else {
+ struct v4l2_rect *r;
+
+ if (fmt->pad == ssd->source_pad)
+ r = &ssd->crop[ssd->source_pad];
+ else
+ r = &ssd->sink_fmt;
+
+ fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
+ fmt->format.width = r->width;
+ fmt->format.height = r->height;
+ fmt->format.field = V4L2_FIELD_NONE;
+ }
+
+ return 0;
+}
+
+static int ccs_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval;
+
+ mutex_lock(&sensor->mutex);
+ rval = __ccs_get_format(subdev, cfg, fmt);
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+}
+
+static void ccs_get_crop_compose(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_rect **crops,
+ struct v4l2_rect **comps, int which)
+{
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ unsigned int i;
+
+ if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ if (crops)
+ for (i = 0; i < subdev->entity.num_pads; i++)
+ crops[i] = &ssd->crop[i];
+ if (comps)
+ *comps = &ssd->compose;
+ } else {
+ if (crops) {
+ for (i = 0; i < subdev->entity.num_pads; i++)
+ crops[i] = v4l2_subdev_get_try_crop(subdev,
+ cfg, i);
+ }
+ if (comps)
+ *comps = v4l2_subdev_get_try_compose(subdev, cfg,
+ CCS_PAD_SINK);
+ }
+}
+
+/* Changes require propagation only on sink pad. */
+static void ccs_propagate(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg, int which,
+ int target)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
+
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, which);
+
+ switch (target) {
+ case V4L2_SEL_TGT_CROP:
+ comp->width = crops[CCS_PAD_SINK]->width;
+ comp->height = crops[CCS_PAD_SINK]->height;
+ if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ if (ssd == sensor->scaler) {
+ sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
+ sensor->scaling_mode =
+ CCS_SCALING_MODE_NO_SCALING;
+ } else if (ssd == sensor->binner) {
+ sensor->binning_horizontal = 1;
+ sensor->binning_vertical = 1;
+ }
+ }
+ fallthrough;
+ case V4L2_SEL_TGT_COMPOSE:
+ *crops[CCS_PAD_SRC] = *comp;
+ break;
+ default:
+ WARN_ON_ONCE(1);
+ }
+}
+
+static const struct ccs_csi_data_format
+*ccs_validate_csi_data_format(struct ccs_sensor *sensor, u32 code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ if (sensor->mbus_frame_fmts & (1 << i) &&
+ ccs_csi_data_formats[i].code == code)
+ return &ccs_csi_data_formats[i];
+ }
+
+ return sensor->csi_format;
+}
+
+static int ccs_set_format_source(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ const struct ccs_csi_data_format *csi_format,
+ *old_csi_format = sensor->csi_format;
+ unsigned long *valid_link_freqs;
+ u32 code = fmt->format.code;
+ unsigned int i;
+ int rval;
+
+ rval = __ccs_get_format(subdev, cfg, fmt);
+ if (rval)
+ return rval;
+
+ /*
+ * Media bus code is changeable on src subdev's source pad. On
+ * other source pads we just get format here.
+ */
+ if (subdev != &sensor->src->sd)
+ return 0;
+
+ csi_format = ccs_validate_csi_data_format(sensor, code);
+
+ fmt->format.code = csi_format->code;
+
+ if (fmt->which != V4L2_SUBDEV_FORMAT_ACTIVE)
+ return 0;
+
+ sensor->csi_format = csi_format;
+
+ if (csi_format->width != old_csi_format->width)
+ for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++)
+ __v4l2_ctrl_modify_range(
+ sensor->test_data[i], 0,
+ (1 << csi_format->width) - 1, 1, 0);
+
+ if (csi_format->compressed == old_csi_format->compressed)
+ return 0;
+
+ valid_link_freqs =
+ &sensor->valid_link_freqs[sensor->csi_format->compressed
+ - sensor->compressed_min_bpp];
+
+ __v4l2_ctrl_modify_range(
+ sensor->link_freq, 0,
+ __fls(*valid_link_freqs), ~*valid_link_freqs,
+ __ffs(*valid_link_freqs));
+
+ return ccs_pll_update(sensor);
+}
+
+static int ccs_set_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *crops[CCS_PADS];
+
+ mutex_lock(&sensor->mutex);
+
+ if (fmt->pad == ssd->source_pad) {
+ int rval;
+
+ rval = ccs_set_format_source(subdev, cfg, fmt);
+
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+ }
+
+ /* Sink pad. Width and height are changeable here. */
+ fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
+ fmt->format.width &= ~1;
+ fmt->format.height &= ~1;
+ fmt->format.field = V4L2_FIELD_NONE;
+
+ fmt->format.width =
+ clamp(fmt->format.width,
+ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ CCS_LIM(sensor, MAX_X_OUTPUT_SIZE));
+ fmt->format.height =
+ clamp(fmt->format.height,
+ CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE));
+
+ ccs_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
+
+ crops[ssd->sink_pad]->left = 0;
+ crops[ssd->sink_pad]->top = 0;
+ crops[ssd->sink_pad]->width = fmt->format.width;
+ crops[ssd->sink_pad]->height = fmt->format.height;
+ if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ ssd->sink_fmt = *crops[ssd->sink_pad];
+ ccs_propagate(subdev, cfg, fmt->which, V4L2_SEL_TGT_CROP);
+
+ mutex_unlock(&sensor->mutex);
+
+ return 0;
+}
+
+/*
+ * Calculate goodness of scaled image size compared to expected image
+ * size and flags provided.
+ */
+#define SCALING_GOODNESS 100000
+#define SCALING_GOODNESS_EXTREME 100000000
+static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
+ int h, int ask_h, u32 flags)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ int val = 0;
+
+ w &= ~1;
+ ask_w &= ~1;
+ h &= ~1;
+ ask_h &= ~1;
+
+ if (flags & V4L2_SEL_FLAG_GE) {
+ if (w < ask_w)
+ val -= SCALING_GOODNESS;
+ if (h < ask_h)
+ val -= SCALING_GOODNESS;
+ }
+
+ if (flags & V4L2_SEL_FLAG_LE) {
+ if (w > ask_w)
+ val -= SCALING_GOODNESS;
+ if (h > ask_h)
+ val -= SCALING_GOODNESS;
+ }
+
+ val -= abs(w - ask_w);
+ val -= abs(h - ask_h);
+
+ if (w < CCS_LIM(sensor, MIN_X_OUTPUT_SIZE))
+ val -= SCALING_GOODNESS_EXTREME;
+
+ dev_dbg(&client->dev, "w %d ask_w %d h %d ask_h %d goodness %d\n",
+ w, ask_w, h, ask_h, val);
+
+ return val;
+}
+
+static void ccs_set_compose_binner(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel,
+ struct v4l2_rect **crops,
+ struct v4l2_rect *comp)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ unsigned int i;
+ unsigned int binh = 1, binv = 1;
+ int best = scaling_goodness(
+ subdev,
+ crops[CCS_PAD_SINK]->width, sel->r.width,
+ crops[CCS_PAD_SINK]->height, sel->r.height, sel->flags);
+
+ for (i = 0; i < sensor->nbinning_subtypes; i++) {
+ int this = scaling_goodness(
+ subdev,
+ crops[CCS_PAD_SINK]->width
+ / sensor->binning_subtypes[i].horizontal,
+ sel->r.width,
+ crops[CCS_PAD_SINK]->height
+ / sensor->binning_subtypes[i].vertical,
+ sel->r.height, sel->flags);
+
+ if (this > best) {
+ binh = sensor->binning_subtypes[i].horizontal;
+ binv = sensor->binning_subtypes[i].vertical;
+ best = this;
+ }
+ }
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ sensor->binning_vertical = binv;
+ sensor->binning_horizontal = binh;
+ }
+
+ sel->r.width = (crops[CCS_PAD_SINK]->width / binh) & ~1;
+ sel->r.height = (crops[CCS_PAD_SINK]->height / binv) & ~1;
+}
+
+/*
+ * Calculate best scaling ratio and mode for given output resolution.
+ *
+ * Try all of these: horizontal ratio, vertical ratio and smallest
+ * size possible (horizontally).
+ *
+ * Also try whether horizontal scaler or full scaler gives a better
+ * result.
+ */
+static void ccs_set_compose_scaler(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel,
+ struct v4l2_rect **crops,
+ struct v4l2_rect *comp)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ u32 min, max, a, b, max_m;
+ u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
+ int mode = CCS_SCALING_MODE_HORIZONTAL;
+ u32 try[4];
+ u32 ntry = 0;
+ unsigned int i;
+ int best = INT_MIN;
+
+ sel->r.width = min_t(unsigned int, sel->r.width,
+ crops[CCS_PAD_SINK]->width);
+ sel->r.height = min_t(unsigned int, sel->r.height,
+ crops[CCS_PAD_SINK]->height);
+
+ a = crops[CCS_PAD_SINK]->width
+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width;
+ b = crops[CCS_PAD_SINK]->height
+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height;
+ max_m = crops[CCS_PAD_SINK]->width
+ * CCS_LIM(sensor, SCALER_N_MIN)
+ / CCS_LIM(sensor, MIN_X_OUTPUT_SIZE);
+
+ a = clamp(a, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+ b = clamp(b, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+ max_m = clamp(max_m, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+
+ dev_dbg(&client->dev, "scaling: a %d b %d max_m %d\n", a, b, max_m);
+
+ min = min(max_m, min(a, b));
+ max = min(max_m, max(a, b));
+
+ try[ntry] = min;
+ ntry++;
+ if (min != max) {
+ try[ntry] = max;
+ ntry++;
+ }
+ if (max != max_m) {
+ try[ntry] = min + 1;
+ ntry++;
+ if (min != max) {
+ try[ntry] = max + 1;
+ ntry++;
+ }
+ }
+
+ for (i = 0; i < ntry; i++) {
+ int this = scaling_goodness(
+ subdev,
+ crops[CCS_PAD_SINK]->width
+ / try[i] * CCS_LIM(sensor, SCALER_N_MIN),
+ sel->r.width,
+ crops[CCS_PAD_SINK]->height,
+ sel->r.height,
+ sel->flags);
+
+ dev_dbg(&client->dev, "trying factor %d (%d)\n", try[i], i);
+
+ if (this > best) {
+ scale_m = try[i];
+ mode = CCS_SCALING_MODE_HORIZONTAL;
+ best = this;
+ }
+
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ == CCS_SCALING_CAPABILITY_HORIZONTAL)
+ continue;
+
+ this = scaling_goodness(
+ subdev, crops[CCS_PAD_SINK]->width
+ / try[i]
+ * CCS_LIM(sensor, SCALER_N_MIN),
+ sel->r.width,
+ crops[CCS_PAD_SINK]->height
+ / try[i]
+ * CCS_LIM(sensor, SCALER_N_MIN),
+ sel->r.height,
+ sel->flags);
+
+ if (this > best) {
+ scale_m = try[i];
+ mode = SMIAPP_SCALING_MODE_BOTH;
+ best = this;
+ }
+ }
+
+ sel->r.width =
+ (crops[CCS_PAD_SINK]->width
+ / scale_m
+ * CCS_LIM(sensor, SCALER_N_MIN)) & ~1;
+ if (mode == SMIAPP_SCALING_MODE_BOTH)
+ sel->r.height =
+ (crops[CCS_PAD_SINK]->height
+ / scale_m
+ * CCS_LIM(sensor, SCALER_N_MIN))
+ & ~1;
+ else
+ sel->r.height = crops[CCS_PAD_SINK]->height;
+
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ sensor->scale_m = scale_m;
+ sensor->scaling_mode = mode;
+ }
+}
+/* We're only called on source pads. This function sets scaling. */
+static int ccs_set_compose(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
+
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
+
+ sel->r.top = 0;
+ sel->r.left = 0;
+
+ if (ssd == sensor->binner)
+ ccs_set_compose_binner(subdev, cfg, sel, crops, comp);
+ else
+ ccs_set_compose_scaler(subdev, cfg, sel, crops, comp);
+
+ *comp = sel->r;
+ ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE);
+
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ return ccs_pll_blanking_update(sensor);
+
+ return 0;
+}
+
+static int __ccs_sel_supported(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+
+ /* We only implement crop in three places. */
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
+ return 0;
+ if (ssd == sensor->src && sel->pad == CCS_PAD_SRC)
+ return 0;
+ if (ssd == sensor->scaler && sel->pad == CCS_PAD_SINK &&
+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
+ return 0;
+ return -EINVAL;
+ case V4L2_SEL_TGT_NATIVE_SIZE:
+ if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
+ return 0;
+ return -EINVAL;
+ case V4L2_SEL_TGT_COMPOSE:
+ case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ if (sel->pad == ssd->source_pad)
+ return -EINVAL;
+ if (ssd == sensor->binner)
+ return 0;
+ if (ssd == sensor->scaler && CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE)
+ return 0;
+ fallthrough;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ccs_set_crop(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *src_size, *crops[CCS_PADS];
+ struct v4l2_rect _r;
+
+ ccs_get_crop_compose(subdev, cfg, crops, NULL, sel->which);
+
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ if (sel->pad == ssd->sink_pad)
+ src_size = &ssd->sink_fmt;
+ else
+ src_size = &ssd->compose;
+ } else {
+ if (sel->pad == ssd->sink_pad) {
+ _r.left = 0;
+ _r.top = 0;
+ _r.width = v4l2_subdev_get_try_format(subdev, cfg,
+ sel->pad)
+ ->width;
+ _r.height = v4l2_subdev_get_try_format(subdev, cfg,
+ sel->pad)
+ ->height;
+ src_size = &_r;
+ } else {
+ src_size = v4l2_subdev_get_try_compose(
+ subdev, cfg, ssd->sink_pad);
+ }
+ }
+
+ if (ssd == sensor->src && sel->pad == CCS_PAD_SRC) {
+ sel->r.left = 0;
+ sel->r.top = 0;
+ }
+
+ sel->r.width = min(sel->r.width, src_size->width);
+ sel->r.height = min(sel->r.height, src_size->height);
+
+ sel->r.left = min_t(int, sel->r.left, src_size->width - sel->r.width);
+ sel->r.top = min_t(int, sel->r.top, src_size->height - sel->r.height);
+
+ *crops[sel->pad] = sel->r;
+
+ if (ssd != sensor->pixel_array && sel->pad == CCS_PAD_SINK)
+ ccs_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_CROP);
+
+ return 0;
+}
+
+static void ccs_get_native_size(struct ccs_subdev *ssd, struct v4l2_rect *r)
+{
+ r->top = 0;
+ r->left = 0;
+ r->width = CCS_LIM(ssd->sensor, X_ADDR_MAX) + 1;
+ r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
+}
+
+static int __ccs_get_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
+ struct v4l2_rect sink_fmt;
+ int ret;
+
+ ret = __ccs_sel_supported(subdev, sel);
+ if (ret)
+ return ret;
+
+ ccs_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
+
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ sink_fmt = ssd->sink_fmt;
+ } else {
+ struct v4l2_mbus_framefmt *fmt =
+ v4l2_subdev_get_try_format(subdev, cfg, ssd->sink_pad);
+
+ sink_fmt.left = 0;
+ sink_fmt.top = 0;
+ sink_fmt.width = fmt->width;
+ sink_fmt.height = fmt->height;
+ }
+
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ case V4L2_SEL_TGT_NATIVE_SIZE:
+ if (ssd == sensor->pixel_array)
+ ccs_get_native_size(ssd, &sel->r);
+ else if (sel->pad == ssd->sink_pad)
+ sel->r = sink_fmt;
+ else
+ sel->r = *comp;
+ break;
+ case V4L2_SEL_TGT_CROP:
+ case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ sel->r = *crops[sel->pad];
+ break;
+ case V4L2_SEL_TGT_COMPOSE:
+ sel->r = *comp;
+ break;
+ }
+
+ return 0;
+}
+
+static int ccs_get_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval;
+
+ mutex_lock(&sensor->mutex);
+ rval = __ccs_get_selection(subdev, cfg, sel);
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+}
+
+static int ccs_set_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int ret;
+
+ ret = __ccs_sel_supported(subdev, sel);
+ if (ret)
+ return ret;
+
+ mutex_lock(&sensor->mutex);
+
+ sel->r.left = max(0, sel->r.left & ~1);
+ sel->r.top = max(0, sel->r.top & ~1);
+ sel->r.width = CCS_ALIGN_DIM(sel->r.width, sel->flags);
+ sel->r.height = CCS_ALIGN_DIM(sel->r.height, sel->flags);
+
+ sel->r.width = max_t(unsigned int, CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ sel->r.width);
+ sel->r.height = max_t(unsigned int, CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ sel->r.height);
+
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+ ret = ccs_set_crop(subdev, cfg, sel);
+ break;
+ case V4L2_SEL_TGT_COMPOSE:
+ ret = ccs_set_compose(subdev, cfg, sel);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ mutex_unlock(&sensor->mutex);
+ return ret;
+}
+
+static int ccs_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+
+ *frames = sensor->frame_skip;
+ return 0;
+}
+
+static int ccs_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+
+ *lines = sensor->image_start;
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * sysfs attributes
+ */
+
+static ssize_t
+ccs_sysfs_nvm_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval;
+
+ if (!sensor->dev_init_done)
+ return -EBUSY;
+
+ rval = ccs_pm_get_init(sensor);
+ if (rval < 0)
+ return -ENODEV;
+
+ rval = ccs_read_nvm(sensor, buf, PAGE_SIZE);
+ if (rval < 0) {
+ pm_runtime_put(&client->dev);
+ dev_err(&client->dev, "nvm read failed\n");
+ return -ENODEV;
+ }
+
+ pm_runtime_mark_last_busy(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+
+ /*
+ * NVM is still way below a PAGE_SIZE, so we can safely
+ * assume this for now.
+ */
+ return rval;
+}
+static DEVICE_ATTR(nvm, S_IRUGO, ccs_sysfs_nvm_read, NULL);
+
+static ssize_t
+ccs_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_module_info *minfo = &sensor->minfo;
+
+ if (minfo->mipi_manufacturer_id)
+ return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n",
+ minfo->mipi_manufacturer_id, minfo->model_id,
+ minfo->revision_number) + 1;
+ else
+ return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
+ minfo->smia_manufacturer_id, minfo->model_id,
+ minfo->revision_number) + 1;
+}
+
+static DEVICE_ATTR(ident, S_IRUGO, ccs_sysfs_ident_read, NULL);
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev core operations
+ */
+
+static int ccs_identify_module(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct ccs_module_info *minfo = &sensor->minfo;
+ unsigned int i;
+ u32 rev;
+ int rval = 0;
+
+ /* Module info */
+ rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
+ &minfo->mipi_manufacturer_id);
+ if (!rval && !minfo->mipi_manufacturer_id)
+ rval = ccs_read_addr_8only(sensor,
+ SMIAPP_REG_U8_MANUFACTURER_ID,
+ &minfo->smia_manufacturer_id);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_MODEL_ID,
+ &minfo->model_id);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_MODULE_REVISION_NUMBER_MAJOR,
+ &rev);
+ if (!rval) {
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_MODULE_REVISION_NUMBER_MINOR,
+ &minfo->revision_number);
+ minfo->revision_number |= rev << 8;
+ }
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR,
+ &minfo->module_year);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_MONTH,
+ &minfo->module_month);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_DAY,
+ &minfo->module_day);
+
+ /* Sensor info */
+ if (!rval)
+ rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,
+ &minfo->sensor_mipi_manufacturer_id);
+ if (!rval && !minfo->sensor_mipi_manufacturer_id)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_MANUFACTURER_ID,
+ &minfo->sensor_smia_manufacturer_id);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_MODEL_ID,
+ &minfo->sensor_model_id);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_REVISION_NUMBER,
+ &minfo->sensor_revision_number);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_FIRMWARE_VERSION,
+ &minfo->sensor_firmware_version);
+
+ /* SMIA */
+ if (!rval)
+ rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version);
+ if (!rval && !minfo->ccs_version)
+ rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
+ &minfo->smia_version);
+ if (!rval && !minfo->ccs_version)
+ rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
+ &minfo->smiapp_version);
+
+ if (rval) {
+ dev_err(&client->dev, "sensor detection failed\n");
+ return -ENODEV;
+ }
+
+ if (minfo->mipi_manufacturer_id)
+ dev_dbg(&client->dev, "MIPI CCS module 0x%4.4x-0x%4.4x\n",
+ minfo->mipi_manufacturer_id, minfo->model_id);
+ else
+ dev_dbg(&client->dev, "SMIA module 0x%2.2x-0x%4.4x\n",
+ minfo->smia_manufacturer_id, minfo->model_id);
+
+ dev_dbg(&client->dev,
+ "module revision 0x%4.4x date %2.2d-%2.2d-%2.2d\n",
+ minfo->revision_number, minfo->module_year, minfo->module_month,
+ minfo->module_day);
+
+ if (minfo->sensor_mipi_manufacturer_id)
+ dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n",
+ minfo->sensor_mipi_manufacturer_id,
+ minfo->sensor_model_id);
+ else
+ dev_dbg(&client->dev, "SMIA sensor 0x%2.2x-0x%4.4x\n",
+ minfo->sensor_smia_manufacturer_id,
+ minfo->sensor_model_id);
+
+ dev_dbg(&client->dev,
+ "sensor revision 0x%2.2x firmware version 0x%2.2x\n",
+ minfo->sensor_revision_number, minfo->sensor_firmware_version);
+
+ if (minfo->ccs_version) {
+ dev_dbg(&client->dev, "MIPI CCS version %u.%u",
+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK)
+ >> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT,
+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK));
+ minfo->name = CCS_NAME;
+ } else {
+ dev_dbg(&client->dev,
+ "smia version %2.2d smiapp version %2.2d\n",
+ minfo->smia_version, minfo->smiapp_version);
+ minfo->name = SMIAPP_NAME;
+ }
+
+ /*
+ * Some modules have bad data in the lvalues below. Hope the
+ * rvalues have better stuff. The lvalues are module
+ * parameters whereas the rvalues are sensor parameters.
+ */
+ if (minfo->sensor_smia_manufacturer_id &&
+ !minfo->smia_manufacturer_id && !minfo->model_id) {
+ minfo->smia_manufacturer_id =
+ minfo->sensor_smia_manufacturer_id;
+ minfo->model_id = minfo->sensor_model_id;
+ minfo->revision_number = minfo->sensor_revision_number;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ccs_module_idents); i++) {
+ if (ccs_module_idents[i].mipi_manufacturer_id &&
+ ccs_module_idents[i].mipi_manufacturer_id
+ != minfo->mipi_manufacturer_id)
+ continue;
+ if (ccs_module_idents[i].smia_manufacturer_id &&
+ ccs_module_idents[i].smia_manufacturer_id
+ != minfo->smia_manufacturer_id)
+ continue;
+ if (ccs_module_idents[i].model_id != minfo->model_id)
+ continue;
+ if (ccs_module_idents[i].flags
+ & CCS_MODULE_IDENT_FLAG_REV_LE) {
+ if (ccs_module_idents[i].revision_number_major
+ < (minfo->revision_number >> 8))
+ continue;
+ } else {
+ if (ccs_module_idents[i].revision_number_major
+ != (minfo->revision_number >> 8))
+ continue;
+ }
+
+ minfo->name = ccs_module_idents[i].name;
+ minfo->quirk = ccs_module_idents[i].quirk;
+ break;
+ }
+
+ if (i >= ARRAY_SIZE(ccs_module_idents))
+ dev_warn(&client->dev,
+ "no quirks for this module; let's hope it's fully compliant\n");
+
+ dev_dbg(&client->dev, "the sensor is called %s\n", minfo->name);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_ops ccs_ops;
+static const struct v4l2_subdev_internal_ops ccs_internal_ops;
+static const struct media_entity_operations ccs_entity_ops;
+
+static int ccs_register_subdev(struct ccs_sensor *sensor,
+ struct ccs_subdev *ssd,
+ struct ccs_subdev *sink_ssd,
+ u16 source_pad, u16 sink_pad, u32 link_flags)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ if (!sink_ssd)
+ return 0;
+
+ rval = media_entity_pads_init(&ssd->sd.entity, ssd->npads, ssd->pads);
+ if (rval) {
+ dev_err(&client->dev, "media_entity_pads_init failed\n");
+ return rval;
+ }
+
+ rval = v4l2_device_register_subdev(sensor->src->sd.v4l2_dev, &ssd->sd);
+ if (rval) {
+ dev_err(&client->dev, "v4l2_device_register_subdev failed\n");
+ return rval;
+ }
+
+ rval = media_create_pad_link(&ssd->sd.entity, source_pad,
+ &sink_ssd->sd.entity, sink_pad,
+ link_flags);
+ if (rval) {
+ dev_err(&client->dev, "media_create_pad_link failed\n");
+ v4l2_device_unregister_subdev(&ssd->sd);
+ return rval;
+ }
+
+ return 0;
+}
+
+static void ccs_unregistered(struct v4l2_subdev *subdev)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ unsigned int i;
+
+ for (i = 1; i < sensor->ssds_used; i++)
+ v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
+}
+
+static int ccs_registered(struct v4l2_subdev *subdev)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval;
+
+ if (sensor->scaler) {
+ rval = ccs_register_subdev(sensor, sensor->binner,
+ sensor->scaler,
+ CCS_PAD_SRC, CCS_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (rval < 0)
+ return rval;
+ }
+
+ rval = ccs_register_subdev(sensor, sensor->pixel_array, sensor->binner,
+ CCS_PA_PAD_SRC, CCS_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (rval)
+ goto out_err;
+
+ return 0;
+
+out_err:
+ ccs_unregistered(subdev);
+
+ return rval;
+}
+
+static void ccs_cleanup(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+
+ device_remove_file(&client->dev, &dev_attr_nvm);
+ device_remove_file(&client->dev, &dev_attr_ident);
+
+ ccs_free_controls(sensor);
+}
+
+static void ccs_create_subdev(struct ccs_sensor *sensor,
+ struct ccs_subdev *ssd, const char *name,
+ unsigned short num_pads, u32 function)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+
+ if (!ssd)
+ return;
+
+ if (ssd != sensor->src)
+ v4l2_subdev_init(&ssd->sd, &ccs_ops);
+
+ ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ ssd->sd.entity.function = function;
+ ssd->sensor = sensor;
+
+ ssd->npads = num_pads;
+ ssd->source_pad = num_pads - 1;
+
+ v4l2_i2c_subdev_set_name(&ssd->sd, client, sensor->minfo.name, name);
+
+ ccs_get_native_size(ssd, &ssd->sink_fmt);
+
+ ssd->compose.width = ssd->sink_fmt.width;
+ ssd->compose.height = ssd->sink_fmt.height;
+ ssd->crop[ssd->source_pad] = ssd->compose;
+ ssd->pads[ssd->source_pad].flags = MEDIA_PAD_FL_SOURCE;
+ if (ssd != sensor->pixel_array) {
+ ssd->crop[ssd->sink_pad] = ssd->compose;
+ ssd->pads[ssd->sink_pad].flags = MEDIA_PAD_FL_SINK;
+ }
+
+ ssd->sd.entity.ops = &ccs_entity_ops;
+
+ if (ssd == sensor->src)
+ return;
+
+ ssd->sd.internal_ops = &ccs_internal_ops;
+ ssd->sd.owner = THIS_MODULE;
+ ssd->sd.dev = &client->dev;
+ v4l2_set_subdevdata(&ssd->sd, client);
+}
+
+static int ccs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ struct ccs_subdev *ssd = to_ccs_subdev(sd);
+ struct ccs_sensor *sensor = ssd->sensor;
+ unsigned int i;
+
+ mutex_lock(&sensor->mutex);
+
+ for (i = 0; i < ssd->npads; i++) {
+ struct v4l2_mbus_framefmt *try_fmt =
+ v4l2_subdev_get_try_format(sd, fh->pad, i);
+ struct v4l2_rect *try_crop =
+ v4l2_subdev_get_try_crop(sd, fh->pad, i);
+ struct v4l2_rect *try_comp;
+
+ ccs_get_native_size(ssd, try_crop);
+
+ try_fmt->width = try_crop->width;
+ try_fmt->height = try_crop->height;
+ try_fmt->code = sensor->internal_csi_format->code;
+ try_fmt->field = V4L2_FIELD_NONE;
+
+ if (ssd != sensor->pixel_array)
+ continue;
+
+ try_comp = v4l2_subdev_get_try_compose(sd, fh->pad, i);
+ *try_comp = *try_crop;
+ }
+
+ mutex_unlock(&sensor->mutex);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_video_ops ccs_video_ops = {
+ .s_stream = ccs_set_stream,
+};
+
+static const struct v4l2_subdev_pad_ops ccs_pad_ops = {
+ .enum_mbus_code = ccs_enum_mbus_code,
+ .get_fmt = ccs_get_format,
+ .set_fmt = ccs_set_format,
+ .get_selection = ccs_get_selection,
+ .set_selection = ccs_set_selection,
+};
+
+static const struct v4l2_subdev_sensor_ops ccs_sensor_ops = {
+ .g_skip_frames = ccs_get_skip_frames,
+ .g_skip_top_lines = ccs_get_skip_top_lines,
+};
+
+static const struct v4l2_subdev_ops ccs_ops = {
+ .video = &ccs_video_ops,
+ .pad = &ccs_pad_ops,
+ .sensor = &ccs_sensor_ops,
+};
+
+static const struct media_entity_operations ccs_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct v4l2_subdev_internal_ops ccs_internal_src_ops = {
+ .registered = ccs_registered,
+ .unregistered = ccs_unregistered,
+ .open = ccs_open,
+};
+
+static const struct v4l2_subdev_internal_ops ccs_internal_ops = {
+ .open = ccs_open,
+};
+
+/* -----------------------------------------------------------------------------
+ * I2C Driver
+ */
+
+static int __maybe_unused ccs_suspend(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ bool streaming = sensor->streaming;
+ int rval;
+
+ rval = pm_runtime_get_sync(dev);
+ if (rval < 0) {
+ pm_runtime_put_noidle(dev);
+
+ return -EAGAIN;
+ }
+
+ if (sensor->streaming)
+ ccs_stop_streaming(sensor);
+
+ /* save state for resume */
+ sensor->streaming = streaming;
+
+ return 0;
+}
+
+static int __maybe_unused ccs_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval = 0;
+
+ pm_runtime_put(dev);
+
+ if (sensor->streaming)
+ rval = ccs_start_streaming(sensor);
+
+ return rval;
+}
+
+static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
+{
+ struct ccs_hwconfig *hwcfg = &sensor->hwcfg;
+ struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = V4L2_MBUS_UNKNOWN };
+ struct fwnode_handle *ep;
+ struct fwnode_handle *fwnode = dev_fwnode(dev);
+ u32 rotation;
+ int i;
+ int rval;
+
+ ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
+ if (!ep)
+ return -ENODEV;
+
+ /*
+ * Note that we do need to rely on detecting the bus type between CSI-2
+ * D-PHY and CCP2 as the old bindings did not require it.
+ */
+ rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ if (rval)
+ goto out_err;
+
+ switch (bus_cfg.bus_type) {
+ case V4L2_MBUS_CSI2_DPHY:
+ hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
+ hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
+ break;
+ case V4L2_MBUS_CSI2_CPHY:
+ hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_CPHY;
+ hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
+ break;
+ case V4L2_MBUS_CSI1:
+ case V4L2_MBUS_CCP2:
+ hwcfg->csi_signalling_mode = (bus_cfg.bus.mipi_csi1.strobe) ?
+ SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE :
+ SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK;
+ hwcfg->lanes = 1;
+ break;
+ default:
+ dev_err(dev, "unsupported bus %u\n", bus_cfg.bus_type);
+ rval = -EINVAL;
+ goto out_err;
+ }
+
+ dev_dbg(dev, "lanes %u\n", hwcfg->lanes);
+
+ rval = fwnode_property_read_u32(fwnode, "rotation", &rotation);
+ if (!rval) {
+ switch (rotation) {
+ case 180:
+ hwcfg->module_board_orient =
+ CCS_MODULE_BOARD_ORIENT_180;
+ fallthrough;
+ case 0:
+ break;
+ default:
+ dev_err(dev, "invalid rotation %u\n", rotation);
+ rval = -EINVAL;
+ goto out_err;
+ }
+ }
+
+ rval = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
+ &hwcfg->ext_clk);
+ if (rval)
+ dev_info(dev, "can't get clock-frequency\n");
+
+ dev_dbg(dev, "clk %d, mode %d\n", hwcfg->ext_clk,
+ hwcfg->csi_signalling_mode);
+
+ if (!bus_cfg.nr_of_link_frequencies) {
+ dev_warn(dev, "no link frequencies defined\n");
+ rval = -EINVAL;
+ goto out_err;
+ }
+
+ hwcfg->op_sys_clock = devm_kcalloc(
+ dev, bus_cfg.nr_of_link_frequencies + 1 /* guardian */,
+ sizeof(*hwcfg->op_sys_clock), GFP_KERNEL);
+ if (!hwcfg->op_sys_clock) {
+ rval = -ENOMEM;
+ goto out_err;
+ }
+
+ for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
+ hwcfg->op_sys_clock[i] = bus_cfg.link_frequencies[i];
+ dev_dbg(dev, "freq %d: %lld\n", i, hwcfg->op_sys_clock[i]);
+ }
+
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+ fwnode_handle_put(ep);
+
+ return 0;
+
+out_err:
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+ fwnode_handle_put(ep);
+
+ return rval;
+}
+
+static int ccs_probe(struct i2c_client *client)
+{
+ struct ccs_sensor *sensor;
+ const struct firmware *fw;
+ char filename[40];
+ unsigned int i;
+ int rval;
+
+ sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
+ if (sensor == NULL)
+ return -ENOMEM;
+
+ rval = ccs_get_hwconfig(sensor, &client->dev);
+ if (rval)
+ return rval;
+
+ sensor->src = &sensor->ssds[sensor->ssds_used];
+
+ v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops);
+ sensor->src->sd.internal_ops = &ccs_internal_src_ops;
+
+ sensor->regulators = devm_kcalloc(&client->dev,
+ ARRAY_SIZE(ccs_regulators),
+ sizeof(*sensor->regulators),
+ GFP_KERNEL);
+ if (!sensor->regulators)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_regulators); i++)
+ sensor->regulators[i].supply = ccs_regulators[i];
+
+ rval = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+ if (rval) {
+ dev_err(&client->dev, "could not get regulators\n");
+ return rval;
+ }
+
+ sensor->ext_clk = devm_clk_get(&client->dev, NULL);
+ if (PTR_ERR(sensor->ext_clk) == -ENOENT) {
+ dev_info(&client->dev, "no clock defined, continuing...\n");
+ sensor->ext_clk = NULL;
+ } else if (IS_ERR(sensor->ext_clk)) {
+ dev_err(&client->dev, "could not get clock (%ld)\n",
+ PTR_ERR(sensor->ext_clk));
+ return -EPROBE_DEFER;
+ }
+
+ if (sensor->ext_clk) {
+ if (sensor->hwcfg.ext_clk) {
+ unsigned long rate;
+
+ rval = clk_set_rate(sensor->ext_clk,
+ sensor->hwcfg.ext_clk);
+ if (rval < 0) {
+ dev_err(&client->dev,
+ "unable to set clock freq to %u\n",
+ sensor->hwcfg.ext_clk);
+ return rval;
+ }
+
+ rate = clk_get_rate(sensor->ext_clk);
+ if (rate != sensor->hwcfg.ext_clk) {
+ dev_err(&client->dev,
+ "can't set clock freq, asked for %u but got %lu\n",
+ sensor->hwcfg.ext_clk, rate);
+ return -EINVAL;
+ }
+ } else {
+ sensor->hwcfg.ext_clk = clk_get_rate(sensor->ext_clk);
+ dev_dbg(&client->dev, "obtained clock freq %u\n",
+ sensor->hwcfg.ext_clk);
+ }
+ } else if (sensor->hwcfg.ext_clk) {
+ dev_dbg(&client->dev, "assuming clock freq %u\n",
+ sensor->hwcfg.ext_clk);
+ } else {
+ dev_err(&client->dev, "unable to obtain clock freq\n");
+ return -EINVAL;
+ }
+
+ sensor->reset = devm_gpiod_get_optional(&client->dev, "reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(sensor->reset))
+ return PTR_ERR(sensor->reset);
+ /* Support old users that may have used "xshutdown" property. */
+ if (!sensor->reset)
+ sensor->xshutdown = devm_gpiod_get_optional(&client->dev,
+ "xshutdown",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(sensor->xshutdown))
+ return PTR_ERR(sensor->xshutdown);
+
+ rval = ccs_power_on(&client->dev);
+ if (rval < 0)
+ return rval;
+
+ mutex_init(&sensor->mutex);
+
+ rval = ccs_identify_module(sensor);
+ if (rval) {
+ rval = -ENODEV;
+ goto out_power_off;
+ }
+
+ rval = snprintf(filename, sizeof(filename),
+ "ccs/ccs-sensor-%4.4x-%4.4x-%4.4x.fw",
+ sensor->minfo.sensor_mipi_manufacturer_id,
+ sensor->minfo.sensor_model_id,
+ sensor->minfo.sensor_revision_number);
+ if (rval >= sizeof(filename)) {
+ rval = -ENOMEM;
+ goto out_power_off;
+ }
+
+ rval = request_firmware(&fw, filename, &client->dev);
+ if (!rval) {
+ ccs_data_parse(&sensor->sdata, fw->data, fw->size, &client->dev,
+ true);
+ release_firmware(fw);
+ }
+
+ rval = snprintf(filename, sizeof(filename),
+ "ccs/ccs-module-%4.4x-%4.4x-%4.4x.fw",
+ sensor->minfo.mipi_manufacturer_id,
+ sensor->minfo.model_id,
+ sensor->minfo.revision_number);
+ if (rval >= sizeof(filename)) {
+ rval = -ENOMEM;
+ goto out_release_sdata;
+ }
+
+ rval = request_firmware(&fw, filename, &client->dev);
+ if (!rval) {
+ ccs_data_parse(&sensor->mdata, fw->data, fw->size, &client->dev,
+ true);
+ release_firmware(fw);
+ }
+
+ rval = ccs_read_all_limits(sensor);
+ if (rval)
+ goto out_release_mdata;
+
+ rval = ccs_read_frame_fmt(sensor);
+ if (rval) {
+ rval = -ENODEV;
+ goto out_free_ccs_limits;
+ }
+
+ /*
+ * Handle Sensor Module orientation on the board.
+ *
+ * The application of H-FLIP and V-FLIP on the sensor is modified by
+ * the sensor orientation on the board.
+ *
+ * For CCS_BOARD_SENSOR_ORIENT_180 the default behaviour is to set
+ * both H-FLIP and V-FLIP for normal operation which also implies
+ * that a set/unset operation for user space HFLIP and VFLIP v4l2
+ * controls will need to be internally inverted.
+ *
+ * Rotation also changes the bayer pattern.
+ */
+ if (sensor->hwcfg.module_board_orient ==
+ CCS_MODULE_BOARD_ORIENT_180)
+ sensor->hvflip_inv_mask =
+ CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR |
+ CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
+
+ rval = ccs_call_quirk(sensor, limits);
+ if (rval) {
+ dev_err(&client->dev, "limits quirks failed\n");
+ goto out_free_ccs_limits;
+ }
+
+ if (CCS_LIM(sensor, BINNING_CAPABILITY)) {
+ sensor->nbinning_subtypes =
+ min_t(u8, CCS_LIM(sensor, BINNING_SUB_TYPES),
+ CCS_LIM_BINNING_SUB_TYPE_MAX_N);
+
+ for (i = 0; i < sensor->nbinning_subtypes; i++) {
+ sensor->binning_subtypes[i].horizontal =
+ CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) >>
+ CCS_BINNING_SUB_TYPE_COLUMN_SHIFT;
+ sensor->binning_subtypes[i].vertical =
+ CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) &
+ CCS_BINNING_SUB_TYPE_ROW_MASK;
+
+ dev_dbg(&client->dev, "binning %xx%x\n",
+ sensor->binning_subtypes[i].horizontal,
+ sensor->binning_subtypes[i].vertical);
+ }
+ }
+ sensor->binning_horizontal = 1;
+ sensor->binning_vertical = 1;
+
+ if (device_create_file(&client->dev, &dev_attr_ident) != 0) {
+ dev_err(&client->dev, "sysfs ident entry creation failed\n");
+ rval = -ENOENT;
+ goto out_free_ccs_limits;
+ }
+
+ if (sensor->minfo.smiapp_version &&
+ CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
+ CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
+ if (device_create_file(&client->dev, &dev_attr_nvm) != 0) {
+ dev_err(&client->dev, "sysfs nvm entry failed\n");
+ rval = -EBUSY;
+ goto out_cleanup;
+ }
+ }
+
+ if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
+ !CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
+ !CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
+ !CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
+ /* No OP clock branch */
+ sensor->pll.flags |= CCS_PLL_FLAG_NO_OP_CLOCKS;
+ } else if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE ||
+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ /* We have a scaler or digital crop. */
+ sensor->scaler = &sensor->ssds[sensor->ssds_used];
+ sensor->ssds_used++;
+ }
+ sensor->binner = &sensor->ssds[sensor->ssds_used];
+ sensor->ssds_used++;
+ sensor->pixel_array = &sensor->ssds[sensor->ssds_used];
+ sensor->ssds_used++;
+
+ sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
+
+ /* prepare PLL configuration input values */
+ sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
+ sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_LANE_SPEED) {
+ sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_LINK_DECOUPLED) {
+ sensor->pll.vt_lanes =
+ CCS_LIM(sensor, NUM_OF_VT_LANES) + 1;
+ sensor->pll.op_lanes =
+ CCS_LIM(sensor, NUM_OF_OP_LANES) + 1;
+ sensor->pll.flags |= CCS_PLL_FLAG_LINK_DECOUPLED;
+ } else {
+ sensor->pll.vt_lanes = sensor->pll.csi2.lanes;
+ sensor->pll.op_lanes = sensor->pll.csi2.lanes;
+ }
+ }
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER)
+ sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV)
+ sensor->pll.flags |= CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV;
+ if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) &
+ CCS_FIFO_SUPPORT_CAPABILITY_DERATING)
+ sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING;
+ if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) &
+ CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING)
+ sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING |
+ CCS_PLL_FLAG_FIFO_OVERRATING;
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL) {
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL) {
+ u32 v;
+
+ /* Use sensor default in PLL mode selection */
+ rval = ccs_read(sensor, PLL_MODE, &v);
+ if (rval)
+ goto out_cleanup;
+
+ if (v == CCS_PLL_MODE_DUAL)
+ sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
+ } else {
+ sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
+ }
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR)
+ sensor->pll.flags |= CCS_PLL_FLAG_OP_SYS_DDR;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR)
+ sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_DDR;
+ }
+ sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
+ sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
+ sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
+
+ ccs_create_subdev(sensor, sensor->scaler, " scaler", 2,
+ MEDIA_ENT_F_CAM_SENSOR);
+ ccs_create_subdev(sensor, sensor->binner, " binner", 2,
+ MEDIA_ENT_F_PROC_VIDEO_SCALER);
+ ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1,
+ MEDIA_ENT_F_PROC_VIDEO_SCALER);
+
+ rval = ccs_init_controls(sensor);
+ if (rval < 0)
+ goto out_cleanup;
+
+ rval = ccs_call_quirk(sensor, init);
+ if (rval)
+ goto out_cleanup;
+
+ rval = ccs_get_mbus_formats(sensor);
+ if (rval) {
+ rval = -ENODEV;
+ goto out_cleanup;
+ }
+
+ rval = ccs_init_late_controls(sensor);
+ if (rval) {
+ rval = -ENODEV;
+ goto out_cleanup;
+ }
+
+ mutex_lock(&sensor->mutex);
+ rval = ccs_pll_blanking_update(sensor);
+ mutex_unlock(&sensor->mutex);
+ if (rval) {
+ dev_err(&client->dev, "update mode failed\n");
+ goto out_cleanup;
+ }
+
+ sensor->streaming = false;
+ sensor->dev_init_done = true;
+
+ rval = media_entity_pads_init(&sensor->src->sd.entity, 2,
+ sensor->src->pads);
+ if (rval < 0)
+ goto out_media_entity_cleanup;
+
+ rval = ccs_write_msr_regs(sensor);
+ if (rval)
+ goto out_media_entity_cleanup;
+
+ pm_runtime_set_active(&client->dev);
+ pm_runtime_get_noresume(&client->dev);
+ pm_runtime_enable(&client->dev);
+
+ rval = v4l2_async_register_subdev_sensor_common(&sensor->src->sd);
+ if (rval < 0)
+ goto out_disable_runtime_pm;
+
+ pm_runtime_set_autosuspend_delay(&client->dev, 1000);
+ pm_runtime_use_autosuspend(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+
+ return 0;
+
+out_disable_runtime_pm:
+ pm_runtime_put_noidle(&client->dev);
+ pm_runtime_disable(&client->dev);
+
+out_media_entity_cleanup:
+ media_entity_cleanup(&sensor->src->sd.entity);
+
+out_cleanup:
+ ccs_cleanup(sensor);
+
+out_release_mdata:
+ kvfree(sensor->mdata.backing);
+
+out_release_sdata:
+ kvfree(sensor->sdata.backing);
+
+out_free_ccs_limits:
+ kfree(sensor->ccs_limits);
+
+out_power_off:
+ ccs_power_off(&client->dev);
+ mutex_destroy(&sensor->mutex);
+
+ return rval;
+}
+
+static int ccs_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ unsigned int i;
+
+ v4l2_async_unregister_subdev(subdev);
+
+ pm_runtime_disable(&client->dev);
+ if (!pm_runtime_status_suspended(&client->dev))
+ ccs_power_off(&client->dev);
+ pm_runtime_set_suspended(&client->dev);
+
+ for (i = 0; i < sensor->ssds_used; i++) {
+ v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
+ media_entity_cleanup(&sensor->ssds[i].sd.entity);
+ }
+ ccs_cleanup(sensor);
+ mutex_destroy(&sensor->mutex);
+ kfree(sensor->ccs_limits);
+ kvfree(sensor->sdata.backing);
+ kvfree(sensor->mdata.backing);
+
+ return 0;
+}
+
+static const struct ccs_device smia_device = {
+ .flags = CCS_DEVICE_FLAG_IS_SMIA,
+};
+
+static const struct ccs_device ccs_device = {};
+
+static const struct acpi_device_id ccs_acpi_table[] = {
+ { .id = "MIPI0200", .driver_data = (unsigned long)&ccs_device },
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, ccs_acpi_table);
+
+static const struct of_device_id ccs_of_table[] = {
+ { .compatible = "mipi-ccs-1.1", .data = &ccs_device },
+ { .compatible = "mipi-ccs-1.0", .data = &ccs_device },
+ { .compatible = "mipi-ccs", .data = &ccs_device },
+ { .compatible = "nokia,smia", .data = &smia_device },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ccs_of_table);
+
+static const struct dev_pm_ops ccs_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume)
+ SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL)
+};
+
+static struct i2c_driver ccs_i2c_driver = {
+ .driver = {
+ .acpi_match_table = ccs_acpi_table,
+ .of_match_table = ccs_of_table,
+ .name = CCS_NAME,
+ .pm = &ccs_pm_ops,
+ },
+ .probe_new = ccs_probe,
+ .remove = ccs_remove,
+};
+
+static int ccs_module_init(void)
+{
+ unsigned int i, l;
+
+ for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) {
+ if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) {
+ ccs_limit_offsets[l + 1].lim =
+ ALIGN(ccs_limit_offsets[l].lim +
+ ccs_limits[i].size,
+ ccs_reg_width(ccs_limits[i + 1].reg));
+ ccs_limit_offsets[l].info = i;
+ l++;
+ } else {
+ ccs_limit_offsets[l].lim += ccs_limits[i].size;
+ }
+ }
+
+ if (WARN_ON(ccs_limits[i].size))
+ return -EINVAL;
+
+ if (WARN_ON(l != CCS_L_LAST))
+ return -EINVAL;
+
+ return i2c_register_driver(THIS_MODULE, &ccs_i2c_driver);
+}
+
+static void ccs_module_cleanup(void)
+{
+ i2c_del_driver(&ccs_i2c_driver);
+}
+
+module_init(ccs_module_init);
+module_exit(ccs_module_cleanup);
+
+MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
+MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("smiapp");
diff --git a/drivers/media/i2c/ccs/ccs-data-defs.h b/drivers/media/i2c/ccs/ccs-data-defs.h
new file mode 100644
index 000000000000..1c9b1d1acd50
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data-defs.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * CCS static data binary format definitions
+ *
+ * Copyright 2019--2020 Intel Corporation
+ */
+
+#ifndef __CCS_DATA_DEFS_H__
+#define __CCS_DATA_DEFS_H__
+
+#include "ccs-data.h"
+
+#define CCS_STATIC_DATA_VERSION 0
+
+enum __ccs_data_length_specifier_id {
+ CCS_DATA_LENGTH_SPECIFIER_1 = 0,
+ CCS_DATA_LENGTH_SPECIFIER_2 = 1,
+ CCS_DATA_LENGTH_SPECIFIER_3 = 2
+};
+
+#define CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT 6
+
+struct __ccs_data_length_specifier {
+ u8 length;
+} __packed;
+
+struct __ccs_data_length_specifier2 {
+ u8 length[2];
+} __packed;
+
+struct __ccs_data_length_specifier3 {
+ u8 length[3];
+} __packed;
+
+struct __ccs_data_block {
+ u8 id;
+ struct __ccs_data_length_specifier length;
+} __packed;
+
+#define CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT 5
+
+struct __ccs_data_block3 {
+ u8 id;
+ struct __ccs_data_length_specifier2 length;
+} __packed;
+
+struct __ccs_data_block4 {
+ u8 id;
+ struct __ccs_data_length_specifier3 length;
+} __packed;
+
+enum __ccs_data_block_id {
+ CCS_DATA_BLOCK_ID_DUMMY = 1,
+ CCS_DATA_BLOCK_ID_DATA_VERSION = 2,
+ CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS = 3,
+ CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS = 4,
+ CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS = 5,
+ CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS = 6,
+ CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK = 32,
+ CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK = 33,
+ CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION = 36,
+ CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION = 37,
+ CCS_DATA_BLOCK_ID_LICENSE = 40,
+ CCS_DATA_BLOCK_ID_END = 127,
+};
+
+struct __ccs_data_block_version {
+ u8 static_data_version_major[2];
+ u8 static_data_version_minor[2];
+ u8 year[2];
+ u8 month;
+ u8 day;
+} __packed;
+
+struct __ccs_data_block_regs {
+ u8 reg_len;
+} __packed;
+
+#define CCS_DATA_BLOCK_REGS_ADDR_MASK 0x07
+#define CCS_DATA_BLOCK_REGS_LEN_SHIFT 3
+#define CCS_DATA_BLOCK_REGS_LEN_MASK 0x38
+#define CCS_DATA_BLOCK_REGS_SEL_SHIFT 6
+
+enum ccs_data_block_regs_sel {
+ CCS_DATA_BLOCK_REGS_SEL_REGS = 0,
+ CCS_DATA_BLOCK_REGS_SEL_REGS2 = 1,
+ CCS_DATA_BLOCK_REGS_SEL_REGS3 = 2,
+};
+
+struct __ccs_data_block_regs2 {
+ u8 reg_len;
+ u8 addr;
+} __packed;
+
+#define CCS_DATA_BLOCK_REGS_2_ADDR_MASK 0x01
+#define CCS_DATA_BLOCK_REGS_2_LEN_SHIFT 1
+#define CCS_DATA_BLOCK_REGS_2_LEN_MASK 0x3e
+
+struct __ccs_data_block_regs3 {
+ u8 reg_len;
+ u8 addr[2];
+} __packed;
+
+#define CCS_DATA_BLOCK_REGS_3_LEN_MASK 0x3f
+
+enum __ccs_data_ffd_pixelcode {
+ CCS_DATA_BLOCK_FFD_PIXELCODE_EMBEDDED = 1,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_DUMMY = 2,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BLACK = 3,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_DARK = 4,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_VISIBLE = 5,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_0 = 8,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_1 = 9,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_2 = 10,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_3 = 11,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_4 = 12,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_5 = 13,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_6 = 14,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_OB = 16,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_OB = 17,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_OB = 18,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_OB = 19,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_OB = 20,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_OB = 21,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_OB = 22,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_OB = 23,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOTAL = 24,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_PDAF = 32,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_PDAF = 33,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_PDAF = 34,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_PDAF = 35,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_PDAF = 36,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_PDAF = 37,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_PDAF = 38,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_PDAF = 39,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_SEPARATED_PDAF = 40,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_ORIGINAL_ORDER_PDAF = 41,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_VENDOR_PDAF = 41,
+};
+
+struct __ccs_data_block_ffd_entry {
+ u8 pixelcode;
+ u8 reserved;
+ u8 value[2];
+} __packed;
+
+struct __ccs_data_block_ffd {
+ u8 num_column_descs;
+ u8 num_row_descs;
+} __packed;
+
+enum __ccs_data_block_rule_id {
+ CCS_DATA_BLOCK_RULE_ID_IF = 1,
+ CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS = 2,
+ CCS_DATA_BLOCK_RULE_ID_FFD = 3,
+ CCS_DATA_BLOCK_RULE_ID_MSR = 4,
+ CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT = 5,
+};
+
+struct __ccs_data_block_rule_if {
+ u8 addr[2];
+ u8 value;
+ u8 mask;
+} __packed;
+
+enum __ccs_data_block_pdaf_readout_order {
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_ORIGINAL = 1,
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_WITHIN_LINE = 2,
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_TYPES_SEPARATE_LINES = 3,
+};
+
+struct __ccs_data_block_pdaf_readout {
+ u8 pdaf_readout_info_reserved;
+ u8 pdaf_readout_info_order;
+} __packed;
+
+struct __ccs_data_block_pdaf_pix_loc_block_desc {
+ u8 block_type_id;
+ u8 repeat_x[2];
+} __packed;
+
+struct __ccs_data_block_pdaf_pix_loc_block_desc_group {
+ u8 num_block_descs[2];
+ u8 repeat_y;
+} __packed;
+
+enum __ccs_data_block_pdaf_pix_loc_pixel_type {
+ CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SEPARATED = 0,
+ CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SEPARATED = 1,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_SEPARATED = 2,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SEPARATED = 3,
+ CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SIDE_BY_SIDE = 4,
+ CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SIDE_BY_SIDE = 5,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_SIDE_BY_SIDE = 6,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SIDE_BY_SIDE = 7,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_LEFT = 8,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_RIGHT = 9,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_LEFT = 10,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_RIGHT = 11,
+};
+
+struct __ccs_data_block_pdaf_pix_loc_pixel_desc {
+ u8 pixel_type;
+ u8 small_offset_x;
+ u8 small_offset_y;
+} __packed;
+
+struct __ccs_data_block_pdaf_pix_loc {
+ u8 main_offset_x[2];
+ u8 main_offset_y[2];
+ u8 global_pdaf_type;
+ u8 block_width;
+ u8 block_height;
+ u8 num_block_desc_groups[2];
+} __packed;
+
+struct __ccs_data_block_end {
+ u8 crc[4];
+} __packed;
+
+#endif /* __CCS_DATA_DEFS_H__ */
diff --git a/drivers/media/i2c/ccs/ccs-data.c b/drivers/media/i2c/ccs/ccs-data.c
new file mode 100644
index 000000000000..9a6097b088bd
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data.c
@@ -0,0 +1,953 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * CCS static data binary parser library
+ *
+ * Copyright 2019--2020 Intel Corporation
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/limits.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "ccs-data-defs.h"
+
+struct bin_container {
+ void *base;
+ void *now;
+ void *end;
+ size_t size;
+};
+
+static void *bin_alloc(struct bin_container *bin, size_t len)
+{
+ void *ptr;
+
+ len = ALIGN(len, 8);
+
+ if (bin->end - bin->now < len)
+ return NULL;
+
+ ptr = bin->now;
+ bin->now += len;
+
+ return ptr;
+}
+
+static void bin_reserve(struct bin_container *bin, size_t len)
+{
+ bin->size += ALIGN(len, 8);
+}
+
+static int bin_backing_alloc(struct bin_container *bin)
+{
+ bin->base = bin->now = kvzalloc(bin->size, GFP_KERNEL);
+ if (!bin->base)
+ return -ENOMEM;
+
+ bin->end = bin->base + bin->size;
+
+ return 0;
+}
+
+#define is_contained(var, endp) \
+ (sizeof(*var) <= (endp) - (void *)(var))
+#define has_headroom(ptr, headroom, endp) \
+ ((headroom) <= (endp) - (void *)(ptr))
+#define is_contained_with_headroom(var, headroom, endp) \
+ (sizeof(*var) + (headroom) <= (endp) - (void *)(var))
+
+static int
+ccs_data_parse_length_specifier(const struct __ccs_data_length_specifier *__len,
+ size_t *__hlen, size_t *__plen,
+ const void *endp)
+{
+ size_t hlen, plen;
+
+ if (!is_contained(__len, endp))
+ return -ENODATA;
+
+ switch (__len->length >> CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) {
+ case CCS_DATA_LENGTH_SPECIFIER_1:
+ hlen = sizeof(*__len);
+ plen = __len->length &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1);
+ break;
+ case CCS_DATA_LENGTH_SPECIFIER_2: {
+ struct __ccs_data_length_specifier2 *__len2 = (void *)__len;
+
+ if (!is_contained(__len2, endp))
+ return -ENODATA;
+
+ hlen = sizeof(*__len2);
+ plen = ((size_t)
+ (__len2->length[0] &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
+ << 8) + __len2->length[1];
+ break;
+ }
+ case CCS_DATA_LENGTH_SPECIFIER_3: {
+ struct __ccs_data_length_specifier3 *__len3 = (void *)__len;
+
+ if (!is_contained(__len3, endp))
+ return -ENODATA;
+
+ hlen = sizeof(*__len3);
+ plen = ((size_t)
+ (__len3->length[0] &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
+ << 16) + (__len3->length[0] << 8) + __len3->length[1];
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
+
+ if (!has_headroom(__len, hlen + plen, endp))
+ return -ENODATA;
+
+ *__hlen = hlen;
+ *__plen = plen;
+
+ return 0;
+}
+
+static u8
+ccs_data_parse_format_version(const struct __ccs_data_block *block)
+{
+ return block->id >> CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT;
+}
+
+static u8 ccs_data_parse_block_id(const struct __ccs_data_block *block,
+ bool is_first)
+{
+ if (!is_first)
+ return block->id;
+
+ return block->id & ((1 << CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT) - 1);
+}
+
+static int ccs_data_parse_version(struct bin_container *bin,
+ struct ccs_data_container *ccsdata,
+ const void *payload, const void *endp)
+{
+ const struct __ccs_data_block_version *v = payload;
+ struct ccs_data_block_version *vv;
+
+ if (v + 1 != endp)
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(*ccsdata->version));
+ return 0;
+ }
+
+ ccsdata->version = bin_alloc(bin, sizeof(*ccsdata->version));
+ if (!ccsdata->version)
+ return -ENOMEM;
+
+ vv = ccsdata->version;
+ vv->version_major = ((u16)v->static_data_version_major[0] << 8) +
+ v->static_data_version_major[1];
+ vv->version_minor = ((u16)v->static_data_version_minor[0] << 8) +
+ v->static_data_version_major[1];
+ vv->date_year = ((u16)v->year[0] << 8) + v->year[1];
+ vv->date_month = v->month;
+ vv->date_day = v->day;
+
+ return 0;
+}
+
+static void print_ccs_data_version(struct device *dev,
+ struct ccs_data_block_version *v)
+{
+ dev_dbg(dev,
+ "static data version %4.4x.%4.4x, date %4.4u-%2.2u-%2.2u\n",
+ v->version_major, v->version_minor,
+ v->date_year, v->date_month, v->date_day);
+}
+
+static int ccs_data_block_parse_header(const struct __ccs_data_block *block,
+ bool is_first, unsigned int *__block_id,
+ const void **payload,
+ const struct __ccs_data_block **next_block,
+ const void *endp, struct device *dev,
+ bool verbose)
+{
+ size_t plen, hlen;
+ u8 block_id;
+ int rval;
+
+ if (!is_contained(block, endp))
+ return -ENODATA;
+
+ rval = ccs_data_parse_length_specifier(&block->length, &hlen, &plen,
+ endp);
+ if (rval < 0)
+ return rval;
+
+ block_id = ccs_data_parse_block_id(block, is_first);
+
+ if (verbose)
+ dev_dbg(dev,
+ "Block ID 0x%2.2x, header length %zu, payload length %zu\n",
+ block_id, hlen, plen);
+
+ if (!has_headroom(&block->length, hlen + plen, endp))
+ return -ENODATA;
+
+ if (__block_id)
+ *__block_id = block_id;
+
+ if (payload)
+ *payload = (void *)&block->length + hlen;
+
+ if (next_block)
+ *next_block = (void *)&block->length + hlen + plen;
+
+ return 0;
+}
+
+static int ccs_data_parse_regs(struct bin_container *bin,
+ struct ccs_reg **__regs,
+ size_t *__num_regs, const void *payload,
+ const void *endp, struct device *dev)
+{
+ struct ccs_reg *regs_base, *regs;
+ size_t num_regs = 0;
+ u16 addr = 0;
+
+ if (bin->base && __regs) {
+ regs = regs_base = bin_alloc(bin, sizeof(*regs) * *__num_regs);
+ if (!regs)
+ return -ENOMEM;
+ }
+
+ while (payload < endp && num_regs < INT_MAX) {
+ const struct __ccs_data_block_regs *r = payload;
+ size_t len;
+ const void *data;
+
+ if (!is_contained(r, endp))
+ return -ENODATA;
+
+ switch (r->reg_len >> CCS_DATA_BLOCK_REGS_SEL_SHIFT) {
+ case CCS_DATA_BLOCK_REGS_SEL_REGS:
+ addr += r->reg_len & CCS_DATA_BLOCK_REGS_ADDR_MASK;
+ len = ((r->reg_len & CCS_DATA_BLOCK_REGS_LEN_MASK)
+ >> CCS_DATA_BLOCK_REGS_LEN_SHIFT) + 1;
+
+ if (!is_contained_with_headroom(r, len, endp))
+ return -ENODATA;
+
+ data = r + 1;
+ break;
+ case CCS_DATA_BLOCK_REGS_SEL_REGS2: {
+ const struct __ccs_data_block_regs2 *r2 = payload;
+
+ if (!is_contained(r2, endp))
+ return -ENODATA;
+
+ addr += ((u16)(r2->reg_len &
+ CCS_DATA_BLOCK_REGS_2_ADDR_MASK) << 8)
+ + r2->addr;
+ len = ((r2->reg_len & CCS_DATA_BLOCK_REGS_2_LEN_MASK)
+ >> CCS_DATA_BLOCK_REGS_2_LEN_SHIFT) + 1;
+
+ if (!is_contained_with_headroom(r2, len, endp))
+ return -ENODATA;
+
+ data = r2 + 1;
+ break;
+ }
+ case CCS_DATA_BLOCK_REGS_SEL_REGS3: {
+ const struct __ccs_data_block_regs3 *r3 = payload;
+
+ if (!is_contained(r3, endp))
+ return -ENODATA;
+
+ addr = ((u16)r3->addr[0] << 8) + r3->addr[1];
+ len = (r3->reg_len & CCS_DATA_BLOCK_REGS_3_LEN_MASK) + 1;
+
+ if (!is_contained_with_headroom(r3, len, endp))
+ return -ENODATA;
+
+ data = r3 + 1;
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
+
+ num_regs++;
+
+ if (!bin->base) {
+ bin_reserve(bin, len);
+ } else if (__regs) {
+ regs->addr = addr;
+ regs->len = len;
+ regs->value = bin_alloc(bin, len);
+ if (!regs->value)
+ return -ENOMEM;
+
+ memcpy(regs->value, data, len);
+ regs++;
+ }
+
+ addr += len;
+ payload = data + len;
+ }
+
+ if (!bin->base)
+ bin_reserve(bin, sizeof(*regs) * num_regs);
+
+ if (__num_regs)
+ *__num_regs = num_regs;
+
+ if (bin->base && __regs)
+ *__regs = regs_base;
+
+ return 0;
+}
+
+static int ccs_data_parse_reg_rules(struct bin_container *bin,
+ struct ccs_reg **__regs,
+ size_t *__num_regs,
+ const void *payload,
+ const void *endp, struct device *dev)
+{
+ int rval;
+
+ if (!bin->base)
+ return ccs_data_parse_regs(bin, NULL, NULL, payload, endp, dev);
+
+ rval = ccs_data_parse_regs(bin, NULL, __num_regs, payload, endp, dev);
+ if (rval)
+ return rval;
+
+ return ccs_data_parse_regs(bin, __regs, __num_regs, payload, endp,
+ dev);
+}
+
+static void assign_ffd_entry(struct ccs_frame_format_desc *desc,
+ const struct __ccs_data_block_ffd_entry *ent)
+{
+ desc->pixelcode = ent->pixelcode;
+ desc->value = ((u16)ent->value[0] << 8) + ent->value[1];
+}
+
+static int ccs_data_parse_ffd(struct bin_container *bin,
+ struct ccs_frame_format_descs **ffd,
+ const void *payload,
+ const void *endp, struct device *dev)
+{
+ const struct __ccs_data_block_ffd *__ffd = payload;
+ const struct __ccs_data_block_ffd_entry *__entry;
+ unsigned int i;
+
+ if (!is_contained(__ffd, endp))
+ return -ENODATA;
+
+ if ((void *)__ffd + sizeof(*__ffd) +
+ ((u32)__ffd->num_column_descs +
+ (u32)__ffd->num_row_descs) *
+ sizeof(struct __ccs_data_block_ffd_entry) != endp)
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(**ffd));
+ bin_reserve(bin, __ffd->num_column_descs *
+ sizeof(struct ccs_frame_format_desc));
+ bin_reserve(bin, __ffd->num_row_descs *
+ sizeof(struct ccs_frame_format_desc));
+
+ return 0;
+ }
+
+ *ffd = bin_alloc(bin, sizeof(**ffd));
+ if (!*ffd)
+ return -ENOMEM;
+
+ (*ffd)->num_column_descs = __ffd->num_column_descs;
+ (*ffd)->num_row_descs = __ffd->num_row_descs;
+ __entry = (void *)(__ffd + 1);
+
+ (*ffd)->column_descs = bin_alloc(bin, __ffd->num_column_descs *
+ sizeof(*(*ffd)->column_descs));
+ if (!(*ffd)->column_descs)
+ return -ENOMEM;
+
+ for (i = 0; i < __ffd->num_column_descs; i++, __entry++)
+ assign_ffd_entry(&(*ffd)->column_descs[i], __entry);
+
+ (*ffd)->row_descs = bin_alloc(bin, __ffd->num_row_descs *
+ sizeof(*(*ffd)->row_descs));
+ if (!(*ffd)->row_descs)
+ return -ENOMEM;
+
+ for (i = 0; i < __ffd->num_row_descs; i++, __entry++)
+ assign_ffd_entry(&(*ffd)->row_descs[i], __entry);
+
+ if (__entry != endp)
+ return -EPROTO;
+
+ return 0;
+}
+
+static int ccs_data_parse_pdaf_readout(struct bin_container *bin,
+ struct ccs_pdaf_readout **pdaf_readout,
+ const void *payload,
+ const void *endp, struct device *dev)
+{
+ const struct __ccs_data_block_pdaf_readout *__pdaf = payload;
+
+ if (!is_contained(__pdaf, endp))
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(**pdaf_readout));
+ } else {
+ *pdaf_readout = bin_alloc(bin, sizeof(**pdaf_readout));
+ if (!*pdaf_readout)
+ return -ENOMEM;
+
+ (*pdaf_readout)->pdaf_readout_info_order =
+ __pdaf->pdaf_readout_info_order;
+ }
+
+ return ccs_data_parse_ffd(bin, !bin->base ? NULL : &(*pdaf_readout)->ffd,
+ __pdaf + 1, endp, dev);
+}
+
+static int ccs_data_parse_rules(struct bin_container *bin,
+ struct ccs_rule **__rules,
+ size_t *__num_rules, const void *payload,
+ const void *endp, struct device *dev)
+{
+ struct ccs_rule *rules_base, *rules = NULL, *next_rule;
+ size_t num_rules = 0;
+ const void *__next_rule = payload;
+ int rval;
+
+ if (bin->base) {
+ rules_base = next_rule =
+ bin_alloc(bin, sizeof(*rules) * *__num_rules);
+ if (!rules_base)
+ return -ENOMEM;
+ }
+
+ while (__next_rule < endp) {
+ size_t rule_hlen, rule_plen, rule_plen2;
+ const u8 *__rule_type;
+ const void *rule_payload;
+
+ /* Size of a single rule */
+ rval = ccs_data_parse_length_specifier(__next_rule, &rule_hlen,
+ &rule_plen, endp);
+
+ if (rval < 0)
+ return rval;
+
+ __rule_type = __next_rule + rule_hlen;
+
+ if (!is_contained(__rule_type, endp))
+ return -ENODATA;
+
+ rule_payload = __rule_type + 1;
+ rule_plen2 = rule_plen - sizeof(*__rule_type);
+
+ switch (*__rule_type) {
+ case CCS_DATA_BLOCK_RULE_ID_IF: {
+ const struct __ccs_data_block_rule_if *__if_rules =
+ rule_payload;
+ const size_t __num_if_rules =
+ rule_plen2 / sizeof(*__if_rules);
+ struct ccs_if_rule *if_rule;
+
+ if (!has_headroom(__if_rules,
+ sizeof(*__if_rules) * __num_if_rules,
+ rule_payload + rule_plen2))
+ return -ENODATA;
+
+ /* Also check there is no extra data */
+ if (__if_rules + __num_if_rules !=
+ rule_payload + rule_plen2)
+ return -EINVAL;
+
+ if (!bin->base) {
+ bin_reserve(bin,
+ sizeof(*if_rule) *
+ __num_if_rules);
+ num_rules++;
+ } else {
+ unsigned int i;
+
+ rules = next_rule;
+ next_rule++;
+
+ if_rule = bin_alloc(bin,
+ sizeof(*if_rule) *
+ __num_if_rules);
+ if (!if_rule)
+ return -ENOMEM;
+
+ for (i = 0; i < __num_if_rules; i++) {
+ if_rule[i].addr =
+ ((u16)__if_rules[i].addr[0]
+ << 8) +
+ __if_rules[i].addr[1];
+ if_rule[i].value = __if_rules[i].value;
+ if_rule[i].mask = __if_rules[i].mask;
+ }
+
+ rules->if_rules = if_rule;
+ rules->num_if_rules = __num_if_rules;
+ }
+ break;
+ }
+ case CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS:
+ rval = ccs_data_parse_reg_rules(bin, &rules->read_only_regs,
+ &rules->num_read_only_regs,
+ rule_payload,
+ rule_payload + rule_plen2,
+ dev);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_FFD:
+ rval = ccs_data_parse_ffd(bin, &rules->frame_format,
+ rule_payload,
+ rule_payload + rule_plen2,
+ dev);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_MSR:
+ rval = ccs_data_parse_reg_rules(bin,
+ &rules->manufacturer_regs,
+ &rules->num_manufacturer_regs,
+ rule_payload,
+ rule_payload + rule_plen2,
+ dev);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT:
+ rval = ccs_data_parse_pdaf_readout(bin,
+ &rules->pdaf_readout,
+ rule_payload,
+ rule_payload + rule_plen2,
+ dev);
+ if (rval)
+ return rval;
+ break;
+ default:
+ dev_dbg(dev,
+ "Don't know how to handle rule type %u!\n",
+ *__rule_type);
+ return -EINVAL;
+ }
+ __next_rule = __next_rule + rule_hlen + rule_plen;
+ }
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(*rules) * num_rules);
+ *__num_rules = num_rules;
+ } else {
+ *__rules = rules_base;
+ }
+
+ return 0;
+}
+
+static int ccs_data_parse_pdaf(struct bin_container *bin, struct ccs_pdaf_pix_loc **pdaf,
+ const void *payload, const void *endp,
+ struct device *dev)
+{
+ const struct __ccs_data_block_pdaf_pix_loc *__pdaf = payload;
+ const struct __ccs_data_block_pdaf_pix_loc_block_desc_group *__bdesc_group;
+ const struct __ccs_data_block_pdaf_pix_loc_pixel_desc *__pixel_desc;
+ unsigned int i;
+ u16 num_block_desc_groups;
+ u8 max_block_type_id = 0;
+ const u8 *__num_pixel_descs;
+
+ if (!is_contained(__pdaf, endp))
+ return -ENODATA;
+
+ if (bin->base) {
+ *pdaf = bin_alloc(bin, sizeof(**pdaf));
+ if (!*pdaf)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(**pdaf));
+ }
+
+ num_block_desc_groups =
+ ((u16)__pdaf->num_block_desc_groups[0] << 8) +
+ __pdaf->num_block_desc_groups[1];
+
+ if (bin->base) {
+ (*pdaf)->main_offset_x =
+ ((u16)__pdaf->main_offset_x[0] << 8) +
+ __pdaf->main_offset_x[1];
+ (*pdaf)->main_offset_y =
+ ((u16)__pdaf->main_offset_y[0] << 8) +
+ __pdaf->main_offset_y[1];
+ (*pdaf)->global_pdaf_type = __pdaf->global_pdaf_type;
+ (*pdaf)->block_width = __pdaf->block_width;
+ (*pdaf)->block_height = __pdaf->block_height;
+ (*pdaf)->num_block_desc_groups = num_block_desc_groups;
+ }
+
+ __bdesc_group = (const void *)(__pdaf + 1);
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
+ num_block_desc_groups);
+ if (!(*pdaf)->block_desc_groups)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
+ num_block_desc_groups);
+ }
+
+ for (i = 0; i < num_block_desc_groups; i++) {
+ const struct __ccs_data_block_pdaf_pix_loc_block_desc *__bdesc;
+ u16 num_block_descs;
+ unsigned int j;
+
+ if (!is_contained(__bdesc_group, endp))
+ return -ENODATA;
+
+ num_block_descs =
+ ((u16)__bdesc_group->num_block_descs[0] << 8) +
+ __bdesc_group->num_block_descs[1];
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups[i].repeat_y =
+ __bdesc_group->repeat_y;
+ (*pdaf)->block_desc_groups[i].num_block_descs =
+ num_block_descs;
+ }
+
+ __bdesc = (const void *)(__bdesc_group + 1);
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups[i].block_descs =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_block_desc) *
+ num_block_descs);
+ if (!(*pdaf)->block_desc_groups[i].block_descs)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc) *
+ num_block_descs);
+ }
+
+ for (j = 0; j < num_block_descs; j++, __bdesc++) {
+ struct ccs_pdaf_pix_loc_block_desc *bdesc;
+
+ if (!is_contained(__bdesc, endp))
+ return -ENODATA;
+
+ if (max_block_type_id <= __bdesc->block_type_id)
+ max_block_type_id = __bdesc->block_type_id + 1;
+
+ if (!bin->base)
+ continue;
+
+ bdesc = &(*pdaf)->block_desc_groups[i].block_descs[j];
+
+ bdesc->repeat_x = ((u16)__bdesc->repeat_x[0] << 8)
+ + __bdesc->repeat_x[1];
+
+ if (__bdesc->block_type_id >= num_block_descs)
+ return -EINVAL;
+
+ bdesc->block_type_id = __bdesc->block_type_id;
+ }
+
+ __bdesc_group = (const void *)__bdesc;
+ }
+
+ __num_pixel_descs = (const void *)__bdesc_group;
+
+ if (bin->base) {
+ (*pdaf)->pixel_desc_groups =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
+ max_block_type_id);
+ if (!(*pdaf)->pixel_desc_groups)
+ return -ENOMEM;
+ (*pdaf)->num_pixel_desc_grups = max_block_type_id;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
+ max_block_type_id);
+ }
+
+ for (i = 0; i < max_block_type_id; i++) {
+ struct ccs_pdaf_pix_loc_pixel_desc_group *pdgroup;
+ unsigned int j;
+
+ if (!is_contained(__num_pixel_descs, endp))
+ return -ENODATA;
+
+ if (bin->base) {
+ pdgroup = &(*pdaf)->pixel_desc_groups[i];
+ pdgroup->descs =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
+ *__num_pixel_descs);
+ if (!pdgroup->descs)
+ return -ENOMEM;
+ pdgroup->num_descs = *__num_pixel_descs;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
+ *__num_pixel_descs);
+ }
+
+ __pixel_desc = (const void *)(__num_pixel_descs + 1);
+
+ for (j = 0; j < *__num_pixel_descs; j++, __pixel_desc++) {
+ struct ccs_pdaf_pix_loc_pixel_desc *pdesc;
+
+ if (!is_contained(__pixel_desc, endp))
+ return -ENODATA;
+
+ if (!bin->base)
+ continue;
+
+ pdesc = &pdgroup->descs[j];
+ pdesc->pixel_type = __pixel_desc->pixel_type;
+ pdesc->small_offset_x = __pixel_desc->small_offset_x;
+ pdesc->small_offset_y = __pixel_desc->small_offset_y;
+ }
+
+ __num_pixel_descs = (const void *)(__pixel_desc + 1);
+ }
+
+ return 0;
+}
+
+static int ccs_data_parse_license(struct bin_container *bin,
+ char **__license,
+ size_t *__license_length,
+ const void *payload, const void *endp)
+{
+ size_t size = endp - payload;
+ char *license;
+
+ if (!bin->base) {
+ bin_reserve(bin, size);
+ return 0;
+ }
+
+ license = bin_alloc(bin, size);
+ if (!license)
+ return -ENOMEM;
+
+ memcpy(license, payload, size);
+
+ *__license = license;
+ *__license_length = size;
+
+ return 0;
+}
+
+static int ccs_data_parse_end(bool *end, const void *payload, const void *endp,
+ struct device *dev)
+{
+ const struct __ccs_data_block_end *__end = payload;
+
+ if (__end + 1 != endp) {
+ dev_dbg(dev, "Invalid end block length %u\n",
+ (unsigned int)(endp - payload));
+ return -ENODATA;
+ }
+
+ *end = true;
+
+ return 0;
+}
+
+static int __ccs_data_parse(struct bin_container *bin,
+ struct ccs_data_container *ccsdata,
+ const void *data, size_t len, struct device *dev,
+ bool verbose)
+{
+ const struct __ccs_data_block *block = data;
+ const struct __ccs_data_block *endp = data + len;
+ unsigned int version;
+ bool is_first = true;
+ int rval;
+
+ version = ccs_data_parse_format_version(block);
+ if (version != CCS_STATIC_DATA_VERSION) {
+ dev_dbg(dev, "Don't know how to handle version %u\n", version);
+ return -EINVAL;
+ }
+
+ if (verbose)
+ dev_dbg(dev, "Parsing CCS static data version %u\n", version);
+
+ if (!bin->base)
+ *ccsdata = (struct ccs_data_container){ 0 };
+
+ while (block < endp) {
+ const struct __ccs_data_block *next_block;
+ unsigned int block_id;
+ const void *payload;
+
+ rval = ccs_data_block_parse_header(block, is_first, &block_id,
+ &payload, &next_block, endp,
+ dev,
+ bin->base ? false : verbose);
+
+ if (rval < 0)
+ return rval;
+
+ switch (block_id) {
+ case CCS_DATA_BLOCK_ID_DUMMY:
+ break;
+ case CCS_DATA_BLOCK_ID_DATA_VERSION:
+ rval = ccs_data_parse_version(bin, ccsdata, payload,
+ next_block);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->sensor_read_only_regs,
+ &ccsdata->num_sensor_read_only_regs, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->sensor_manufacturer_regs,
+ &ccsdata->num_sensor_manufacturer_regs, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->module_read_only_regs,
+ &ccsdata->num_module_read_only_regs, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->module_manufacturer_regs,
+ &ccsdata->num_module_manufacturer_regs, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION:
+ rval = ccs_data_parse_pdaf(bin, &ccsdata->sensor_pdaf,
+ payload, next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION:
+ rval = ccs_data_parse_pdaf(bin, &ccsdata->module_pdaf,
+ payload, next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK:
+ rval = ccs_data_parse_rules(
+ bin, &ccsdata->sensor_rules,
+ &ccsdata->num_sensor_rules, payload, next_block,
+ dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK:
+ rval = ccs_data_parse_rules(
+ bin, &ccsdata->module_rules,
+ &ccsdata->num_module_rules, payload, next_block,
+ dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_LICENSE:
+ rval = ccs_data_parse_license(bin, &ccsdata->license,
+ &ccsdata->license_length,
+ payload, next_block);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_END:
+ rval = ccs_data_parse_end(&ccsdata->end, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ default:
+ dev_dbg(dev, "WARNING: not handling block ID 0x%2.2x\n",
+ block_id);
+ }
+
+ block = next_block;
+ is_first = false;
+ }
+
+ return 0;
+}
+
+/**
+ * ccs_data_parse - Parse a CCS static data file into a usable in-memory
+ * data structure
+ * @ccsdata: CCS static data in-memory data structure
+ * @data: CCS static data binary
+ * @len: Length of @data
+ * @dev: Device the data is related to (used for printing debug messages)
+ * @verbose: Whether to be verbose or not
+ */
+int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data,
+ size_t len, struct device *dev, bool verbose)
+{
+ struct bin_container bin = { 0 };
+ int rval;
+
+ rval = __ccs_data_parse(&bin, ccsdata, data, len, dev, verbose);
+ if (rval)
+ return rval;
+
+ rval = bin_backing_alloc(&bin);
+ if (rval)
+ return rval;
+
+ rval = __ccs_data_parse(&bin, ccsdata, data, len, dev, false);
+ if (rval)
+ goto out_free;
+
+ if (verbose && ccsdata->version)
+ print_ccs_data_version(dev, ccsdata->version);
+
+ if (bin.now != bin.end) {
+ rval = -EPROTO;
+ dev_dbg(dev, "parsing mismatch; base %p; now %p; end %p\n",
+ bin.base, bin.now, bin.end);
+ goto out_free;
+ }
+
+ ccsdata->backing = bin.base;
+
+ return 0;
+
+out_free:
+ kvfree(bin.base);
+
+ return rval;
+}
diff --git a/drivers/media/i2c/ccs/ccs-data.h b/drivers/media/i2c/ccs/ccs-data.h
new file mode 100644
index 000000000000..50d6508b24f3
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * CCS static data in-memory data structure definitions
+ *
+ * Copyright 2019--2020 Intel Corporation
+ */
+
+#ifndef __CCS_DATA_H__
+#define __CCS_DATA_H__
+
+#include <linux/types.h>
+
+/**
+ * struct ccs_data_block_version - CCS static data version
+ * @version_major: Major version number
+ * @version_minor: Minor version number
+ * @date_year: Year
+ * @date_month: Month
+ * @date_day: Day
+ */
+struct ccs_data_block_version {
+ u16 version_major;
+ u16 version_minor;
+ u16 date_year;
+ u8 date_month;
+ u8 date_day;
+};
+
+/**
+ * struct ccs_reg - CCS register value
+ * @addr: The 16-bit address of the register
+ * @len: Length of the data
+ * @value: Data
+ */
+struct ccs_reg {
+ u16 addr;
+ u16 len;
+ u8 *value;
+};
+
+/**
+ * struct ccs_if_rule - CCS static data if rule
+ * @addr: Register address
+ * @value: Register value
+ * @mask: Value applied to both actual register value and @value
+ */
+struct ccs_if_rule {
+ u16 addr;
+ u8 value;
+ u8 mask;
+};
+
+/**
+ * struct ccs_frame_format_desc - CCS frame format descriptor
+ * @pixelcode: The pixelcode; CCS_DATA_BLOCK_FFD_PIXELCODE_*
+ * @value: Value related to the pixelcode
+ */
+struct ccs_frame_format_desc {
+ u8 pixelcode;
+ u16 value;
+};
+
+/**
+ * struct ccs_frame_format_descs - A series of CCS frame format descriptors
+ * @num_column_descs: Number of column descriptors
+ * @num_row_descs: Number of row descriptors
+ * @column_descs: Column descriptors
+ * @row_descs: Row descriptors
+ */
+struct ccs_frame_format_descs {
+ u8 num_column_descs;
+ u8 num_row_descs;
+ struct ccs_frame_format_desc *column_descs;
+ struct ccs_frame_format_desc *row_descs;
+};
+
+/**
+ * struct ccs_pdaf_readout - CCS PDAF data readout descriptor
+ * @pdaf_readout_info_order: PDAF readout order
+ * @ffd: Frame format of PDAF data
+ */
+struct ccs_pdaf_readout {
+ u8 pdaf_readout_info_order;
+ struct ccs_frame_format_descs *ffd;
+};
+
+/**
+ * struct ccs_rule - A CCS static data rule
+ * @num_if_rules: Number of if rules
+ * @if_rules: If rules
+ * @num_read_only_regs: Number of read-only registers
+ * @read_only_regs: Read-only registers
+ * @num_manufacturer_regs: Number of manufacturer-specific registers
+ * @manufacturer_regs: Manufacturer-specific registers
+ * @frame_format: Frame format
+ * @pdaf_readout: PDAF readout
+ */
+struct ccs_rule {
+ size_t num_if_rules;
+ struct ccs_if_rule *if_rules;
+ size_t num_read_only_regs;
+ struct ccs_reg *read_only_regs;
+ size_t num_manufacturer_regs;
+ struct ccs_reg *manufacturer_regs;
+ struct ccs_frame_format_descs *frame_format;
+ struct ccs_pdaf_readout *pdaf_readout;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc_block_desc - PDAF pixel location block descriptor
+ * @block_type_id: Block type identifier, from 0 to n
+ * @repeat_x: Number of times this block is repeated to right
+ */
+struct ccs_pdaf_pix_loc_block_desc {
+ u8 block_type_id;
+ u16 repeat_x;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc_block_desc_group - PDAF pixel location block
+ * descriptor group
+ * @repeat_y: Number of times the group is repeated down
+ * @num_block_descs: Number of block descriptors in @block_descs
+ * @block_descs: Block descriptors
+ */
+struct ccs_pdaf_pix_loc_block_desc_group {
+ u8 repeat_y;
+ u16 num_block_descs;
+ struct ccs_pdaf_pix_loc_block_desc *block_descs;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc_block_desc - PDAF pixel location block descriptor
+ * @pixel_type: Type of the pixel; CCS_DATA_PDAF_PIXEL_TYPE_*
+ * @small_offset_x: offset X coordinate
+ * @small_offset_y: offset Y coordinate
+ */
+struct ccs_pdaf_pix_loc_pixel_desc {
+ u8 pixel_type;
+ u8 small_offset_x;
+ u8 small_offset_y;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc_pixel_desc_group - PDAF pixel location pixel
+ * descriptor group
+ * @num_descs: Number of descriptors in @descs
+ * @descs: PDAF pixel location pixel descriptors
+ */
+struct ccs_pdaf_pix_loc_pixel_desc_group {
+ u8 num_descs;
+ struct ccs_pdaf_pix_loc_pixel_desc *descs;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc - PDAF pixel locations
+ * @main_offset_x: Start X coordinate of PDAF pixel blocks
+ * @main_offset_y: Start Y coordinate of PDAF pixel blocks
+ * @global_pdaf_type: PDAF pattern type
+ * @block_width: Width of a block in pixels
+ * @block_height: Heigth of a block in pixels
+ * @num_block_desc_groups: Number of block descriptor groups
+ * @block_desc_groups: Block descriptor groups
+ * @num_pixel_desc_grups: Number of pixel descriptor groups
+ * @pixel_desc_groups: Pixel descriptor groups
+ */
+struct ccs_pdaf_pix_loc {
+ u16 main_offset_x;
+ u16 main_offset_y;
+ u8 global_pdaf_type;
+ u8 block_width;
+ u8 block_height;
+ u16 num_block_desc_groups;
+ struct ccs_pdaf_pix_loc_block_desc_group *block_desc_groups;
+ u8 num_pixel_desc_grups;
+ struct ccs_pdaf_pix_loc_pixel_desc_group *pixel_desc_groups;
+};
+
+/**
+ * struct ccs_data_container - In-memory CCS static data
+ * @version: CCS static data version
+ * @num_sensor_read_only_regs: Number of the read-only registers for the sensor
+ * @sensor_read_only_regs: Read-only registers for the sensor
+ * @num_sensor_manufacturer_regs: Number of the manufacturer-specific registers
+ * for the sensor
+ * @sensor_manufacturer_regs: Manufacturer-specific registers for the sensor
+ * @num_sensor_rules: Number of rules for the sensor
+ * @sensor_rules: Rules for the sensor
+ * @num_module_read_only_regs: Number of the read-only registers for the module
+ * @module_read_only_regs: Read-only registers for the module
+ * @num_module_manufacturer_regs: Number of the manufacturer-specific registers
+ * for the module
+ * @module_manufacturer_regs: Manufacturer-specific registers for the module
+ * @num_module_rules: Number of rules for the module
+ * @module_rules: Rules for the module
+ * @sensor_pdaf: PDAF data for the sensor
+ * @module_pdaf: PDAF data for the module
+ * @license_length: Lenght of the license data
+ * @license: License data
+ * @end: Whether or not there's an end block
+ * @backing: Raw data, pointed to from elsewhere so keep it around
+ */
+struct ccs_data_container {
+ struct ccs_data_block_version *version;
+ size_t num_sensor_read_only_regs;
+ struct ccs_reg *sensor_read_only_regs;
+ size_t num_sensor_manufacturer_regs;
+ struct ccs_reg *sensor_manufacturer_regs;
+ size_t num_sensor_rules;
+ struct ccs_rule *sensor_rules;
+ size_t num_module_read_only_regs;
+ struct ccs_reg *module_read_only_regs;
+ size_t num_module_manufacturer_regs;
+ struct ccs_reg *module_manufacturer_regs;
+ size_t num_module_rules;
+ struct ccs_rule *module_rules;
+ struct ccs_pdaf_pix_loc *sensor_pdaf;
+ struct ccs_pdaf_pix_loc *module_pdaf;
+ size_t license_length;
+ char *license;
+ bool end;
+ void *backing;
+};
+
+int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data,
+ size_t len, struct device *dev, bool verbose);
+
+#endif /* __CCS_DATA_H__ */
diff --git a/drivers/media/i2c/ccs/ccs-limits.c b/drivers/media/i2c/ccs/ccs-limits.c
new file mode 100644
index 000000000000..f5511789ac83
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-limits.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+/* Copyright (C) 2019--2020 Intel Corporation */
+
+#include "ccs-limits.h"
+#include "ccs-regs.h"
+
+const struct ccs_limit ccs_limits[] = {
+ { CCS_R_FRAME_FORMAT_MODEL_TYPE, 1, 0, "frame_format_model_type" },
+ { CCS_R_FRAME_FORMAT_MODEL_SUBTYPE, 1, 0, "frame_format_model_subtype" },
+ { CCS_R_FRAME_FORMAT_DESCRIPTOR(0), 30, 0, "frame_format_descriptor" },
+ { CCS_R_FRAME_FORMAT_DESCRIPTOR_4(0), 32, 0, "frame_format_descriptor_4" },
+ { CCS_R_ANALOG_GAIN_CAPABILITY, 2, 0, "analog_gain_capability" },
+ { CCS_R_ANALOG_GAIN_CODE_MIN, 2, 0, "analog_gain_code_min" },
+ { CCS_R_ANALOG_GAIN_CODE_MAX, 2, 0, "analog_gain_code_max" },
+ { CCS_R_ANALOG_GAIN_CODE_STEP, 2, 0, "analog_gain_code_step" },
+ { CCS_R_ANALOG_GAIN_TYPE, 2, 0, "analog_gain_type" },
+ { CCS_R_ANALOG_GAIN_M0, 2, 0, "analog_gain_m0" },
+ { CCS_R_ANALOG_GAIN_C0, 2, 0, "analog_gain_c0" },
+ { CCS_R_ANALOG_GAIN_M1, 2, 0, "analog_gain_m1" },
+ { CCS_R_ANALOG_GAIN_C1, 2, 0, "analog_gain_c1" },
+ { CCS_R_ANALOG_LINEAR_GAIN_MIN, 2, 0, "analog_linear_gain_min" },
+ { CCS_R_ANALOG_LINEAR_GAIN_MAX, 2, 0, "analog_linear_gain_max" },
+ { CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE, 2, 0, "analog_linear_gain_step_size" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN, 2, 0, "analog_exponential_gain_min" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX, 2, 0, "analog_exponential_gain_max" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE, 2, 0, "analog_exponential_gain_step_size" },
+ { CCS_R_DATA_FORMAT_MODEL_TYPE, 1, 0, "data_format_model_type" },
+ { CCS_R_DATA_FORMAT_MODEL_SUBTYPE, 1, 0, "data_format_model_subtype" },
+ { CCS_R_DATA_FORMAT_DESCRIPTOR(0), 32, 0, "data_format_descriptor" },
+ { CCS_R_INTEGRATION_TIME_CAPABILITY, 2, 0, "integration_time_capability" },
+ { CCS_R_COARSE_INTEGRATION_TIME_MIN, 2, 0, "coarse_integration_time_min" },
+ { CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "coarse_integration_time_max_margin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MIN, 2, 0, "fine_integration_time_min" },
+ { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "fine_integration_time_max_margin" },
+ { CCS_R_DIGITAL_GAIN_CAPABILITY, 1, 0, "digital_gain_capability" },
+ { CCS_R_DIGITAL_GAIN_MIN, 2, 0, "digital_gain_min" },
+ { CCS_R_DIGITAL_GAIN_MAX, 2, 0, "digital_gain_max" },
+ { CCS_R_DIGITAL_GAIN_STEP_SIZE, 2, 0, "digital_gain_step_size" },
+ { CCS_R_PEDESTAL_CAPABILITY, 1, 0, "Pedestal_capability" },
+ { CCS_R_ADC_CAPABILITY, 1, 0, "ADC_capability" },
+ { CCS_R_ADC_BIT_DEPTH_CAPABILITY, 4, 0, "ADC_bit_depth_capability" },
+ { CCS_R_MIN_EXT_CLK_FREQ_MHZ, 4, 0, "min_ext_clk_freq_mhz" },
+ { CCS_R_MAX_EXT_CLK_FREQ_MHZ, 4, 0, "max_ext_clk_freq_mhz" },
+ { CCS_R_MIN_PRE_PLL_CLK_DIV, 2, 0, "min_pre_pll_clk_div" },
+ { CCS_R_MAX_PRE_PLL_CLK_DIV, 2, 0, "max_pre_pll_clk_div" },
+ { CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_pll_ip_clk_freq_mhz" },
+ { CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_pll_ip_clk_freq_mhz" },
+ { CCS_R_MIN_PLL_MULTIPLIER, 2, 0, "min_pll_multiplier" },
+ { CCS_R_MAX_PLL_MULTIPLIER, 2, 0, "max_pll_multiplier" },
+ { CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_pll_op_clk_freq_mhz" },
+ { CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_pll_op_clk_freq_mhz" },
+ { CCS_R_MIN_VT_SYS_CLK_DIV, 2, 0, "min_vt_sys_clk_div" },
+ { CCS_R_MAX_VT_SYS_CLK_DIV, 2, 0, "max_vt_sys_clk_div" },
+ { CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ, 4, 0, "min_vt_sys_clk_freq_mhz" },
+ { CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ, 4, 0, "max_vt_sys_clk_freq_mhz" },
+ { CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ, 4, 0, "min_vt_pix_clk_freq_mhz" },
+ { CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ, 4, 0, "max_vt_pix_clk_freq_mhz" },
+ { CCS_R_MIN_VT_PIX_CLK_DIV, 2, 0, "min_vt_pix_clk_div" },
+ { CCS_R_MAX_VT_PIX_CLK_DIV, 2, 0, "max_vt_pix_clk_div" },
+ { CCS_R_CLOCK_CALCULATION, 1, 0, "clock_calculation" },
+ { CCS_R_NUM_OF_VT_LANES, 1, 0, "num_of_vt_lanes" },
+ { CCS_R_NUM_OF_OP_LANES, 1, 0, "num_of_op_lanes" },
+ { CCS_R_OP_BITS_PER_LANE, 1, 0, "op_bits_per_lane" },
+ { CCS_R_MIN_FRAME_LENGTH_LINES, 2, 0, "min_frame_length_lines" },
+ { CCS_R_MAX_FRAME_LENGTH_LINES, 2, 0, "max_frame_length_lines" },
+ { CCS_R_MIN_LINE_LENGTH_PCK, 2, 0, "min_line_length_pck" },
+ { CCS_R_MAX_LINE_LENGTH_PCK, 2, 0, "max_line_length_pck" },
+ { CCS_R_MIN_LINE_BLANKING_PCK, 2, 0, "min_line_blanking_pck" },
+ { CCS_R_MIN_FRAME_BLANKING_LINES, 2, 0, "min_frame_blanking_lines" },
+ { CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE, 1, 0, "min_line_length_pck_step_size" },
+ { CCS_R_TIMING_MODE_CAPABILITY, 1, 0, "timing_mode_capability" },
+ { CCS_R_FRAME_MARGIN_MAX_VALUE, 2, 0, "frame_margin_max_value" },
+ { CCS_R_FRAME_MARGIN_MIN_VALUE, 1, 0, "frame_margin_min_value" },
+ { CCS_R_GAIN_DELAY_TYPE, 1, 0, "gain_delay_type" },
+ { CCS_R_MIN_OP_SYS_CLK_DIV, 2, 0, "min_op_sys_clk_div" },
+ { CCS_R_MAX_OP_SYS_CLK_DIV, 2, 0, "max_op_sys_clk_div" },
+ { CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ, 4, 0, "min_op_sys_clk_freq_mhz" },
+ { CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ, 4, 0, "max_op_sys_clk_freq_mhz" },
+ { CCS_R_MIN_OP_PIX_CLK_DIV, 2, 0, "min_op_pix_clk_div" },
+ { CCS_R_MAX_OP_PIX_CLK_DIV, 2, 0, "max_op_pix_clk_div" },
+ { CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ, 4, 0, "min_op_pix_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ, 4, 0, "max_op_pix_clk_freq_mhz" },
+ { CCS_R_X_ADDR_MIN, 2, 0, "x_addr_min" },
+ { CCS_R_Y_ADDR_MIN, 2, 0, "y_addr_min" },
+ { CCS_R_X_ADDR_MAX, 2, 0, "x_addr_max" },
+ { CCS_R_Y_ADDR_MAX, 2, 0, "y_addr_max" },
+ { CCS_R_MIN_X_OUTPUT_SIZE, 2, 0, "min_x_output_size" },
+ { CCS_R_MIN_Y_OUTPUT_SIZE, 2, 0, "min_y_output_size" },
+ { CCS_R_MAX_X_OUTPUT_SIZE, 2, 0, "max_x_output_size" },
+ { CCS_R_MAX_Y_OUTPUT_SIZE, 2, 0, "max_y_output_size" },
+ { CCS_R_X_ADDR_START_DIV_CONSTANT, 1, 0, "x_addr_start_div_constant" },
+ { CCS_R_Y_ADDR_START_DIV_CONSTANT, 1, 0, "y_addr_start_div_constant" },
+ { CCS_R_X_ADDR_END_DIV_CONSTANT, 1, 0, "x_addr_end_div_constant" },
+ { CCS_R_Y_ADDR_END_DIV_CONSTANT, 1, 0, "y_addr_end_div_constant" },
+ { CCS_R_X_SIZE_DIV, 1, 0, "x_size_div" },
+ { CCS_R_Y_SIZE_DIV, 1, 0, "y_size_div" },
+ { CCS_R_X_OUTPUT_DIV, 1, 0, "x_output_div" },
+ { CCS_R_Y_OUTPUT_DIV, 1, 0, "y_output_div" },
+ { CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT, 1, 0, "non_flexible_resolution_support" },
+ { CCS_R_MIN_OP_PRE_PLL_CLK_DIV, 2, 0, "min_op_pre_pll_clk_div" },
+ { CCS_R_MAX_OP_PRE_PLL_CLK_DIV, 2, 0, "max_op_pre_pll_clk_div" },
+ { CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_ip_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_ip_clk_freq_mhz" },
+ { CCS_R_MIN_OP_PLL_MULTIPLIER, 2, 0, "min_op_pll_multiplier" },
+ { CCS_R_MAX_OP_PLL_MULTIPLIER, 2, 0, "max_op_pll_multiplier" },
+ { CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_op_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_op_clk_freq_mhz" },
+ { CCS_R_CLOCK_TREE_PLL_CAPABILITY, 1, 0, "clock_tree_pll_capability" },
+ { CCS_R_CLOCK_CAPA_TYPE_CAPABILITY, 1, 0, "clock_capa_type_capability" },
+ { CCS_R_MIN_EVEN_INC, 2, 0, "min_even_inc" },
+ { CCS_R_MIN_ODD_INC, 2, 0, "min_odd_inc" },
+ { CCS_R_MAX_EVEN_INC, 2, 0, "max_even_inc" },
+ { CCS_R_MAX_ODD_INC, 2, 0, "max_odd_inc" },
+ { CCS_R_AUX_SUBSAMP_CAPABILITY, 1, 0, "aux_subsamp_capability" },
+ { CCS_R_AUX_SUBSAMP_MONO_CAPABILITY, 1, 0, "aux_subsamp_mono_capability" },
+ { CCS_R_MONOCHROME_CAPABILITY, 1, 0, "monochrome_capability" },
+ { CCS_R_PIXEL_READOUT_CAPABILITY, 1, 0, "pixel_readout_capability" },
+ { CCS_R_MIN_EVEN_INC_MONO, 2, 0, "min_even_inc_mono" },
+ { CCS_R_MAX_EVEN_INC_MONO, 2, 0, "max_even_inc_mono" },
+ { CCS_R_MIN_ODD_INC_MONO, 2, 0, "min_odd_inc_mono" },
+ { CCS_R_MAX_ODD_INC_MONO, 2, 0, "max_odd_inc_mono" },
+ { CCS_R_MIN_EVEN_INC_BC2, 2, 0, "min_even_inc_bc2" },
+ { CCS_R_MAX_EVEN_INC_BC2, 2, 0, "max_even_inc_bc2" },
+ { CCS_R_MIN_ODD_INC_BC2, 2, 0, "min_odd_inc_bc2" },
+ { CCS_R_MAX_ODD_INC_BC2, 2, 0, "max_odd_inc_bc2" },
+ { CCS_R_MIN_EVEN_INC_MONO_BC2, 2, 0, "min_even_inc_mono_bc2" },
+ { CCS_R_MAX_EVEN_INC_MONO_BC2, 2, 0, "max_even_inc_mono_bc2" },
+ { CCS_R_MIN_ODD_INC_MONO_BC2, 2, 0, "min_odd_inc_mono_bc2" },
+ { CCS_R_MAX_ODD_INC_MONO_BC2, 2, 0, "max_odd_inc_mono_bc2" },
+ { CCS_R_SCALING_CAPABILITY, 2, 0, "scaling_capability" },
+ { CCS_R_SCALER_M_MIN, 2, 0, "scaler_m_min" },
+ { CCS_R_SCALER_M_MAX, 2, 0, "scaler_m_max" },
+ { CCS_R_SCALER_N_MIN, 2, 0, "scaler_n_min" },
+ { CCS_R_SCALER_N_MAX, 2, 0, "scaler_n_max" },
+ { CCS_R_DIGITAL_CROP_CAPABILITY, 1, 0, "digital_crop_capability" },
+ { CCS_R_HDR_CAPABILITY_1, 1, 0, "hdr_capability_1" },
+ { CCS_R_MIN_HDR_BIT_DEPTH, 1, 0, "min_hdr_bit_depth" },
+ { CCS_R_HDR_RESOLUTION_SUB_TYPES, 1, 0, "hdr_resolution_sub_types" },
+ { CCS_R_HDR_RESOLUTION_SUB_TYPE(0), 2, 0, "hdr_resolution_sub_type" },
+ { CCS_R_HDR_CAPABILITY_2, 1, 0, "hdr_capability_2" },
+ { CCS_R_MAX_HDR_BIT_DEPTH, 1, 0, "max_hdr_bit_depth" },
+ { CCS_R_USL_SUPPORT_CAPABILITY, 1, 0, "usl_support_capability" },
+ { CCS_R_USL_CLOCK_MODE_D_CAPABILITY, 1, 0, "usl_clock_mode_d_capability" },
+ { CCS_R_MIN_OP_SYS_CLK_DIV_REV, 1, 0, "min_op_sys_clk_div_rev" },
+ { CCS_R_MAX_OP_SYS_CLK_DIV_REV, 1, 0, "max_op_sys_clk_div_rev" },
+ { CCS_R_MIN_OP_PIX_CLK_DIV_REV, 1, 0, "min_op_pix_clk_div_rev" },
+ { CCS_R_MAX_OP_PIX_CLK_DIV_REV, 1, 0, "max_op_pix_clk_div_rev" },
+ { CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "min_op_sys_clk_freq_rev_mhz" },
+ { CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "max_op_sys_clk_freq_rev_mhz" },
+ { CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "min_op_pix_clk_freq_rev_mhz" },
+ { CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "max_op_pix_clk_freq_rev_mhz" },
+ { CCS_R_MAX_BITRATE_REV_D_MODE_MBPS, 4, 0, "max_bitrate_rev_d_mode_mbps" },
+ { CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS, 4, 0, "max_symrate_rev_c_mode_msps" },
+ { CCS_R_COMPRESSION_CAPABILITY, 1, 0, "compression_capability" },
+ { CCS_R_TEST_MODE_CAPABILITY, 2, 0, "test_mode_capability" },
+ { CCS_R_PN9_DATA_FORMAT1, 1, 0, "pn9_data_format1" },
+ { CCS_R_PN9_DATA_FORMAT2, 1, 0, "pn9_data_format2" },
+ { CCS_R_PN9_DATA_FORMAT3, 1, 0, "pn9_data_format3" },
+ { CCS_R_PN9_DATA_FORMAT4, 1, 0, "pn9_data_format4" },
+ { CCS_R_PN9_MISC_CAPABILITY, 1, 0, "pn9_misc_capability" },
+ { CCS_R_TEST_PATTERN_CAPABILITY, 1, 0, "test_pattern_capability" },
+ { CCS_R_PATTERN_SIZE_DIV_M1, 1, 0, "pattern_size_div_m1" },
+ { CCS_R_FIFO_SUPPORT_CAPABILITY, 1, 0, "fifo_support_capability" },
+ { CCS_R_PHY_CTRL_CAPABILITY, 1, 0, "phy_ctrl_capability" },
+ { CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_dphy_lane_mode_capability" },
+ { CCS_R_CSI_SIGNALING_MODE_CAPABILITY, 1, 0, "csi_signaling_mode_capability" },
+ { CCS_R_FAST_STANDBY_CAPABILITY, 1, 0, "fast_standby_capability" },
+ { CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY, 1, 0, "csi_address_control_capability" },
+ { CCS_R_DATA_TYPE_CAPABILITY, 1, 0, "data_type_capability" },
+ { CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_cphy_lane_mode_capability" },
+ { CCS_R_EMB_DATA_CAPABILITY, 1, 0, "emb_data_capability" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_d_mode_mbps 0" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_d_mode_mbps 4" },
+ { CCS_R_TEMP_SENSOR_CAPABILITY, 1, 0, "temp_sensor_capability" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_c_mode_mbps 0" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_c_mode_mbps 4" },
+ { CCS_R_DPHY_EQUALIZATION_CAPABILITY, 1, 0, "dphy_equalization_capability" },
+ { CCS_R_CPHY_EQUALIZATION_CAPABILITY, 1, 0, "cphy_equalization_capability" },
+ { CCS_R_DPHY_PREAMBLE_CAPABILITY, 1, 0, "dphy_preamble_capability" },
+ { CCS_R_DPHY_SSC_CAPABILITY, 1, 0, "dphy_ssc_capability" },
+ { CCS_R_CPHY_CALIBRATION_CAPABILITY, 1, 0, "cphy_calibration_capability" },
+ { CCS_R_DPHY_CALIBRATION_CAPABILITY, 1, 0, "dphy_calibration_capability" },
+ { CCS_R_PHY_CTRL_CAPABILITY_2, 1, 0, "phy_ctrl_capability_2" },
+ { CCS_R_LRTE_CPHY_CAPABILITY, 1, 0, "lrte_cphy_capability" },
+ { CCS_R_LRTE_DPHY_CAPABILITY, 1, 0, "lrte_dphy_capability" },
+ { CCS_R_ALPS_CAPABILITY_DPHY, 1, 0, "alps_capability_dphy" },
+ { CCS_R_ALPS_CAPABILITY_CPHY, 1, 0, "alps_capability_cphy" },
+ { CCS_R_SCRAMBLING_CAPABILITY, 1, 0, "scrambling_capability" },
+ { CCS_R_DPHY_MANUAL_CONSTANT, 1, 0, "dphy_manual_constant" },
+ { CCS_R_CPHY_MANUAL_CONSTANT, 1, 0, "cphy_manual_constant" },
+ { CCS_R_CSI2_INTERFACE_CAPABILITY_MISC, 1, 0, "CSI2_interface_capability_misc" },
+ { CCS_R_PHY_CTRL_CAPABILITY_3, 1, 0, "PHY_ctrl_capability_3" },
+ { CCS_R_DPHY_SF, 1, 0, "dphy_sf" },
+ { CCS_R_CPHY_SF, 1, 0, "cphy_sf" },
+ { CCS_R_DPHY_LIMITS_1, 1, 0, "dphy_limits_1" },
+ { CCS_R_DPHY_LIMITS_2, 1, 0, "dphy_limits_2" },
+ { CCS_R_DPHY_LIMITS_3, 1, 0, "dphy_limits_3" },
+ { CCS_R_DPHY_LIMITS_4, 1, 0, "dphy_limits_4" },
+ { CCS_R_DPHY_LIMITS_5, 1, 0, "dphy_limits_5" },
+ { CCS_R_DPHY_LIMITS_6, 1, 0, "dphy_limits_6" },
+ { CCS_R_CPHY_LIMITS_1, 1, 0, "cphy_limits_1" },
+ { CCS_R_CPHY_LIMITS_2, 1, 0, "cphy_limits_2" },
+ { CCS_R_CPHY_LIMITS_3, 1, 0, "cphy_limits_3" },
+ { CCS_R_MIN_FRAME_LENGTH_LINES_BIN, 2, 0, "min_frame_length_lines_bin" },
+ { CCS_R_MAX_FRAME_LENGTH_LINES_BIN, 2, 0, "max_frame_length_lines_bin" },
+ { CCS_R_MIN_LINE_LENGTH_PCK_BIN, 2, 0, "min_line_length_pck_bin" },
+ { CCS_R_MAX_LINE_LENGTH_PCK_BIN, 2, 0, "max_line_length_pck_bin" },
+ { CCS_R_MIN_LINE_BLANKING_PCK_BIN, 2, 0, "min_line_blanking_pck_bin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MIN_BIN, 2, 0, "fine_integration_time_min_bin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, 2, 0, "fine_integration_time_max_margin_bin" },
+ { CCS_R_BINNING_CAPABILITY, 1, 0, "binning_capability" },
+ { CCS_R_BINNING_WEIGHTING_CAPABILITY, 1, 0, "binning_weighting_capability" },
+ { CCS_R_BINNING_SUB_TYPES, 1, 0, "binning_sub_types" },
+ { CCS_R_BINNING_SUB_TYPE(0), 64, 0, "binning_sub_type" },
+ { CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY, 1, 0, "binning_weighting_mono_capability" },
+ { CCS_R_BINNING_SUB_TYPES_MONO, 1, 0, "binning_sub_types_mono" },
+ { CCS_R_BINNING_SUB_TYPE_MONO(0), 64, 0, "binning_sub_type_mono" },
+ { CCS_R_DATA_TRANSFER_IF_CAPABILITY, 1, 0, "data_transfer_if_capability" },
+ { CCS_R_SHADING_CORRECTION_CAPABILITY, 1, 0, "shading_correction_capability" },
+ { CCS_R_GREEN_IMBALANCE_CAPABILITY, 1, 0, "green_imbalance_capability" },
+ { CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY, 1, 0, "module_specific_correction_capability" },
+ { CCS_R_DEFECT_CORRECTION_CAPABILITY, 2, 0, "defect_correction_capability" },
+ { CCS_R_DEFECT_CORRECTION_CAPABILITY_2, 2, 0, "defect_correction_capability_2" },
+ { CCS_R_NF_CAPABILITY, 1, 0, "nf_capability" },
+ { CCS_R_OB_READOUT_CAPABILITY, 1, 0, "ob_readout_capability" },
+ { CCS_R_COLOR_FEEDBACK_CAPABILITY, 1, 0, "color_feedback_capability" },
+ { CCS_R_CFA_PATTERN_CAPABILITY, 1, 0, "CFA_pattern_capability" },
+ { CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY, 1, 0, "CFA_pattern_conversion_capability" },
+ { CCS_R_FLASH_MODE_CAPABILITY, 1, 0, "flash_mode_capability" },
+ { CCS_R_SA_STROBE_MODE_CAPABILITY, 1, 0, "sa_strobe_mode_capability" },
+ { CCS_R_RESET_MAX_DELAY, 1, 0, "reset_max_delay" },
+ { CCS_R_RESET_MIN_TIME, 1, 0, "reset_min_time" },
+ { CCS_R_PDAF_CAPABILITY_1, 1, 0, "pdaf_capability_1" },
+ { CCS_R_PDAF_CAPABILITY_2, 1, 0, "pdaf_capability_2" },
+ { CCS_R_BRACKETING_LUT_CAPABILITY_1, 1, 0, "bracketing_lut_capability_1" },
+ { CCS_R_BRACKETING_LUT_CAPABILITY_2, 1, 0, "bracketing_lut_capability_2" },
+ { CCS_R_BRACKETING_LUT_SIZE, 1, 0, "bracketing_lut_size" },
+ { 0 } /* Guardian */
+};
diff --git a/drivers/media/i2c/ccs/ccs-limits.h b/drivers/media/i2c/ccs/ccs-limits.h
new file mode 100644
index 000000000000..1efa43c23a2e
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-limits.h
@@ -0,0 +1,259 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/* Copyright (C) 2019--2020 Intel Corporation */
+
+#ifndef __CCS_LIMITS_H__
+#define __CCS_LIMITS_H__
+
+#include <linux/bits.h>
+#include <linux/types.h>
+
+struct ccs_limit {
+ u32 reg;
+ u16 size;
+ u16 flags;
+ const char *name;
+};
+
+#define CCS_L_FL_SAME_REG BIT(0)
+
+extern const struct ccs_limit ccs_limits[];
+
+#define CCS_L_FRAME_FORMAT_MODEL_TYPE 0
+#define CCS_L_FRAME_FORMAT_MODEL_SUBTYPE 1
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR 2
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4 3
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4_OFFSET(n) ((n) * 4)
+#define CCS_L_ANALOG_GAIN_CAPABILITY 4
+#define CCS_L_ANALOG_GAIN_CODE_MIN 5
+#define CCS_L_ANALOG_GAIN_CODE_MAX 6
+#define CCS_L_ANALOG_GAIN_CODE_STEP 7
+#define CCS_L_ANALOG_GAIN_TYPE 8
+#define CCS_L_ANALOG_GAIN_M0 9
+#define CCS_L_ANALOG_GAIN_C0 10
+#define CCS_L_ANALOG_GAIN_M1 11
+#define CCS_L_ANALOG_GAIN_C1 12
+#define CCS_L_ANALOG_LINEAR_GAIN_MIN 13
+#define CCS_L_ANALOG_LINEAR_GAIN_MAX 14
+#define CCS_L_ANALOG_LINEAR_GAIN_STEP_SIZE 15
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MIN 16
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MAX 17
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE 18
+#define CCS_L_DATA_FORMAT_MODEL_TYPE 19
+#define CCS_L_DATA_FORMAT_MODEL_SUBTYPE 20
+#define CCS_L_DATA_FORMAT_DESCRIPTOR 21
+#define CCS_L_DATA_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
+#define CCS_L_INTEGRATION_TIME_CAPABILITY 22
+#define CCS_L_COARSE_INTEGRATION_TIME_MIN 23
+#define CCS_L_COARSE_INTEGRATION_TIME_MAX_MARGIN 24
+#define CCS_L_FINE_INTEGRATION_TIME_MIN 25
+#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN 26
+#define CCS_L_DIGITAL_GAIN_CAPABILITY 27
+#define CCS_L_DIGITAL_GAIN_MIN 28
+#define CCS_L_DIGITAL_GAIN_MAX 29
+#define CCS_L_DIGITAL_GAIN_STEP_SIZE 30
+#define CCS_L_PEDESTAL_CAPABILITY 31
+#define CCS_L_ADC_CAPABILITY 32
+#define CCS_L_ADC_BIT_DEPTH_CAPABILITY 33
+#define CCS_L_MIN_EXT_CLK_FREQ_MHZ 34
+#define CCS_L_MAX_EXT_CLK_FREQ_MHZ 35
+#define CCS_L_MIN_PRE_PLL_CLK_DIV 36
+#define CCS_L_MAX_PRE_PLL_CLK_DIV 37
+#define CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ 38
+#define CCS_L_MAX_PLL_IP_CLK_FREQ_MHZ 39
+#define CCS_L_MIN_PLL_MULTIPLIER 40
+#define CCS_L_MAX_PLL_MULTIPLIER 41
+#define CCS_L_MIN_PLL_OP_CLK_FREQ_MHZ 42
+#define CCS_L_MAX_PLL_OP_CLK_FREQ_MHZ 43
+#define CCS_L_MIN_VT_SYS_CLK_DIV 44
+#define CCS_L_MAX_VT_SYS_CLK_DIV 45
+#define CCS_L_MIN_VT_SYS_CLK_FREQ_MHZ 46
+#define CCS_L_MAX_VT_SYS_CLK_FREQ_MHZ 47
+#define CCS_L_MIN_VT_PIX_CLK_FREQ_MHZ 48
+#define CCS_L_MAX_VT_PIX_CLK_FREQ_MHZ 49
+#define CCS_L_MIN_VT_PIX_CLK_DIV 50
+#define CCS_L_MAX_VT_PIX_CLK_DIV 51
+#define CCS_L_CLOCK_CALCULATION 52
+#define CCS_L_NUM_OF_VT_LANES 53
+#define CCS_L_NUM_OF_OP_LANES 54
+#define CCS_L_OP_BITS_PER_LANE 55
+#define CCS_L_MIN_FRAME_LENGTH_LINES 56
+#define CCS_L_MAX_FRAME_LENGTH_LINES 57
+#define CCS_L_MIN_LINE_LENGTH_PCK 58
+#define CCS_L_MAX_LINE_LENGTH_PCK 59
+#define CCS_L_MIN_LINE_BLANKING_PCK 60
+#define CCS_L_MIN_FRAME_BLANKING_LINES 61
+#define CCS_L_MIN_LINE_LENGTH_PCK_STEP_SIZE 62
+#define CCS_L_TIMING_MODE_CAPABILITY 63
+#define CCS_L_FRAME_MARGIN_MAX_VALUE 64
+#define CCS_L_FRAME_MARGIN_MIN_VALUE 65
+#define CCS_L_GAIN_DELAY_TYPE 66
+#define CCS_L_MIN_OP_SYS_CLK_DIV 67
+#define CCS_L_MAX_OP_SYS_CLK_DIV 68
+#define CCS_L_MIN_OP_SYS_CLK_FREQ_MHZ 69
+#define CCS_L_MAX_OP_SYS_CLK_FREQ_MHZ 70
+#define CCS_L_MIN_OP_PIX_CLK_DIV 71
+#define CCS_L_MAX_OP_PIX_CLK_DIV 72
+#define CCS_L_MIN_OP_PIX_CLK_FREQ_MHZ 73
+#define CCS_L_MAX_OP_PIX_CLK_FREQ_MHZ 74
+#define CCS_L_X_ADDR_MIN 75
+#define CCS_L_Y_ADDR_MIN 76
+#define CCS_L_X_ADDR_MAX 77
+#define CCS_L_Y_ADDR_MAX 78
+#define CCS_L_MIN_X_OUTPUT_SIZE 79
+#define CCS_L_MIN_Y_OUTPUT_SIZE 80
+#define CCS_L_MAX_X_OUTPUT_SIZE 81
+#define CCS_L_MAX_Y_OUTPUT_SIZE 82
+#define CCS_L_X_ADDR_START_DIV_CONSTANT 83
+#define CCS_L_Y_ADDR_START_DIV_CONSTANT 84
+#define CCS_L_X_ADDR_END_DIV_CONSTANT 85
+#define CCS_L_Y_ADDR_END_DIV_CONSTANT 86
+#define CCS_L_X_SIZE_DIV 87
+#define CCS_L_Y_SIZE_DIV 88
+#define CCS_L_X_OUTPUT_DIV 89
+#define CCS_L_Y_OUTPUT_DIV 90
+#define CCS_L_NON_FLEXIBLE_RESOLUTION_SUPPORT 91
+#define CCS_L_MIN_OP_PRE_PLL_CLK_DIV 92
+#define CCS_L_MAX_OP_PRE_PLL_CLK_DIV 93
+#define CCS_L_MIN_OP_PLL_IP_CLK_FREQ_MHZ 94
+#define CCS_L_MAX_OP_PLL_IP_CLK_FREQ_MHZ 95
+#define CCS_L_MIN_OP_PLL_MULTIPLIER 96
+#define CCS_L_MAX_OP_PLL_MULTIPLIER 97
+#define CCS_L_MIN_OP_PLL_OP_CLK_FREQ_MHZ 98
+#define CCS_L_MAX_OP_PLL_OP_CLK_FREQ_MHZ 99
+#define CCS_L_CLOCK_TREE_PLL_CAPABILITY 100
+#define CCS_L_CLOCK_CAPA_TYPE_CAPABILITY 101
+#define CCS_L_MIN_EVEN_INC 102
+#define CCS_L_MIN_ODD_INC 103
+#define CCS_L_MAX_EVEN_INC 104
+#define CCS_L_MAX_ODD_INC 105
+#define CCS_L_AUX_SUBSAMP_CAPABILITY 106
+#define CCS_L_AUX_SUBSAMP_MONO_CAPABILITY 107
+#define CCS_L_MONOCHROME_CAPABILITY 108
+#define CCS_L_PIXEL_READOUT_CAPABILITY 109
+#define CCS_L_MIN_EVEN_INC_MONO 110
+#define CCS_L_MAX_EVEN_INC_MONO 111
+#define CCS_L_MIN_ODD_INC_MONO 112
+#define CCS_L_MAX_ODD_INC_MONO 113
+#define CCS_L_MIN_EVEN_INC_BC2 114
+#define CCS_L_MAX_EVEN_INC_BC2 115
+#define CCS_L_MIN_ODD_INC_BC2 116
+#define CCS_L_MAX_ODD_INC_BC2 117
+#define CCS_L_MIN_EVEN_INC_MONO_BC2 118
+#define CCS_L_MAX_EVEN_INC_MONO_BC2 119
+#define CCS_L_MIN_ODD_INC_MONO_BC2 120
+#define CCS_L_MAX_ODD_INC_MONO_BC2 121
+#define CCS_L_SCALING_CAPABILITY 122
+#define CCS_L_SCALER_M_MIN 123
+#define CCS_L_SCALER_M_MAX 124
+#define CCS_L_SCALER_N_MIN 125
+#define CCS_L_SCALER_N_MAX 126
+#define CCS_L_DIGITAL_CROP_CAPABILITY 127
+#define CCS_L_HDR_CAPABILITY_1 128
+#define CCS_L_MIN_HDR_BIT_DEPTH 129
+#define CCS_L_HDR_RESOLUTION_SUB_TYPES 130
+#define CCS_L_HDR_RESOLUTION_SUB_TYPE 131
+#define CCS_L_HDR_RESOLUTION_SUB_TYPE_OFFSET(n) (n)
+#define CCS_L_HDR_CAPABILITY_2 132
+#define CCS_L_MAX_HDR_BIT_DEPTH 133
+#define CCS_L_USL_SUPPORT_CAPABILITY 134
+#define CCS_L_USL_CLOCK_MODE_D_CAPABILITY 135
+#define CCS_L_MIN_OP_SYS_CLK_DIV_REV 136
+#define CCS_L_MAX_OP_SYS_CLK_DIV_REV 137
+#define CCS_L_MIN_OP_PIX_CLK_DIV_REV 138
+#define CCS_L_MAX_OP_PIX_CLK_DIV_REV 139
+#define CCS_L_MIN_OP_SYS_CLK_FREQ_REV_MHZ 140
+#define CCS_L_MAX_OP_SYS_CLK_FREQ_REV_MHZ 141
+#define CCS_L_MIN_OP_PIX_CLK_FREQ_REV_MHZ 142
+#define CCS_L_MAX_OP_PIX_CLK_FREQ_REV_MHZ 143
+#define CCS_L_MAX_BITRATE_REV_D_MODE_MBPS 144
+#define CCS_L_MAX_SYMRATE_REV_C_MODE_MSPS 145
+#define CCS_L_COMPRESSION_CAPABILITY 146
+#define CCS_L_TEST_MODE_CAPABILITY 147
+#define CCS_L_PN9_DATA_FORMAT1 148
+#define CCS_L_PN9_DATA_FORMAT2 149
+#define CCS_L_PN9_DATA_FORMAT3 150
+#define CCS_L_PN9_DATA_FORMAT4 151
+#define CCS_L_PN9_MISC_CAPABILITY 152
+#define CCS_L_TEST_PATTERN_CAPABILITY 153
+#define CCS_L_PATTERN_SIZE_DIV_M1 154
+#define CCS_L_FIFO_SUPPORT_CAPABILITY 155
+#define CCS_L_PHY_CTRL_CAPABILITY 156
+#define CCS_L_CSI_DPHY_LANE_MODE_CAPABILITY 157
+#define CCS_L_CSI_SIGNALING_MODE_CAPABILITY 158
+#define CCS_L_FAST_STANDBY_CAPABILITY 159
+#define CCS_L_CSI_ADDRESS_CONTROL_CAPABILITY 160
+#define CCS_L_DATA_TYPE_CAPABILITY 161
+#define CCS_L_CSI_CPHY_LANE_MODE_CAPABILITY 162
+#define CCS_L_EMB_DATA_CAPABILITY 163
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS 164
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_OFFSET(n) ((n) * 4)
+#define CCS_L_TEMP_SENSOR_CAPABILITY 165
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS 166
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_OFFSET(n) ((n) * 4)
+#define CCS_L_DPHY_EQUALIZATION_CAPABILITY 167
+#define CCS_L_CPHY_EQUALIZATION_CAPABILITY 168
+#define CCS_L_DPHY_PREAMBLE_CAPABILITY 169
+#define CCS_L_DPHY_SSC_CAPABILITY 170
+#define CCS_L_CPHY_CALIBRATION_CAPABILITY 171
+#define CCS_L_DPHY_CALIBRATION_CAPABILITY 172
+#define CCS_L_PHY_CTRL_CAPABILITY_2 173
+#define CCS_L_LRTE_CPHY_CAPABILITY 174
+#define CCS_L_LRTE_DPHY_CAPABILITY 175
+#define CCS_L_ALPS_CAPABILITY_DPHY 176
+#define CCS_L_ALPS_CAPABILITY_CPHY 177
+#define CCS_L_SCRAMBLING_CAPABILITY 178
+#define CCS_L_DPHY_MANUAL_CONSTANT 179
+#define CCS_L_CPHY_MANUAL_CONSTANT 180
+#define CCS_L_CSI2_INTERFACE_CAPABILITY_MISC 181
+#define CCS_L_PHY_CTRL_CAPABILITY_3 182
+#define CCS_L_DPHY_SF 183
+#define CCS_L_CPHY_SF 184
+#define CCS_L_DPHY_LIMITS_1 185
+#define CCS_L_DPHY_LIMITS_2 186
+#define CCS_L_DPHY_LIMITS_3 187
+#define CCS_L_DPHY_LIMITS_4 188
+#define CCS_L_DPHY_LIMITS_5 189
+#define CCS_L_DPHY_LIMITS_6 190
+#define CCS_L_CPHY_LIMITS_1 191
+#define CCS_L_CPHY_LIMITS_2 192
+#define CCS_L_CPHY_LIMITS_3 193
+#define CCS_L_MIN_FRAME_LENGTH_LINES_BIN 194
+#define CCS_L_MAX_FRAME_LENGTH_LINES_BIN 195
+#define CCS_L_MIN_LINE_LENGTH_PCK_BIN 196
+#define CCS_L_MAX_LINE_LENGTH_PCK_BIN 197
+#define CCS_L_MIN_LINE_BLANKING_PCK_BIN 198
+#define CCS_L_FINE_INTEGRATION_TIME_MIN_BIN 199
+#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 200
+#define CCS_L_BINNING_CAPABILITY 201
+#define CCS_L_BINNING_WEIGHTING_CAPABILITY 202
+#define CCS_L_BINNING_SUB_TYPES 203
+#define CCS_L_BINNING_SUB_TYPE 204
+#define CCS_L_BINNING_SUB_TYPE_OFFSET(n) (n)
+#define CCS_L_BINNING_WEIGHTING_MONO_CAPABILITY 205
+#define CCS_L_BINNING_SUB_TYPES_MONO 206
+#define CCS_L_BINNING_SUB_TYPE_MONO 207
+#define CCS_L_BINNING_SUB_TYPE_MONO_OFFSET(n) (n)
+#define CCS_L_DATA_TRANSFER_IF_CAPABILITY 208
+#define CCS_L_SHADING_CORRECTION_CAPABILITY 209
+#define CCS_L_GREEN_IMBALANCE_CAPABILITY 210
+#define CCS_L_MODULE_SPECIFIC_CORRECTION_CAPABILITY 211
+#define CCS_L_DEFECT_CORRECTION_CAPABILITY 212
+#define CCS_L_DEFECT_CORRECTION_CAPABILITY_2 213
+#define CCS_L_NF_CAPABILITY 214
+#define CCS_L_OB_READOUT_CAPABILITY 215
+#define CCS_L_COLOR_FEEDBACK_CAPABILITY 216
+#define CCS_L_CFA_PATTERN_CAPABILITY 217
+#define CCS_L_CFA_PATTERN_CONVERSION_CAPABILITY 218
+#define CCS_L_FLASH_MODE_CAPABILITY 219
+#define CCS_L_SA_STROBE_MODE_CAPABILITY 220
+#define CCS_L_RESET_MAX_DELAY 221
+#define CCS_L_RESET_MIN_TIME 222
+#define CCS_L_PDAF_CAPABILITY_1 223
+#define CCS_L_PDAF_CAPABILITY_2 224
+#define CCS_L_BRACKETING_LUT_CAPABILITY_1 225
+#define CCS_L_BRACKETING_LUT_CAPABILITY_2 226
+#define CCS_L_BRACKETING_LUT_SIZE 227
+#define CCS_L_LAST 228
+
+#endif /* __CCS_LIMITS_H__ */
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
index ab96d6067fc3..e3d4c7a275bc 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.c
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -1,30 +1,27 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp/smiapp-quirk.c
+ * drivers/media/i2c/ccs/ccs-quirk.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
#include <linux/delay.h>
-#include "smiapp.h"
+#include "ccs.h"
+#include "ccs-limits.h"
-static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
-{
- return smiapp_write(sensor, SMIAPP_REG_MK_U8(reg), val);
-}
-
-static int smiapp_write_8s(struct smiapp_sensor *sensor,
- const struct smiapp_reg_8 *regs, int len)
+static int ccs_write_addr_8s(struct ccs_sensor *sensor,
+ const struct ccs_reg_8 *regs, int len)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
for (; len > 0; len--, regs++) {
- rval = smiapp_write_8(sensor, regs->reg, regs->val);
+ rval = ccs_write_addr(sensor, regs->reg, regs->val);
if (rval < 0) {
dev_err(&client->dev,
"error %d writing reg 0x%4.4x, val 0x%2.2x",
@@ -36,34 +33,22 @@ static int smiapp_write_8s(struct smiapp_sensor *sensor,
return 0;
}
-void smiapp_replace_limit(struct smiapp_sensor *sensor,
- u32 limit, u32 val)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-
- dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" = %d, 0x%x\n",
- smiapp_reg_limits[limit].addr,
- smiapp_reg_limits[limit].what, val, val);
- sensor->limits[limit] = val;
-}
-
-static int jt8ew9_limits(struct smiapp_sensor *sensor)
+static int jt8ew9_limits(struct ccs_sensor *sensor)
{
- if (sensor->minfo.revision_number_major < 0x03)
+ if (sensor->minfo.revision_number < 0x0300)
sensor->frame_skip = 1;
/* Below 24 gain doesn't have effect at all, */
/* but ~59 is needed for full dynamic range */
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN, 59);
- smiapp_replace_limit(
- sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX, 6000);
+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
return 0;
}
-static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
+static int jt8ew9_post_poweron(struct ccs_sensor *sensor)
{
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
@@ -96,18 +81,18 @@ static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
};
- return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
-const struct smiapp_quirk smiapp_jt8ew9_quirk = {
+const struct ccs_quirk smiapp_jt8ew9_quirk = {
.limits = jt8ew9_limits,
.post_poweron = jt8ew9_post_poweron,
};
-static int imx125es_post_poweron(struct smiapp_sensor *sensor)
+static int imx125es_post_poweron(struct ccs_sensor *sensor)
{
/* Taken from v02. No idea what the other two are. */
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
/*
* 0x3302: clk during frame blanking:
* 0x00 - HS mode, 0x01 - LP11
@@ -117,27 +102,26 @@ static int imx125es_post_poweron(struct smiapp_sensor *sensor)
{ 0x3b08, 0x8c },
};
- return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
}
-const struct smiapp_quirk smiapp_imx125es_quirk = {
+const struct ccs_quirk smiapp_imx125es_quirk = {
.post_poweron = imx125es_post_poweron,
};
-static int jt8ev1_limits(struct smiapp_sensor *sensor)
+static int jt8ev1_limits(struct ccs_sensor *sensor)
{
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_X_ADDR_MAX, 4271);
- smiapp_replace_limit(sensor,
- SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN, 184);
+ ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
+ ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
return 0;
}
-static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
+static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
int rval;
- static const struct smiapp_reg_8 regs[] = {
+ static const struct ccs_reg_8 regs[] = {
{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */
{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */
@@ -158,38 +142,38 @@ static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
{ 0x33cf, 0xec }, /* For Black sun */
{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */
};
- static const struct smiapp_reg_8 regs_96[] = {
+ static const struct ccs_reg_8 regs_96[] = {
{ 0x30ae, 0x00 }, /* For control of ADC clock */
{ 0x30af, 0xd0 },
{ 0x30b0, 0x01 },
};
- rval = smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
+ rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
if (rval < 0)
return rval;
- switch (sensor->hwcfg->ext_clk) {
+ switch (sensor->hwcfg.ext_clk) {
case 9600000:
- return smiapp_write_8s(sensor, regs_96,
+ return ccs_write_addr_8s(sensor, regs_96,
ARRAY_SIZE(regs_96));
default:
dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
- sensor->hwcfg->ext_clk);
+ sensor->hwcfg.ext_clk);
return 0;
}
}
-static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
+static int jt8ev1_pre_streamon(struct ccs_sensor *sensor)
{
- return smiapp_write_8(sensor, 0x3328, 0x00);
+ return ccs_write_addr(sensor, 0x3328, 0x00);
}
-static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
+static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
{
int rval;
/* Workaround: allows fast standby to work properly */
- rval = smiapp_write_8(sensor, 0x3205, 0x04);
+ rval = ccs_write_addr(sensor, 0x3205, 0x04);
if (rval < 0)
return rval;
@@ -197,21 +181,24 @@ static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
usleep_range(2000, 2050);
/* Restore it */
- rval = smiapp_write_8(sensor, 0x3205, 0x00);
+ rval = ccs_write_addr(sensor, 0x3205, 0x00);
if (rval < 0)
return rval;
- return smiapp_write_8(sensor, 0x3328, 0x80);
+ return ccs_write_addr(sensor, 0x3328, 0x80);
}
-static int jt8ev1_init(struct smiapp_sensor *sensor)
+static int jt8ev1_init(struct ccs_sensor *sensor)
{
- sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
+ sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL |
+ CCS_PLL_FLAG_LINK_DECOUPLED;
+ sensor->pll.vt_lanes = 1;
+ sensor->pll.op_lanes = sensor->pll.csi2.lanes;
return 0;
}
-const struct smiapp_quirk smiapp_jt8ev1_quirk = {
+const struct ccs_quirk smiapp_jt8ev1_quirk = {
.limits = jt8ev1_limits,
.post_poweron = jt8ev1_post_poweron,
.pre_streamon = jt8ev1_pre_streamon,
@@ -219,13 +206,13 @@ const struct smiapp_quirk smiapp_jt8ev1_quirk = {
.init = jt8ev1_init,
};
-static int tcm8500md_limits(struct smiapp_sensor *sensor)
+static int tcm8500md_limits(struct ccs_sensor *sensor)
{
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ, 2700000);
+ ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
return 0;
}
-const struct smiapp_quirk smiapp_tcm8500md_quirk = {
+const struct ccs_quirk smiapp_tcm8500md_quirk = {
.limits = tcm8500md_limits,
};
diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.h b/drivers/media/i2c/ccs/ccs-quirk.h
index 17505be60c1d..6b4ec4beaba0 100644
--- a/drivers/media/i2c/smiapp/smiapp-quirk.h
+++ b/drivers/media/i2c/ccs/ccs-quirk.h
@@ -1,20 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp/smiapp-quirk.h
+ * drivers/media/i2c/ccs/ccs-quirk.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
-#ifndef __SMIAPP_QUIRK__
-#define __SMIAPP_QUIRK__
+#ifndef __CCS_QUIRK__
+#define __CCS_QUIRK__
-struct smiapp_sensor;
+struct ccs_sensor;
/**
- * struct smiapp_quirk - quirks for sensors that deviate from SMIA++ standard
+ * struct ccs_quirk - quirks for sensors that deviate from SMIA++ standard
*
* @limits: Replace sensor->limits with values which can't be read from
* sensor registers. Called the first time the sensor is powered up.
@@ -36,46 +37,43 @@ struct smiapp_sensor;
* access may be done by the caller (default read
* value is zero), else negative error code on error
*/
-struct smiapp_quirk {
- int (*limits)(struct smiapp_sensor *sensor);
- int (*post_poweron)(struct smiapp_sensor *sensor);
- int (*pre_streamon)(struct smiapp_sensor *sensor);
- int (*post_streamoff)(struct smiapp_sensor *sensor);
- unsigned long (*pll_flags)(struct smiapp_sensor *sensor);
- int (*init)(struct smiapp_sensor *sensor);
- int (*reg_access)(struct smiapp_sensor *sensor, bool write, u32 *reg,
+struct ccs_quirk {
+ int (*limits)(struct ccs_sensor *sensor);
+ int (*post_poweron)(struct ccs_sensor *sensor);
+ int (*pre_streamon)(struct ccs_sensor *sensor);
+ int (*post_streamoff)(struct ccs_sensor *sensor);
+ unsigned long (*pll_flags)(struct ccs_sensor *sensor);
+ int (*init)(struct ccs_sensor *sensor);
+ int (*reg_access)(struct ccs_sensor *sensor, bool write, u32 *reg,
u32 *val);
unsigned long flags;
};
-#define SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)
+#define CCS_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)
-struct smiapp_reg_8 {
+struct ccs_reg_8 {
u16 reg;
u8 val;
};
-void smiapp_replace_limit(struct smiapp_sensor *sensor,
- u32 limit, u32 val);
-
-#define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \
+#define CCS_MK_QUIRK_REG_8(_reg, _val) \
{ \
.reg = (u16)_reg, \
.val = _val, \
}
-#define smiapp_call_quirk(sensor, _quirk, ...) \
+#define ccs_call_quirk(sensor, _quirk, ...) \
((sensor)->minfo.quirk && \
(sensor)->minfo.quirk->_quirk ? \
(sensor)->minfo.quirk->_quirk(sensor, ##__VA_ARGS__) : 0)
-#define smiapp_needs_quirk(sensor, _quirk) \
+#define ccs_needs_quirk(sensor, _quirk) \
((sensor)->minfo.quirk ? \
(sensor)->minfo.quirk->flags & _quirk : 0)
-extern const struct smiapp_quirk smiapp_jt8ev1_quirk;
-extern const struct smiapp_quirk smiapp_imx125es_quirk;
-extern const struct smiapp_quirk smiapp_jt8ew9_quirk;
-extern const struct smiapp_quirk smiapp_tcm8500md_quirk;
+extern const struct ccs_quirk smiapp_jt8ev1_quirk;
+extern const struct ccs_quirk smiapp_imx125es_quirk;
+extern const struct ccs_quirk smiapp_jt8ew9_quirk;
+extern const struct ccs_quirk smiapp_tcm8500md_quirk;
-#endif /* __SMIAPP_QUIRK__ */
+#endif /* __CCS_QUIRK__ */
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
new file mode 100644
index 000000000000..b776af2a3c33
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * drivers/media/i2c/ccs/ccs-reg-access.c
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#include <asm/unaligned.h>
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+
+#include "ccs.h"
+#include "ccs-limits.h"
+
+static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
+ uint32_t phloat)
+{
+ int32_t exp;
+ uint64_t man;
+
+ if (phloat >= 0x80000000) {
+ dev_err(&client->dev, "this is a negative number\n");
+ return 0;
+ }
+
+ if (phloat == 0x7f800000)
+ return ~0; /* Inf. */
+
+ if ((phloat & 0x7f800000) == 0x7f800000) {
+ dev_err(&client->dev, "NaN or other special number\n");
+ return 0;
+ }
+
+ /* Valid cases begin here */
+ if (phloat == 0)
+ return 0; /* Valid zero */
+
+ if (phloat > 0x4f800000)
+ return ~0; /* larger than 4294967295 */
+
+ /*
+ * Unbias exponent (note how phloat is now guaranteed to
+ * have 0 in the high bit)
+ */
+ exp = ((int32_t)phloat >> 23) - 127;
+
+ /* Extract mantissa, add missing '1' bit and it's in MHz */
+ man = ((phloat & 0x7fffff) | 0x800000) * 1000000ULL;
+
+ if (exp < 0)
+ man >>= -exp;
+ else
+ man <<= exp;
+
+ man >>= 23; /* Remove mantissa bias */
+
+ return man & 0xffffffff;
+}
+
+
+/*
+ * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
+ * Returns zero if successful, or non-zero otherwise.
+ */
+static int ____ccs_read_addr(struct ccs_sensor *sensor, u16 reg, u16 len,
+ u32 *val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct i2c_msg msg;
+ unsigned char data_buf[sizeof(u32)] = { 0 };
+ unsigned char offset_buf[sizeof(u16)];
+ int r;
+
+ if (len > sizeof(data_buf))
+ return -EINVAL;
+
+ msg.addr = client->addr;
+ msg.flags = 0;
+ msg.len = sizeof(offset_buf);
+ msg.buf = offset_buf;
+ put_unaligned_be16(reg, offset_buf);
+
+ r = i2c_transfer(client->adapter, &msg, 1);
+ if (r != 1) {
+ if (r >= 0)
+ r = -EBUSY;
+ goto err;
+ }
+
+ msg.len = len;
+ msg.flags = I2C_M_RD;
+ msg.buf = &data_buf[sizeof(data_buf) - len];
+
+ r = i2c_transfer(client->adapter, &msg, 1);
+ if (r != 1) {
+ if (r >= 0)
+ r = -EBUSY;
+ goto err;
+ }
+
+ *val = get_unaligned_be32(data_buf);
+
+ return 0;
+
+err:
+ dev_err(&client->dev, "read from offset 0x%x error %d\n", reg, r);
+
+ return r;
+}
+
+/* Read a register using 8-bit access only. */
+static int ____ccs_read_addr_8only(struct ccs_sensor *sensor, u16 reg,
+ u16 len, u32 *val)
+{
+ unsigned int i;
+ int rval;
+
+ *val = 0;
+
+ for (i = 0; i < len; i++) {
+ u32 val8;
+
+ rval = ____ccs_read_addr(sensor, reg + i, 1, &val8);
+ if (rval < 0)
+ return rval;
+ *val |= val8 << ((len - i - 1) << 3);
+ }
+
+ return 0;
+}
+
+unsigned int ccs_reg_width(u32 reg)
+{
+ if (reg & CCS_FL_16BIT)
+ return sizeof(uint16_t);
+ if (reg & CCS_FL_32BIT)
+ return sizeof(uint32_t);
+
+ return sizeof(uint8_t);
+}
+
+static u32 ireal32_to_u32_mul_1000000(struct i2c_client *client, u32 val)
+{
+ if (val >> 10 > U32_MAX / 15625) {
+ dev_warn(&client->dev, "value %u overflows!\n", val);
+ return U32_MAX;
+ }
+
+ return ((val >> 10) * 15625) +
+ (val & GENMASK(9, 0)) * 15625 / 1024;
+}
+
+u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+
+ if (reg & CCS_FL_FLOAT_IREAL) {
+ if (CCS_LIM(sensor, CLOCK_CAPA_TYPE_CAPABILITY) &
+ CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL)
+ val = ireal32_to_u32_mul_1000000(client, val);
+ else
+ val = float_to_u32_mul_1000000(client, val);
+ } else if (reg & CCS_FL_IREAL) {
+ val = ireal32_to_u32_mul_1000000(client, val);
+ }
+
+ return val;
+}
+
+/*
+ * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
+ * Returns zero if successful, or non-zero otherwise.
+ */
+static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,
+ bool only8, bool conv)
+{
+ unsigned int len = ccs_reg_width(reg);
+ int rval;
+
+ if (!only8)
+ rval = ____ccs_read_addr(sensor, CCS_REG_ADDR(reg), len, val);
+ else
+ rval = ____ccs_read_addr_8only(sensor, CCS_REG_ADDR(reg), len,
+ val);
+ if (rval < 0)
+ return rval;
+
+ if (!conv)
+ return 0;
+
+ *val = ccs_reg_conv(sensor, reg, *val);
+
+ return 0;
+}
+
+static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs,
+ u32 reg, u32 *val)
+{
+ unsigned int width = ccs_reg_width(reg);
+ size_t i;
+
+ for (i = 0; i < num_regs; i++, regs++) {
+ uint8_t *data;
+
+ if (regs->addr + regs->len < CCS_REG_ADDR(reg) + width)
+ continue;
+
+ if (regs->addr > CCS_REG_ADDR(reg))
+ break;
+
+ data = &regs->value[CCS_REG_ADDR(reg) - regs->addr];
+
+ switch (width) {
+ case sizeof(uint8_t):
+ *val = *data;
+ break;
+ case sizeof(uint16_t):
+ *val = get_unaligned_be16(data);
+ break;
+ case sizeof(uint32_t):
+ *val = get_unaligned_be32(data);
+ break;
+ default:
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+static int ccs_read_data(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ if (!__ccs_read_data(sensor->sdata.sensor_read_only_regs,
+ sensor->sdata.num_sensor_read_only_regs,
+ reg, val))
+ return 0;
+
+ return __ccs_read_data(sensor->mdata.module_read_only_regs,
+ sensor->mdata.num_module_read_only_regs,
+ reg, val);
+}
+
+static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,
+ bool force8, bool quirk, bool conv, bool data)
+{
+ int rval;
+
+ if (data) {
+ rval = ccs_read_data(sensor, reg, val);
+ if (!rval)
+ return 0;
+ }
+
+ if (quirk) {
+ *val = 0;
+ rval = ccs_call_quirk(sensor, reg_access, false, &reg, val);
+ if (rval == -ENOIOCTLCMD)
+ return 0;
+ if (rval < 0)
+ return rval;
+
+ if (force8)
+ return __ccs_read_addr(sensor, reg, val, true, conv);
+ }
+
+ return __ccs_read_addr(sensor, reg, val,
+ ccs_needs_quirk(sensor,
+ CCS_QUIRK_FLAG_8BIT_READ_ONLY),
+ conv);
+}
+
+int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ return ccs_read_addr_raw(sensor, reg, val, false, true, true, true);
+}
+
+int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ return ccs_read_addr_raw(sensor, reg, val, true, true, true, true);
+}
+
+int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ return ccs_read_addr_raw(sensor, reg, val, false, true, false, true);
+}
+
+static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg)
+{
+ unsigned int retries;
+ int r;
+
+ for (retries = 0; retries < 10; retries++) {
+ /*
+ * Due to unknown reason sensor stops responding. This
+ * loop is a temporaty solution until the root cause
+ * is found.
+ */
+ r = i2c_transfer(client->adapter, msg, 1);
+ if (r != 1) {
+ usleep_range(1000, 2000);
+ continue;
+ }
+
+ if (retries)
+ dev_err(&client->dev,
+ "sensor i2c stall encountered. retries: %d\n",
+ retries);
+ return 0;
+ }
+
+ return r;
+}
+
+int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct i2c_msg msg;
+ unsigned char data[6];
+ unsigned int len = ccs_reg_width(reg);
+ int r;
+
+ if (len > sizeof(data) - 2)
+ return -EINVAL;
+
+ msg.addr = client->addr;
+ msg.flags = 0; /* Write */
+ msg.len = 2 + len;
+ msg.buf = data;
+
+ put_unaligned_be16(CCS_REG_ADDR(reg), data);
+ put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
+
+ dev_dbg(&client->dev, "writing reg 0x%4.4x value 0x%*.*x (%u)\n",
+ CCS_REG_ADDR(reg), ccs_reg_width(reg) << 1,
+ ccs_reg_width(reg) << 1, val, val);
+
+ r = ccs_write_retry(client, &msg);
+ if (r)
+ dev_err(&client->dev,
+ "wrote 0x%x to offset 0x%x error %d\n", val,
+ CCS_REG_ADDR(reg), r);
+
+ return r;
+}
+
+/*
+ * Write to a 8/16-bit register.
+ * Returns zero if successful, or non-zero otherwise.
+ */
+int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)
+{
+ int rval;
+
+ rval = ccs_call_quirk(sensor, reg_access, true, &reg, &val);
+ if (rval == -ENOIOCTLCMD)
+ return 0;
+ if (rval < 0)
+ return rval;
+
+ return ccs_write_addr_no_quirk(sensor, reg, val);
+}
+
+#define MAX_WRITE_LEN 32U
+
+int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
+ size_t num_regs)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ unsigned char buf[2 + MAX_WRITE_LEN];
+ struct i2c_msg msg = {
+ .addr = client->addr,
+ .buf = buf,
+ };
+ size_t i;
+
+ for (i = 0; i < num_regs; i++, regs++) {
+ unsigned char *regdata = regs->value;
+ unsigned int j;
+
+ for (j = 0; j < regs->len;
+ j += msg.len - 2, regdata += msg.len - 2) {
+ int rval;
+
+ msg.len = min(regs->len - j, MAX_WRITE_LEN);
+
+ put_unaligned_be16(regs->addr + j, buf);
+ memcpy(buf + 2, regdata, msg.len);
+ msg.len += 2;
+
+ rval = ccs_write_retry(client, &msg);
+ if (rval) {
+ dev_err(&client->dev,
+ "error writing %u octets to address 0x%4.4x\n",
+ msg.len, regs->addr + j);
+ return rval;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h
new file mode 100644
index 000000000000..78c43f92d99a
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-reg-access.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * include/media/ccs/ccs-reg-access.h
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#ifndef SMIAPP_REGS_H
+#define SMIAPP_REGS_H
+
+#include <linux/i2c.h>
+#include <linux/types.h>
+
+#include "ccs-regs.h"
+
+#define CCS_REG_ADDR(reg) ((u16)reg)
+
+struct ccs_sensor;
+
+int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val);
+int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val);
+int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
+ size_t num_regs);
+
+unsigned int ccs_reg_width(u32 reg);
+u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val);
+
+#define ccs_read(sensor, reg_name, val) \
+ ccs_read_addr(sensor, CCS_R_##reg_name, val)
+
+#define ccs_write(sensor, reg_name, val) \
+ ccs_write_addr(sensor, CCS_R_##reg_name, val)
+
+#endif
diff --git a/drivers/media/i2c/ccs/ccs-regs.h b/drivers/media/i2c/ccs/ccs-regs.h
new file mode 100644
index 000000000000..4b3e5df2121f
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-regs.h
@@ -0,0 +1,954 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/* Copyright (C) 2019--2020 Intel Corporation */
+
+#ifndef __CCS_REGS_H__
+#define __CCS_REGS_H__
+
+#include <linux/bits.h>
+
+#define CCS_FL_BASE 16
+#define CCS_FL_16BIT BIT(CCS_FL_BASE)
+#define CCS_FL_32BIT BIT(CCS_FL_BASE + 1)
+#define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE + 2)
+#define CCS_FL_IREAL BIT(CCS_FL_BASE + 3)
+#define CCS_R_ADDR(r) ((r) & 0xffff)
+
+#define CCS_R_MODULE_MODEL_ID (0x0000 | CCS_FL_16BIT)
+#define CCS_R_MODULE_REVISION_NUMBER_MAJOR 0x0002
+#define CCS_R_FRAME_COUNT 0x0005
+#define CCS_R_PIXEL_ORDER 0x0006
+#define CCS_PIXEL_ORDER_GRBG 0U
+#define CCS_PIXEL_ORDER_RGGB 1U
+#define CCS_PIXEL_ORDER_BGGR 2U
+#define CCS_PIXEL_ORDER_GBRG 3U
+#define CCS_R_MIPI_CCS_VERSION 0x0007
+#define CCS_MIPI_CCS_VERSION_V1_0 0x10
+#define CCS_MIPI_CCS_VERSION_V1_1 0x11
+#define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT 4U
+#define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0
+#define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
+#define CCS_MIPI_CCS_VERSION_MINOR_MASK 0xf
+#define CCS_R_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
+#define CCS_R_MODULE_MANUFACTURER_ID (0x000e | CCS_FL_16BIT)
+#define CCS_R_MODULE_REVISION_NUMBER_MINOR 0x0010
+#define CCS_R_MODULE_DATE_YEAR 0x0012
+#define CCS_R_MODULE_DATE_MONTH 0x0013
+#define CCS_R_MODULE_DATE_DAY 0x0014
+#define CCS_R_MODULE_DATE_PHASE 0x0015
+#define CCS_MODULE_DATE_PHASE_SHIFT 0U
+#define CCS_MODULE_DATE_PHASE_MASK 0x7
+#define CCS_MODULE_DATE_PHASE_TS 0U
+#define CCS_MODULE_DATE_PHASE_ES 1U
+#define CCS_MODULE_DATE_PHASE_CS 2U
+#define CCS_MODULE_DATE_PHASE_MP 3U
+#define CCS_R_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT)
+#define CCS_R_SENSOR_REVISION_NUMBER 0x0018
+#define CCS_R_SENSOR_FIRMWARE_VERSION 0x001a
+#define CCS_R_SERIAL_NUMBER (0x001c | CCS_FL_32BIT)
+#define CCS_R_SENSOR_MANUFACTURER_ID (0x0020 | CCS_FL_16BIT)
+#define CCS_R_SENSOR_REVISION_NUMBER_16 (0x0022 | CCS_FL_16BIT)
+#define CCS_R_FRAME_FORMAT_MODEL_TYPE 0x0040
+#define CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE 1U
+#define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U
+#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
+#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) ((0x0042 | CCS_FL_16BIT) + (n) * 2)
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MAX_N 14U
+#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 | CCS_FL_32BIT) + (n) * 4)
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK 0xfff
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK 0xf000
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED 1U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL 2U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL 3U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL 4U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL 5U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_0 8U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_1 9U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_2 10U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_3 11U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_4 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_5 13U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_6 14U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MAX_N 7U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK 0xffff
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT 28U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK 0xf0000000
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_EMBEDDED 1U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DUMMY_PIXEL 2U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_BLACK_PIXEL 3U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DARK_PIXEL 4U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_VISIBLE_PIXEL 5U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_0 8U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_1 9U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_2 10U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_3 11U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_4 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_5 13U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_6 14U
+#define CCS_R_ANALOG_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT)
+#define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U
+#define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL 2U
+#define CCS_R_ANALOG_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_TYPE (0x008a | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_M0 (0x008c | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_C0 (0x008e | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_M1 (0x0090 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_C1 (0x0092 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_MIN (0x0094 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_MAX (0x0096 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE (0x0098 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN (0x009a | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX (0x009c | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE (0x009e | CCS_FL_16BIT)
+#define CCS_R_DATA_FORMAT_MODEL_TYPE 0x00c0
+#define CCS_DATA_FORMAT_MODEL_TYPE_NORMAL 1U
+#define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED 2U
+#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE 0x00c1
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
+#define CCS_R_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 | CCS_FL_16BIT) + (n) * 2)
+#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N 0U
+#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N 15U
+#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT 0U
+#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK 0xff
+#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT 8U
+#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK 0xff00
+#define CCS_R_MODE_SELECT 0x0100
+#define CCS_MODE_SELECT_SOFTWARE_STANDBY 0U
+#define CCS_MODE_SELECT_STREAMING 1U
+#define CCS_R_IMAGE_ORIENTATION 0x0101
+#define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR BIT(0)
+#define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP BIT(1)
+#define CCS_R_SOFTWARE_RESET 0x0103
+#define CCS_SOFTWARE_RESET_OFF 0U
+#define CCS_SOFTWARE_RESET_ON 1U
+#define CCS_R_GROUPED_PARAMETER_HOLD 0x0104
+#define CCS_R_MASK_CORRUPTED_FRAMES 0x0105
+#define CCS_MASK_CORRUPTED_FRAMES_ALLOW 0U
+#define CCS_MASK_CORRUPTED_FRAMES_MASK 1U
+#define CCS_R_FAST_STANDBY_CTRL 0x0106
+#define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0U
+#define CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION 1U
+#define CCS_R_CCI_ADDRESS_CTRL 0x0107
+#define CCS_R_2ND_CCI_IF_CTRL 0x0108
+#define CCS_2ND_CCI_IF_CTRL_ENABLE BIT(0)
+#define CCS_2ND_CCI_IF_CTRL_ACK BIT(1)
+#define CCS_R_2ND_CCI_ADDRESS_CTRL 0x0109
+#define CCS_R_CSI_CHANNEL_IDENTIFIER 0x0110
+#define CCS_R_CSI_SIGNALING_MODE 0x0111
+#define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY 2U
+#define CCS_CSI_SIGNALING_MODE_CSI_2_CPHY 3U
+#define CCS_R_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT)
+#define CCS_R_CSI_LANE_MODE 0x0114
+#define CCS_R_DPCM_FRAME_DT 0x011d
+#define CCS_R_BOTTOM_EMBEDDED_DATA_DT 0x011e
+#define CCS_R_BOTTOM_EMBEDDED_DATA_VC 0x011f
+#define CCS_R_GAIN_MODE 0x0120
+#define CCS_GAIN_MODE_GLOBAL 0U
+#define CCS_GAIN_MODE_ALTERNATE 1U
+#define CCS_R_ADC_BIT_DEPTH 0x0121
+#define CCS_R_EMB_DATA_CTRL 0x0122
+#define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 BIT(0)
+#define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20 BIT(1)
+#define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24 BIT(2)
+#define CCS_R_GPIO_TRIG_MODE 0x0130
+#define CCS_R_EXTCLK_FREQUENCY_MHZ (0x0136 | (CCS_FL_16BIT | CCS_FL_IREAL))
+#define CCS_R_TEMP_SENSOR_CTRL 0x0138
+#define CCS_TEMP_SENSOR_CTRL_ENABLE BIT(0)
+#define CCS_R_TEMP_SENSOR_MODE 0x0139
+#define CCS_R_TEMP_SENSOR_OUTPUT 0x013a
+#define CCS_R_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT)
+#define CCS_R_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL (0x0206 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0208 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_GLOBAL (0x020e | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL (0x0216 | CCS_FL_16BIT)
+#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL (0x0218 | CCS_FL_16BIT)
+#define CCS_R_HDR_MODE 0x0220
+#define CCS_HDR_MODE_ENABLED BIT(0)
+#define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN BIT(1)
+#define CCS_HDR_MODE_UPSCALING BIT(2)
+#define CCS_HDR_MODE_RESET_SYNC BIT(3)
+#define CCS_HDR_MODE_TIMING_MODE BIT(4)
+#define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT BIT(5)
+#define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN BIT(6)
+#define CCS_R_HDR_RESOLUTION_REDUCTION 0x0221
+#define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT 0U
+#define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK 0xf
+#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_SHIFT 4U
+#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK 0xf0
+#define CCS_R_EXPOSURE_RATIO 0x0222
+#define CCS_R_HDR_INTERNAL_BIT_DEPTH 0x0223
+#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME (0x0224 | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL (0x0226 | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0228 | CCS_FL_16BIT)
+#define CCS_R_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT)
+#define CCS_R_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT)
+#define CCS_R_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT)
+#define CCS_R_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT)
+#define CCS_R_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
+#define CCS_R_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
+#define CCS_R_OP_PRE_PLL_CLK_DIV (0x030c | CCS_FL_16BIT)
+#define CCS_R_OP_PLL_MULTIPLIER (0x031e | CCS_FL_16BIT)
+#define CCS_R_PLL_MODE 0x0310
+#define CCS_PLL_MODE_SHIFT 0U
+#define CCS_PLL_MODE_MASK 0x1
+#define CCS_PLL_MODE_SINGLE 0U
+#define CCS_PLL_MODE_DUAL 1U
+#define CCS_R_OP_PIX_CLK_DIV_REV (0x0312 | CCS_FL_16BIT)
+#define CCS_R_OP_SYS_CLK_DIV_REV (0x0314 | CCS_FL_16BIT)
+#define CCS_R_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT)
+#define CCS_R_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_START (0x0344 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_START (0x0346 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_END (0x0348 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_END (0x034a | CCS_FL_16BIT)
+#define CCS_R_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT)
+#define CCS_R_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT)
+#define CCS_R_FRAME_LENGTH_CTRL 0x0350
+#define CCS_FRAME_LENGTH_CTRL_AUTOMATIC BIT(0)
+#define CCS_R_TIMING_MODE_CTRL 0x0352
+#define CCS_TIMING_MODE_CTRL_MANUAL_READOUT BIT(0)
+#define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE BIT(1)
+#define CCS_R_START_READOUT_RS 0x0353
+#define CCS_START_READOUT_RS_MANUAL_READOUT_START BIT(0)
+#define CCS_R_FRAME_MARGIN (0x0354 | CCS_FL_16BIT)
+#define CCS_R_X_EVEN_INC (0x0380 | CCS_FL_16BIT)
+#define CCS_R_X_ODD_INC (0x0382 | CCS_FL_16BIT)
+#define CCS_R_Y_EVEN_INC (0x0384 | CCS_FL_16BIT)
+#define CCS_R_Y_ODD_INC (0x0386 | CCS_FL_16BIT)
+#define CCS_R_MONOCHROME_EN 0x0390
+#define CCS_MONOCHROME_EN_ENABLED 0U
+#define CCS_R_SCALING_MODE (0x0400 | CCS_FL_16BIT)
+#define CCS_SCALING_MODE_NO_SCALING 0U
+#define CCS_SCALING_MODE_HORIZONTAL 1U
+#define CCS_R_SCALE_M (0x0404 | CCS_FL_16BIT)
+#define CCS_R_SCALE_N (0x0406 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT)
+#define CCS_R_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT)
+#define CCS_COMPRESSION_MODE_NONE 0U
+#define CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE 1U
+#define CCS_R_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT)
+#define CCS_TEST_PATTERN_MODE_NONE 0U
+#define CCS_TEST_PATTERN_MODE_SOLID_COLOR 1U
+#define CCS_TEST_PATTERN_MODE_COLOR_BARS 2U
+#define CCS_TEST_PATTERN_MODE_FADE_TO_GREY 3U
+#define CCS_TEST_PATTERN_MODE_PN9 4U
+#define CCS_TEST_PATTERN_MODE_COLOR_TILE 5U
+#define CCS_R_TEST_DATA_RED (0x0602 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT)
+#define CCS_R_VALUE_STEP_SIZE_SMOOTH 0x060a
+#define CCS_R_VALUE_STEP_SIZE_QUANTISED 0x060b
+#define CCS_R_TCLK_POST 0x0800
+#define CCS_R_THS_PREPARE 0x0801
+#define CCS_R_THS_ZERO_MIN 0x0802
+#define CCS_R_THS_TRAIL 0x0803
+#define CCS_R_TCLK_TRAIL_MIN 0x0804
+#define CCS_R_TCLK_PREPARE 0x0805
+#define CCS_R_TCLK_ZERO 0x0806
+#define CCS_R_TLPX 0x0807
+#define CCS_R_PHY_CTRL 0x0808
+#define CCS_PHY_CTRL_AUTO 0U
+#define CCS_PHY_CTRL_UI 1U
+#define CCS_PHY_CTRL_MANUAL 2U
+#define CCS_R_TCLK_POST_EX (0x080a | CCS_FL_16BIT)
+#define CCS_R_THS_PREPARE_EX (0x080c | CCS_FL_16BIT)
+#define CCS_R_THS_ZERO_MIN_EX (0x080e | CCS_FL_16BIT)
+#define CCS_R_THS_TRAIL_EX (0x0810 | CCS_FL_16BIT)
+#define CCS_R_TCLK_TRAIL_MIN_EX (0x0812 | CCS_FL_16BIT)
+#define CCS_R_TCLK_PREPARE_EX (0x0814 | CCS_FL_16BIT)
+#define CCS_R_TCLK_ZERO_EX (0x0816 | CCS_FL_16BIT)
+#define CCS_R_TLPX_EX (0x0818 | CCS_FL_16BIT)
+#define CCS_R_REQUESTED_LINK_RATE (0x0820 | CCS_FL_32BIT)
+#define CCS_R_DPHY_EQUALIZATION_MODE 0x0824
+#define CCS_DPHY_EQUALIZATION_MODE_EQ2 BIT(0)
+#define CCS_R_PHY_EQUALIZATION_CTRL 0x0825
+#define CCS_PHY_EQUALIZATION_CTRL_ENABLE BIT(0)
+#define CCS_R_DPHY_PREAMBLE_CTRL 0x0826
+#define CCS_DPHY_PREAMBLE_CTRL_ENABLE BIT(0)
+#define CCS_R_DPHY_PREAMBLE_LENGTH 0x0826
+#define CCS_R_PHY_SSC_CTRL 0x0828
+#define CCS_PHY_SSC_CTRL_ENABLE BIT(0)
+#define CCS_R_MANUAL_LP_CTRL 0x0829
+#define CCS_MANUAL_LP_CTRL_ENABLE BIT(0)
+#define CCS_R_TWAKEUP 0x082a
+#define CCS_R_TINIT 0x082b
+#define CCS_R_THS_EXIT 0x082c
+#define CCS_R_THS_EXIT_EX (0x082e | CCS_FL_16BIT)
+#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL 0x0830
+#define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING BIT(0)
+#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL 0x0831
+#define CCS_R_PHY_INIT_CALIBRATION_CTRL 0x0832
+#define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START BIT(0)
+#define CCS_R_DPHY_CALIBRATION_MODE 0x0833
+#define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE BIT(0)
+#define CCS_R_CPHY_CALIBRATION_MODE 0x0834
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_1 0U
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_2 1U
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_3 2U
+#define CCS_R_T3_CALPREAMBLE_LENGTH 0x0835
+#define CCS_R_T3_CALPREAMBLE_LENGTH_PER 0x0836
+#define CCS_R_T3_CALALTSEQ_LENGTH 0x0837
+#define CCS_R_T3_CALALTSEQ_LENGTH_PER 0x0838
+#define CCS_R_FM2_INIT_SEED (0x083a | CCS_FL_16BIT)
+#define CCS_R_T3_CALUDEFSEQ_LENGTH (0x083c | CCS_FL_16BIT)
+#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER (0x083e | CCS_FL_16BIT)
+#define CCS_R_TGR_PREAMBLE_LENGTH 0x0841
+#define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ BIT(7)
+#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT 0U
+#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK 0x3f
+#define CCS_R_TGR_POST_LENGTH 0x0842
+#define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT 0U
+#define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK 0x1f
+#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2) (0x0843 + (n2))
+#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2 0U
+#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MAX_N2 6U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_SHIFT 3U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK 0x38
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT 0U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK 0x7
+#define CCS_R_T3_PREPARE (0x084e | CCS_FL_16BIT)
+#define CCS_R_T3_LPX (0x0850 | CCS_FL_16BIT)
+#define CCS_R_ALPS_CTRL 0x085a
+#define CCS_ALPS_CTRL_LVLP_DPHY BIT(0)
+#define CCS_ALPS_CTRL_LVLP_CPHY BIT(1)
+#define CCS_ALPS_CTRL_ALP_CPHY BIT(2)
+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY (0x0860 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY (0x0862 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY (0x0864 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY (0x0866 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY 0x0868
+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY 0x0869
+#define CCS_R_SCRAMBLING_CTRL 0x0870
+#define CCS_SCRAMBLING_CTRL_ENABLED BIT(0)
+#define CCS_SCRAMBLING_CTRL_SHIFT 2U
+#define CCS_SCRAMBLING_CTRL_MASK 0xc
+#define CCS_SCRAMBLING_CTRL_1_SEED_CPHY 0U
+#define CCS_SCRAMBLING_CTRL_4_SEED_CPHY 3U
+#define CCS_R_LANE_SEED_VALUE(seed, lane) ((0x0872 | CCS_FL_16BIT) + (seed) * 16 + (lane) * 2)
+#define CCS_LIM_LANE_SEED_VALUE_MIN_SEED 0U
+#define CCS_LIM_LANE_SEED_VALUE_MAX_SEED 3U
+#define CCS_LIM_LANE_SEED_VALUE_MIN_LANE 0U
+#define CCS_LIM_LANE_SEED_VALUE_MAX_LANE 7U
+#define CCS_R_TX_USL_REV_ENTRY (0x08c0 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_CLOCK_COUNTER (0x08c2 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_LP_COUNTER (0x08c4 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_FRAME_COUNTER (0x08c6 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER (0x08c8 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_FWD_ENTRY (0x08ca | CCS_FL_16BIT)
+#define CCS_R_TX_USL_GPIO (0x08cc | CCS_FL_16BIT)
+#define CCS_R_TX_USL_OPERATION (0x08ce | CCS_FL_16BIT)
+#define CCS_TX_USL_OPERATION_RESET BIT(0)
+#define CCS_R_TX_USL_ALP_CTRL (0x08d0 | CCS_FL_16BIT)
+#define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE BIT(0)
+#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT)
+#define CCS_R_USL_CLOCK_MODE_D_CTRL 0x08d2
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY BIT(0)
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK BIT(1)
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK BIT(2)
+#define CCS_R_BINNING_MODE 0x0900
+#define CCS_R_BINNING_TYPE 0x0901
+#define CCS_R_BINNING_WEIGHTING 0x0902
+#define CCS_R_DATA_TRANSFER_IF_1_CTRL 0x0a00
+#define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE BIT(0)
+#define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE BIT(1)
+#define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR BIT(2)
+#define CCS_R_DATA_TRANSFER_IF_1_STATUS 0x0a01
+#define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY BIT(0)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY BIT(1)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED BIT(2)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE BIT(3)
+#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02
+#define CCS_R_DATA_TRANSFER_IF_1_DATA(p) (0x0a04 + (p))
+#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P 0U
+#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P 63U
+#define CCS_R_SHADING_CORRECTION_EN 0x0b00
+#define CCS_SHADING_CORRECTION_EN_ENABLE BIT(0)
+#define CCS_R_LUMINANCE_CORRECTION_LEVEL 0x0b01
+#define CCS_R_GREEN_IMBALANCE_FILTER_EN 0x0b02
+#define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE BIT(0)
+#define CCS_R_MAPPED_DEFECT_CORRECT_EN 0x0b05
+#define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_SINGLE_DEFECT_CORRECT_EN 0x0b06
+#define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN 0x0b08
+#define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_COMBINED_DEFECT_CORRECT_EN 0x0b0a
+#define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN 0x0b0c
+#define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE BIT(0)
+#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN 0x0b13
+#define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_NF_CTRL 0x0b15
+#define CCS_NF_CTRL_LUMA BIT(0)
+#define CCS_NF_CTRL_CHROMA BIT(1)
+#define CCS_NF_CTRL_COMBINED BIT(2)
+#define CCS_R_OB_READOUT_CONTROL 0x0b30
+#define CCS_OB_READOUT_CONTROL_ENABLE BIT(0)
+#define CCS_OB_READOUT_CONTROL_INTERLEAVING BIT(1)
+#define CCS_R_OB_VIRTUAL_CHANNEL 0x0b31
+#define CCS_R_OB_DT 0x0b32
+#define CCS_R_OB_DATA_FORMAT 0x0b33
+#define CCS_R_COLOR_TEMPERATURE (0x0b8c | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT)
+#define CCS_R_CFA_CONVERSION_CTRL 0x0ba0
+#define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE BIT(0)
+#define CCS_R_FLASH_STROBE_ADJUSTMENT 0x0c12
+#define CCS_R_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT)
+#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT)
+#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT)
+#define CCS_R_FLASH_MODE_RS 0x0c1a
+#define CCS_FLASH_MODE_RS_CONTINUOUS BIT(0)
+#define CCS_FLASH_MODE_RS_TRUNCATE BIT(1)
+#define CCS_FLASH_MODE_RS_ASYNC BIT(3)
+#define CCS_R_FLASH_TRIGGER_RS 0x0c1b
+#define CCS_R_FLASH_STATUS 0x0c1c
+#define CCS_FLASH_STATUS_RETIMED BIT(0)
+#define CCS_R_SA_STROBE_MODE 0x0c1d
+#define CCS_SA_STROBE_MODE_CONTINUOUS BIT(0)
+#define CCS_SA_STROBE_MODE_TRUNCATE BIT(1)
+#define CCS_SA_STROBE_MODE_ASYNC BIT(3)
+#define CCS_SA_STROBE_MODE_ADJUST_EDGE BIT(4)
+#define CCS_R_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT)
+#define CCS_R_SA_STROBE_TRIGGER 0x0c24
+#define CCS_R_SA_STROBE_STATUS 0x0c25
+#define CCS_SA_STROBE_STATUS_RETIMED BIT(0)
+#define CCS_R_TSA_STROBE_RE_DELAY_CTRL (0x0c30 | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_FE_DELAY_CTRL (0x0c32 | CCS_FL_16BIT)
+#define CCS_R_PDAF_CTRL (0x0d00 | CCS_FL_16BIT)
+#define CCS_PDAF_CTRL_ENABLE BIT(0)
+#define CCS_PDAF_CTRL_PROCESSED BIT(1)
+#define CCS_PDAF_CTRL_INTERLEAVED BIT(2)
+#define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION BIT(3)
+#define CCS_R_PDAF_VC 0x0d02
+#define CCS_R_PDAF_DT 0x0d03
+#define CCS_R_PD_X_ADDR_START (0x0d04 | CCS_FL_16BIT)
+#define CCS_R_PD_Y_ADDR_START (0x0d06 | CCS_FL_16BIT)
+#define CCS_R_PD_X_ADDR_END (0x0d08 | CCS_FL_16BIT)
+#define CCS_R_PD_Y_ADDR_END (0x0d0a | CCS_FL_16BIT)
+#define CCS_R_BRACKETING_LUT_CTRL 0x0e00
+#define CCS_R_BRACKETING_LUT_MODE 0x0e01
+#define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING BIT(0)
+#define CCS_BRACKETING_LUT_MODE_LOOP_MODE BIT(1)
+#define CCS_R_BRACKETING_LUT_ENTRY_CTRL 0x0e02
+#define CCS_R_BRACKETING_LUT_FRAME(n) (0x0e10 + (n))
+#define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N 0U
+#define CCS_LIM_BRACKETING_LUT_FRAME_MAX_N 239U
+#define CCS_R_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT)
+#define CCS_INTEGRATION_TIME_CAPABILITY_FINE BIT(0)
+#define CCS_R_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT)
+#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_CAPABILITY 0x1081
+#define CCS_DIGITAL_GAIN_CAPABILITY_NONE 0U
+#define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL 2U
+#define CCS_R_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT)
+#define CCS_R_PEDESTAL_CAPABILITY 0x10e0
+#define CCS_R_ADC_CAPABILITY 0x10f0
+#define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL BIT(0)
+#define CCS_R_ADC_BIT_DEPTH_CAPABILITY (0x10f4 | CCS_FL_32BIT)
+#define CCS_R_MIN_EXT_CLK_FREQ_MHZ (0x1100 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_EXT_CLK_FREQ_MHZ (0x1104 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT)
+#define CCS_R_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT)
+#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (0x110c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (0x1110 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT)
+#define CCS_R_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT)
+#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (0x1118 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (0x111c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT)
+#define CCS_R_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT)
+#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ (0x1124 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ (0x1128 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ (0x112c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ (0x1130 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT)
+#define CCS_R_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT)
+#define CCS_R_CLOCK_CALCULATION 0x1138
+#define CCS_CLOCK_CALCULATION_LANE_SPEED BIT(0)
+#define CCS_CLOCK_CALCULATION_LINK_DECOUPLED BIT(1)
+#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR BIT(2)
+#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR BIT(3)
+#define CCS_R_NUM_OF_VT_LANES 0x1139
+#define CCS_R_NUM_OF_OP_LANES 0x113a
+#define CCS_R_OP_BITS_PER_LANE 0x113b
+#define CCS_R_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT)
+#define CCS_R_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT)
+#define CCS_R_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT)
+#define CCS_R_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c
+#define CCS_R_TIMING_MODE_CAPABILITY 0x114d
+#define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH BIT(0)
+#define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT BIT(2)
+#define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START BIT(3)
+#define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA BIT(4)
+#define CCS_R_FRAME_MARGIN_MAX_VALUE (0x114e | CCS_FL_16BIT)
+#define CCS_R_FRAME_MARGIN_MIN_VALUE 0x1150
+#define CCS_R_GAIN_DELAY_TYPE 0x1151
+#define CCS_GAIN_DELAY_TYPE_FIXED 0U
+#define CCS_GAIN_DELAY_TYPE_VARIABLE 1U
+#define CCS_R_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ (0x1164 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ (0x1168 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ (0x1170 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ (0x1174 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_X_ADDR_MIN (0x1180 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_MAX (0x1184 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT)
+#define CCS_R_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT)
+#define CCS_R_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT)
+#define CCS_R_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT)
+#define CCS_R_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_START_DIV_CONSTANT 0x1190
+#define CCS_R_Y_ADDR_START_DIV_CONSTANT 0x1191
+#define CCS_R_X_ADDR_END_DIV_CONSTANT 0x1192
+#define CCS_R_Y_ADDR_END_DIV_CONSTANT 0x1193
+#define CCS_R_X_SIZE_DIV 0x1194
+#define CCS_R_Y_SIZE_DIV 0x1195
+#define CCS_R_X_OUTPUT_DIV 0x1196
+#define CCS_R_Y_OUTPUT_DIV 0x1197
+#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT 0x1198
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR BIT(0)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES BIT(1)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD BIT(2)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP BIT(3)
+#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV (0x11a0 | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV (0x11a2 | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ (0x11a4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ (0x11a8 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PLL_MULTIPLIER (0x11ac | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PLL_MULTIPLIER (0x11ae | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ (0x11b0 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ (0x11b4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_CLOCK_TREE_PLL_CAPABILITY 0x11b8
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL BIT(0)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL BIT(1)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER BIT(2)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV BIT(3)
+#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY 0x11b9
+#define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL BIT(0)
+#define CCS_R_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC (0x11c2 | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC (0x11c4 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT)
+#define CCS_R_AUX_SUBSAMP_CAPABILITY 0x11c8
+#define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
+#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY 0x11c9
+#define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
+#define CCS_R_MONOCHROME_CAPABILITY 0x11ca
+#define CCS_MONOCHROME_CAPABILITY_INC_ODD 0U
+#define CCS_MONOCHROME_CAPABILITY_INC_EVEN 1U
+#define CCS_R_PIXEL_READOUT_CAPABILITY 0x11cb
+#define CCS_PIXEL_READOUT_CAPABILITY_BAYER 0U
+#define CCS_PIXEL_READOUT_CAPABILITY_MONOCHROME 1U
+#define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO 2U
+#define CCS_R_MIN_EVEN_INC_MONO (0x11cc | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_MONO (0x11ce | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_MONO (0x11d0 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_MONO (0x11d2 | CCS_FL_16BIT)
+#define CCS_R_MIN_EVEN_INC_BC2 (0x11d4 | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_BC2 (0x11d6 | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_BC2 (0x11d8 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_BC2 (0x11da | CCS_FL_16BIT)
+#define CCS_R_MIN_EVEN_INC_MONO_BC2 (0x11dc | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_MONO_BC2 (0x11de | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_MONO_BC2 (0x11f0 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_MONO_BC2 (0x11f2 | CCS_FL_16BIT)
+#define CCS_R_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT)
+#define CCS_SCALING_CAPABILITY_NONE 0U
+#define CCS_SCALING_CAPABILITY_HORIZONTAL 1U
+#define CCS_SCALING_CAPABILITY_RESERVED 2U
+#define CCS_R_SCALER_M_MIN (0x1204 | CCS_FL_16BIT)
+#define CCS_R_SCALER_M_MAX (0x1206 | CCS_FL_16BIT)
+#define CCS_R_SCALER_N_MIN (0x1208 | CCS_FL_16BIT)
+#define CCS_R_SCALER_N_MAX (0x120a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_CAPABILITY 0x120e
+#define CCS_DIGITAL_CROP_CAPABILITY_NONE 0U
+#define CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1U
+#define CCS_R_HDR_CAPABILITY_1 0x1210
+#define CCS_HDR_CAPABILITY_1_2X2_BINNING BIT(0)
+#define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN BIT(1)
+#define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN BIT(2)
+#define CCS_HDR_CAPABILITY_1_UPSCALING BIT(3)
+#define CCS_HDR_CAPABILITY_1_RESET_SYNC BIT(4)
+#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING BIT(5)
+#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS BIT(6)
+#define CCS_R_MIN_HDR_BIT_DEPTH 0x1211
+#define CCS_R_HDR_RESOLUTION_SUB_TYPES 0x1212
+#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n) (0x1213 + (n))
+#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N 0U
+#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MAX_N 1U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT 0U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK 0xf
+#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_SHIFT 4U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK 0xf0
+#define CCS_R_HDR_CAPABILITY_2 0x121b
+#define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN BIT(0)
+#define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN BIT(1)
+#define CCS_HDR_CAPABILITY_2_TIMING_MODE BIT(3)
+#define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE BIT(4)
+#define CCS_R_MAX_HDR_BIT_DEPTH 0x121c
+#define CCS_R_USL_SUPPORT_CAPABILITY 0x1230
+#define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE BIT(0)
+#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE BIT(1)
+#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC BIT(2)
+#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY 0x1231
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY BIT(0)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK BIT(1)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK BIT(2)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY BIT(3)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK BIT(4)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK BIT(5)
+#define CCS_R_MIN_OP_SYS_CLK_DIV_REV 0x1234
+#define CCS_R_MAX_OP_SYS_CLK_DIV_REV 0x1236
+#define CCS_R_MIN_OP_PIX_CLK_DIV_REV 0x1238
+#define CCS_R_MAX_OP_PIX_CLK_DIV_REV 0x123a
+#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ (0x123c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ (0x1240 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ (0x1244 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ (0x1248 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS (0x124c | (CCS_FL_32BIT | CCS_FL_IREAL))
+#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS (0x1250 | (CCS_FL_32BIT | CCS_FL_IREAL))
+#define CCS_R_COMPRESSION_CAPABILITY 0x1300
+#define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE BIT(0)
+#define CCS_R_TEST_MODE_CAPABILITY (0x1310 | CCS_FL_16BIT)
+#define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR BIT(0)
+#define CCS_TEST_MODE_CAPABILITY_COLOR_BARS BIT(1)
+#define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY BIT(2)
+#define CCS_TEST_MODE_CAPABILITY_PN9 BIT(3)
+#define CCS_TEST_MODE_CAPABILITY_COLOR_TILE BIT(5)
+#define CCS_R_PN9_DATA_FORMAT1 0x1312
+#define CCS_R_PN9_DATA_FORMAT2 0x1313
+#define CCS_R_PN9_DATA_FORMAT3 0x1314
+#define CCS_R_PN9_DATA_FORMAT4 0x1315
+#define CCS_R_PN9_MISC_CAPABILITY 0x1316
+#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT 0U
+#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK 0x7
+#define CCS_PN9_MISC_CAPABILITY_COMPRESSION BIT(3)
+#define CCS_R_TEST_PATTERN_CAPABILITY 0x1317
+#define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT BIT(1)
+#define CCS_R_PATTERN_SIZE_DIV_M1 0x1318
+#define CCS_R_FIFO_SUPPORT_CAPABILITY 0x1502
+#define CCS_FIFO_SUPPORT_CAPABILITY_NONE 0U
+#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING 1U
+#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING 2U
+#define CCS_R_PHY_CTRL_CAPABILITY 0x1600
+#define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_2_CTL BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_CTL BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL BIT(6)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL BIT(7)
+#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY 0x1601
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
+#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY 0x1602
+#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY BIT(2)
+#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY BIT(3)
+#define CCS_R_FAST_STANDBY_CAPABILITY 0x1603
+#define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION 0U
+#define CCS_FAST_STANDBY_CAPABILITY_FRAME_TRUNCATION 1U
+#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY 0x1604
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE BIT(0)
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR BIT(1)
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR BIT(2)
+#define CCS_R_DATA_TYPE_CAPABILITY 0x1605
+#define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE BIT(0)
+#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE BIT(1)
+#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE BIT(2)
+#define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE BIT(3)
+#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY 0x1606
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
+#define CCS_R_EMB_DATA_CAPABILITY 0x1607
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 BIT(0)
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20 BIT(1)
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24 BIT(2)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16 BIT(3)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20 BIT(4)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24 BIT(5)
+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n) ((0x1608 | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4))
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N 0U
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MAX_N 7U
+#define CCS_R_TEMP_SENSOR_CAPABILITY 0x1618
+#define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT BIT(1)
+#define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80 BIT(2)
+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n) ((0x161a | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4))
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N 0U
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MAX_N 7U
+#define CCS_R_DPHY_EQUALIZATION_CAPABILITY 0x162b
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1 BIT(1)
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2 BIT(2)
+#define CCS_R_CPHY_EQUALIZATION_CAPABILITY 0x162c
+#define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
+#define CCS_R_DPHY_PREAMBLE_CAPABILITY 0x162d
+#define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL BIT(0)
+#define CCS_R_DPHY_SSC_CAPABILITY 0x162e
+#define CCS_DPHY_SSC_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_R_CPHY_CALIBRATION_CAPABILITY 0x162f
+#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL BIT(2)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL BIT(3)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL BIT(4)
+#define CCS_R_DPHY_CALIBRATION_CAPABILITY 0x1630
+#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
+#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
+#define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ BIT(2)
+#define CCS_R_PHY_CTRL_CAPABILITY_2 0x1631
+#define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CDPHY BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_DPHY BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY BIT(6)
+#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY BIT(7)
+#define CCS_R_LRTE_CPHY_CAPABILITY 0x1632
+#define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT BIT(0)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT BIT(1)
+#define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG BIT(2)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG BIT(3)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ BIT(4)
+#define CCS_R_LRTE_DPHY_CAPABILITY 0x1633
+#define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 BIT(0)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1 BIT(1)
+#define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1 BIT(2)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT1 BIT(3)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT2 BIT(4)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2 BIT(5)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1 BIT(6)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2 BIT(7)
+#define CCS_R_ALPS_CAPABILITY_DPHY 0x1634
+#define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED 0U
+#define CCS_ALPS_CAPABILITY_DPHY_LVLP_SUPPORTED 1U
+#define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP 2U
+#define CCS_R_ALPS_CAPABILITY_CPHY 0x1635
+#define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED 0U
+#define CCS_ALPS_CAPABILITY_CPHY_LVLP_SUPPORTED 1U
+#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP 2U
+#define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED 0xc
+#define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED 0xd
+#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP 0xe
+#define CCS_R_SCRAMBLING_CAPABILITY 0x1636
+#define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED BIT(0)
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_SHIFT 1U
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK 0x6
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_1 0U
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_4 3U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_SHIFT 3U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_MASK 0x38
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_0 0U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_1 1U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_4 4U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE BIT(6)
+#define CCS_R_DPHY_MANUAL_CONSTANT 0x1637
+#define CCS_R_CPHY_MANUAL_CONSTANT 0x1638
+#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC 0x1639
+#define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 BIT(0)
+#define CCS_R_PHY_CTRL_CAPABILITY_3 0x165c
+#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1 BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_3_TINIT_SUPPORTED BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1 BIT(6)
+#define CCS_R_DPHY_SF 0x165d
+#define CCS_R_CPHY_SF 0x165e
+#define CCS_CPHY_SF_TWAKEUP_SHIFT 0U
+#define CCS_CPHY_SF_TWAKEUP_MASK 0xf
+#define CCS_CPHY_SF_TINIT_SHIFT 4U
+#define CCS_CPHY_SF_TINIT_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_1 0x165f
+#define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT 0U
+#define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK 0xf
+#define CCS_DPHY_LIMITS_1_THS_ZERO_SHIFT 4U
+#define CCS_DPHY_LIMITS_1_THS_ZERO_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_2 0x1660
+#define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT 0U
+#define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK 0xf
+#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_SHIFT 4U
+#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_3 0x1661
+#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT 0U
+#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK 0xf
+#define CCS_DPHY_LIMITS_3_TCLK_ZERO_SHIFT 4U
+#define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_4 0x1662
+#define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT 0U
+#define CCS_DPHY_LIMITS_4_TCLK_POST_MASK 0xf
+#define CCS_DPHY_LIMITS_4_TLPX_SHIFT 4U
+#define CCS_DPHY_LIMITS_4_TLPX_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_5 0x1663
+#define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT 0U
+#define CCS_DPHY_LIMITS_5_THS_EXIT_MASK 0xf
+#define CCS_DPHY_LIMITS_5_TWAKEUP_SHIFT 4U
+#define CCS_DPHY_LIMITS_5_TWAKEUP_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_6 0x1664
+#define CCS_DPHY_LIMITS_6_TINIT_SHIFT 0U
+#define CCS_DPHY_LIMITS_6_TINIT_MASK 0xf
+#define CCS_R_CPHY_LIMITS_1 0x1665
+#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK 0xf
+#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_SHIFT 4U
+#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK 0xf0
+#define CCS_R_CPHY_LIMITS_2 0x1666
+#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK 0xf
+#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_SHIFT 4U
+#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK 0xf0
+#define CCS_R_CPHY_LIMITS_3 0x1667
+#define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK 0xf
+#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT)
+#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT)
+#define CCS_R_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT)
+#define CCS_R_BINNING_CAPABILITY 0x1710
+#define CCS_BINNING_CAPABILITY_UNSUPPORTED 0U
+#define CCS_BINNING_CAPABILITY_BINNING_THEN_SUBSAMPLING 1U
+#define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING 2U
+#define CCS_R_BINNING_WEIGHTING_CAPABILITY 0x1711
+#define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED BIT(0)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED BIT(1)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED BIT(2)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
+#define CCS_R_BINNING_SUB_TYPES 0x1712
+#define CCS_R_BINNING_SUB_TYPE(n) (0x1713 + (n))
+#define CCS_LIM_BINNING_SUB_TYPE_MIN_N 0U
+#define CCS_LIM_BINNING_SUB_TYPE_MAX_N 63U
+#define CCS_BINNING_SUB_TYPE_ROW_SHIFT 0U
+#define CCS_BINNING_SUB_TYPE_ROW_MASK 0xf
+#define CCS_BINNING_SUB_TYPE_COLUMN_SHIFT 4U
+#define CCS_BINNING_SUB_TYPE_COLUMN_MASK 0xf0
+#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY 0x1771
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED BIT(0)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED BIT(1)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED BIT(2)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
+#define CCS_R_BINNING_SUB_TYPES_MONO 0x1772
+#define CCS_R_BINNING_SUB_TYPE_MONO(n) (0x1773 + (n))
+#define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N 0U
+#define CCS_LIM_BINNING_SUB_TYPE_MONO_MAX_N 63U
+#define CCS_R_DATA_TRANSFER_IF_CAPABILITY 0x1800
+#define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING BIT(2)
+#define CCS_R_SHADING_CORRECTION_CAPABILITY 0x1900
+#define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING BIT(0)
+#define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION BIT(1)
+#define CCS_R_GREEN_IMBALANCE_CAPABILITY 0x1901
+#define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903
+#define CCS_R_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT BIT(0)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET BIT(2)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE BIT(5)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC BIT(8)
+#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET BIT(3)
+#define CCS_R_NF_CAPABILITY 0x1908
+#define CCS_NF_CAPABILITY_LUMA BIT(0)
+#define CCS_NF_CAPABILITY_CHROMA BIT(1)
+#define CCS_NF_CAPABILITY_COMBINED BIT(2)
+#define CCS_R_OB_READOUT_CAPABILITY 0x1980
+#define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT BIT(0)
+#define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT BIT(1)
+#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT BIT(2)
+#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT BIT(3)
+#define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT BIT(4)
+#define CCS_R_COLOR_FEEDBACK_CAPABILITY 0x1987
+#define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN BIT(0)
+#define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN BIT(1)
+#define CCS_R_CFA_PATTERN_CAPABILITY 0x1990
+#define CCS_CFA_PATTERN_CAPABILITY_BAYER 0U
+#define CCS_CFA_PATTERN_CAPABILITY_MONOCHROME 1U
+#define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER 2U
+#define CCS_CFA_PATTERN_CAPABILITY_VENDOR_SPECIFIC 3U
+#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY 0x1991
+#define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER BIT(0)
+#define CCS_R_FLASH_MODE_CAPABILITY 0x1a02
+#define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
+#define CCS_R_SA_STROBE_MODE_CAPABILITY 0x1a03
+#define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH BIT(0)
+#define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL BIT(1)
+#define CCS_R_RESET_MAX_DELAY 0x1a10
+#define CCS_R_RESET_MIN_TIME 0x1a11
+#define CCS_R_PDAF_CAPABILITY_1 0x1b80
+#define CCS_PDAF_CAPABILITY_1_SUPPORTED BIT(0)
+#define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED BIT(1)
+#define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED BIT(2)
+#define CCS_PDAF_CAPABILITY_1_RAW_BOTTOM_EMBEDDED BIT(3)
+#define CCS_PDAF_CAPABILITY_1_RAW_INTERLEAVED BIT(4)
+#define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION BIT(5)
+#define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING BIT(6)
+#define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING BIT(7)
+#define CCS_R_PDAF_CAPABILITY_2 0x1b81
+#define CCS_PDAF_CAPABILITY_2_ROI BIT(0)
+#define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP BIT(1)
+#define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED BIT(2)
+#define CCS_R_BRACKETING_LUT_CAPABILITY_1 0x1c00
+#define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION BIT(0)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN BIT(1)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH BIT(4)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN BIT(5)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN BIT(6)
+#define CCS_R_BRACKETING_LUT_CAPABILITY_2 0x1c01
+#define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE BIT(0)
+#define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE BIT(1)
+#define CCS_R_BRACKETING_LUT_SIZE 0x1c02
+
+#endif /* __CCS_REGS_H__ */
diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/ccs/ccs.h
index 6f469934f9e3..356b87c33405 100644
--- a/drivers/media/i2c/smiapp/smiapp.h
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -1,24 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp/smiapp.h
+ * drivers/media/i2c/smiapp/ccs.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2010--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
*/
-#ifndef __SMIAPP_PRIV_H_
-#define __SMIAPP_PRIV_H_
+#ifndef __CCS_H__
+#define __CCS_H__
#include <linux/mutex.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
-#include "smiapp-pll.h"
-#include "smiapp-reg.h"
-#include "smiapp-regs.h"
-#include "smiapp-quirk.h"
+#include "ccs-data.h"
+#include "ccs-limits.h"
+#include "ccs-quirk.h"
+#include "ccs-regs.h"
+#include "ccs-reg-access.h"
+#include "../ccs-pll.h"
+#include "smiapp-reg-defs.h"
/*
* Standard SMIA++ constants
@@ -39,12 +43,19 @@
(1000 + (SMIAPP_RESET_DELAY_CLOCKS * 1000 \
+ (clk) / 1000 - 1) / ((clk) / 1000))
-#define SMIAPP_COLOUR_COMPONENTS 4
+#define CCS_COLOUR_COMPONENTS 4
-#define SMIAPP_NAME "smiapp"
+#define SMIAPP_NAME "smiapp"
+#define CCS_NAME "ccs"
-#define SMIAPP_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
-#define SMIAPP_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
+#define CCS_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
+#define CCS_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
+
+#define CCS_LIM(sensor, limit) \
+ ccs_get_limit(sensor, CCS_L_##limit, 0)
+
+#define CCS_LIM_AT(sensor, limit, offset) \
+ ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
/*
* Sometimes due to board layout considerations the camera module can be
@@ -52,12 +63,12 @@
* corrected by giving a default H-FLIP and V-FLIP in the sensor readout.
* FIXME: rotation also changes the bayer pattern.
*/
-enum smiapp_module_board_orient {
- SMIAPP_MODULE_BOARD_ORIENT_0 = 0,
- SMIAPP_MODULE_BOARD_ORIENT_180,
+enum ccs_module_board_orient {
+ CCS_MODULE_BOARD_ORIENT_0 = 0,
+ CCS_MODULE_BOARD_ORIENT_180,
};
-struct smiapp_flash_strobe_parms {
+struct ccs_flash_strobe_parms {
u8 mode;
u32 strobe_width_high_us;
u16 strobe_delay;
@@ -65,7 +76,7 @@ struct smiapp_flash_strobe_parms {
u8 trigger;
};
-struct smiapp_hwconfig {
+struct ccs_hwconfig {
/*
* Change the cci address if i2c_addr_alt is set.
* Both default and alternate cci addr need to be present
@@ -76,136 +87,128 @@ struct smiapp_hwconfig {
uint32_t ext_clk; /* sensor external clk */
unsigned int lanes; /* Number of CSI-2 lanes */
- uint32_t csi_signalling_mode; /* SMIAPP_CSI_SIGNALLING_MODE_* */
+ uint32_t csi_signalling_mode; /* CCS_CSI_SIGNALLING_MODE_* */
uint64_t *op_sys_clock;
- enum smiapp_module_board_orient module_board_orient;
+ enum ccs_module_board_orient module_board_orient;
- struct smiapp_flash_strobe_parms *strobe_setup;
+ struct ccs_flash_strobe_parms *strobe_setup;
};
-#include "smiapp-limits.h"
+struct ccs_quirk;
-struct smiapp_quirk;
+#define CCS_MODULE_IDENT_FLAG_REV_LE (1 << 0)
-#define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
-
-struct smiapp_module_ident {
- u8 manufacturer_id;
+struct ccs_module_ident {
+ u16 mipi_manufacturer_id;
u16 model_id;
+ u8 smia_manufacturer_id;
u8 revision_number_major;
u8 flags;
char *name;
- const struct smiapp_quirk *quirk;
+ const struct ccs_quirk *quirk;
};
-struct smiapp_module_info {
- u32 manufacturer_id;
+struct ccs_module_info {
+ u32 smia_manufacturer_id;
+ u32 mipi_manufacturer_id;
u32 model_id;
- u32 revision_number_major;
- u32 revision_number_minor;
+ u32 revision_number;
u32 module_year;
u32 module_month;
u32 module_day;
- u32 sensor_manufacturer_id;
+ u32 sensor_smia_manufacturer_id;
+ u32 sensor_mipi_manufacturer_id;
u32 sensor_model_id;
u32 sensor_revision_number;
u32 sensor_firmware_version;
u32 smia_version;
u32 smiapp_version;
-
- u32 smiapp_profile;
+ u32 ccs_version;
char *name;
- const struct smiapp_quirk *quirk;
+ const struct ccs_quirk *quirk;
};
-#define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+#define CCS_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = fl, \
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+#define CCS_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
- .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
+ .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \
- { .manufacturer_id = manufacturer, \
+#define CCS_IDENT_L(manufacturer, model, rev, _name) \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
- .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
+ .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \
.name = _name, }
-#define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
- { .manufacturer_id = manufacturer, \
+#define CCS_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = 0, \
.name = _name, \
.quirk = _quirk, }
-#define SMIAPP_IDENT(manufacturer, model, rev, _name) \
- { .manufacturer_id = manufacturer, \
+#define CCS_IDENT(manufacturer, model, rev, _name) \
+ { .smia_manufacturer_id = manufacturer, \
.model_id = model, \
.revision_number_major = rev, \
.flags = 0, \
.name = _name, }
-struct smiapp_reg_limits {
- u32 addr;
- char *what;
-};
-
-extern struct smiapp_reg_limits smiapp_reg_limits[];
-
-struct smiapp_csi_data_format {
+struct ccs_csi_data_format {
u32 code;
u8 width;
u8 compressed;
u8 pixel_order;
};
-#define SMIAPP_SUBDEVS 3
+#define CCS_SUBDEVS 3
-#define SMIAPP_PA_PAD_SRC 0
-#define SMIAPP_PAD_SINK 0
-#define SMIAPP_PAD_SRC 1
-#define SMIAPP_PADS 2
+#define CCS_PA_PAD_SRC 0
+#define CCS_PAD_SINK 0
+#define CCS_PAD_SRC 1
+#define CCS_PADS 2
-struct smiapp_binning_subtype {
+struct ccs_binning_subtype {
u8 horizontal:4;
u8 vertical:4;
} __packed;
-struct smiapp_subdev {
+struct ccs_subdev {
struct v4l2_subdev sd;
- struct media_pad pads[SMIAPP_PADS];
+ struct media_pad pads[CCS_PADS];
struct v4l2_rect sink_fmt;
- struct v4l2_rect crop[SMIAPP_PADS];
+ struct v4l2_rect crop[CCS_PADS];
struct v4l2_rect compose; /* compose on sink */
unsigned short sink_pad;
unsigned short source_pad;
int npads;
- struct smiapp_sensor *sensor;
+ struct ccs_sensor *sensor;
struct v4l2_ctrl_handler ctrl_handler;
};
/*
- * struct smiapp_sensor - Main device structure
+ * struct ccs_sensor - Main device structure
*/
-struct smiapp_sensor {
+struct ccs_sensor {
/*
* "mutex" is used to serialise access to all fields here
* except v4l2_ctrls at the end of the struct. "mutex" is also
@@ -213,24 +216,26 @@ struct smiapp_sensor {
* information.
*/
struct mutex mutex;
- struct smiapp_subdev ssds[SMIAPP_SUBDEVS];
+ struct ccs_subdev ssds[CCS_SUBDEVS];
u32 ssds_used;
- struct smiapp_subdev *src;
- struct smiapp_subdev *binner;
- struct smiapp_subdev *scaler;
- struct smiapp_subdev *pixel_array;
- struct smiapp_hwconfig *hwcfg;
- struct regulator *vana;
+ struct ccs_subdev *src;
+ struct ccs_subdev *binner;
+ struct ccs_subdev *scaler;
+ struct ccs_subdev *pixel_array;
+ struct ccs_hwconfig hwcfg;
+ struct regulator_bulk_data *regulators;
struct clk *ext_clk;
struct gpio_desc *xshutdown;
- u32 limits[SMIAPP_LIMIT_LAST];
+ struct gpio_desc *reset;
+ void *ccs_limits;
u8 nbinning_subtypes;
- struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
+ struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
u32 mbus_frame_fmts;
- const struct smiapp_csi_data_format *csi_format;
- const struct smiapp_csi_data_format *internal_csi_format;
+ const struct ccs_csi_data_format *csi_format;
+ const struct ccs_csi_data_format *internal_csi_format;
u32 default_mbus_frame_fmts;
int default_pixel_order;
+ struct ccs_data_container sdata, mdata;
u8 binning_horizontal;
u8 binning_vertical;
@@ -249,9 +254,9 @@ struct smiapp_sensor {
bool dev_init_done;
u8 compressed_min_bpp;
- struct smiapp_module_info minfo;
+ struct ccs_module_info minfo;
- struct smiapp_pll pll;
+ struct ccs_pll pll;
/* Is a default format supported for a given BPP? */
unsigned long *valid_link_freqs;
@@ -268,13 +273,18 @@ struct smiapp_sensor {
struct v4l2_ctrl *link_freq;
struct v4l2_ctrl *pixel_rate_csi;
/* test pattern colour components */
- struct v4l2_ctrl *test_data[SMIAPP_COLOUR_COMPONENTS];
+ struct v4l2_ctrl *test_data[CCS_COLOUR_COMPONENTS];
};
-#define to_smiapp_subdev(_sd) \
- container_of(_sd, struct smiapp_subdev, sd)
+#define to_ccs_subdev(_sd) \
+ container_of(_sd, struct ccs_subdev, sd)
+
+#define to_ccs_sensor(_sd) \
+ (to_ccs_subdev(_sd)->sensor)
-#define to_smiapp_sensor(_sd) \
- (to_smiapp_subdev(_sd)->sensor)
+void ccs_replace_limit(struct ccs_sensor *sensor,
+ unsigned int limit, unsigned int offset, u32 val);
+u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,
+ unsigned int offset);
-#endif /* __SMIAPP_PRIV_H_ */
+#endif /* __CCS_H__ */
diff --git a/drivers/media/i2c/ccs/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h
new file mode 100644
index 000000000000..e80c110ebf3a
--- /dev/null
+++ b/drivers/media/i2c/ccs/smiapp-reg-defs.h
@@ -0,0 +1,580 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * drivers/media/i2c/smiapp/smiapp-reg-defs.h
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ */
+
+#ifndef __SMIAPP_REG_DEFS_H__
+#define __SMIAPP_REG_DEFS_H__
+
+/* Register addresses */
+#define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002
+#define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003
+#define SMIAPP_REG_U8_SMIA_VERSION 0x0004
+#define SMIAPP_REG_U8_FRAME_COUNT 0x0005
+#define SMIAPP_REG_U8_PIXEL_ORDER 0x0006
+#define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c
+#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010
+#define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011
+#define SMIAPP_REG_U8_MODULE_DATE_YEAR 0x0012
+#define SMIAPP_REG_U8_MODULE_DATE_MONTH 0x0013
+#define SMIAPP_REG_U8_MODULE_DATE_DAY 0x0014
+#define SMIAPP_REG_U8_MODULE_DATE_PHASE 0x0015
+#define SMIAPP_REG_U16_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER 0x0018
+#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID 0x0019
+#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION 0x001a
+#define SMIAPP_REG_U32_SERIAL_NUMBER (0x001c | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE 0x0040
+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
+#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) ((0x0042 + ((n) << 1)) | CCS_FL_16BIT) /* 0 <= n <= 14 */
+#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 + ((n) << 2)) | CCS_FL_32BIT) /* 0 <= n <= 7 */
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE (0x008a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 (0x008c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 (0x008e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 (0x0090 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 (0x0092 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE 0x00c0
+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE 0x00c1
+#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 + ((n) << 1)) | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MODE_SELECT 0x0100
+#define SMIAPP_REG_U8_IMAGE_ORIENTATION 0x0101
+#define SMIAPP_REG_U8_SOFTWARE_RESET 0x0103
+#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD 0x0104
+#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES 0x0105
+#define SMIAPP_REG_U8_FAST_STANDBY_CTRL 0x0106
+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL 0x0107
+#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL 0x0108
+#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL 0x0109
+#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER 0x0110
+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE 0x0111
+#define SMIAPP_REG_U16_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_CSI_LANE_MODE 0x0114
+#define SMIAPP_REG_U8_CSI2_10_TO_8_DT 0x0115
+#define SMIAPP_REG_U8_CSI2_10_TO_7_DT 0x0116
+#define SMIAPP_REG_U8_CSI2_10_TO_6_DT 0x0117
+#define SMIAPP_REG_U8_CSI2_12_TO_8_DT 0x0118
+#define SMIAPP_REG_U8_CSI2_12_TO_7_DT 0x0119
+#define SMIAPP_REG_U8_CSI2_12_TO_6_DT 0x011a
+#define SMIAPP_REG_U8_CSI2_14_TO_10_DT 0x011b
+#define SMIAPP_REG_U8_CSI2_14_TO_8_DT 0x011c
+#define SMIAPP_REG_U8_CSI2_16_TO_10_DT 0x011d
+#define SMIAPP_REG_U8_CSI2_16_TO_8_DT 0x011e
+#define SMIAPP_REG_U8_GAIN_MODE 0x0120
+#define SMIAPP_REG_U16_VANA_VOLTAGE (0x0130 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VDIG_VOLTAGE (0x0132 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VIO_VOLTAGE (0x0134 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ (0x0136 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL 0x0138
+#define SMIAPP_REG_U8_TEMP_SENSOR_MODE 0x0139
+#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT 0x013a
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR (0x0206 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED (0x0208 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE (0x020a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB (0x020c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR (0x020e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_RED (0x0210 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE (0x0212 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB (0x0214 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_START (0x0344 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_START (0x0346 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_END (0x0348 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_END (0x034a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_EVEN_INC (0x0380 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ODD_INC (0x0382 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_EVEN_INC (0x0384 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ODD_INC (0x0386 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALING_MODE (0x0400 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SPATIAL_SAMPLING (0x0402 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALE_M (0x0404 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALE_N (0x0406 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_RED (0x0602 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH (0x060a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION (0x060c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH (0x060e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION (0x0610 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS (0x0700 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TCLK_POST 0x0800
+#define SMIAPP_REG_U8_THS_PREPARE 0x0801
+#define SMIAPP_REG_U8_THS_ZERO_MIN 0x0802
+#define SMIAPP_REG_U8_THS_TRAIL 0x0803
+#define SMIAPP_REG_U8_TCLK_TRAIL_MIN 0x0804
+#define SMIAPP_REG_U8_TCLK_PREPARE 0x0805
+#define SMIAPP_REG_U8_TCLK_ZERO 0x0806
+#define SMIAPP_REG_U8_TLPX 0x0807
+#define SMIAPP_REG_U8_DPHY_CTRL 0x0808
+#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS (0x0820 | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_BINNING_MODE 0x0900
+#define SMIAPP_REG_U8_BINNING_TYPE 0x0901
+#define SMIAPP_REG_U8_BINNING_WEIGHTING 0x0902
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL 0x0a00
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS 0x0a01
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 0x0a04
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 0x0a05
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 0x0a06
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 0x0a07
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 0x0a08
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 0x0a09
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 0x0a10
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 0x0a11
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 0x0a12
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 0x0a13
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 0x0a14
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 0x0a15
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 0x0a16
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 0x0a17
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 0x0a18
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 0x0a19
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 0x0a1a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 0x0a1b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 0x0a1c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 0x0a1d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 0x0a1e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 0x0a1f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 0x0a20
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 0x0a21
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 0x0a22
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 0x0a23
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 0x0a24
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 0x0a25
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 0x0a26
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 0x0a27
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 0x0a28
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 0x0a29
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 0x0a2a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 0x0a2b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 0x0a2c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 0x0a2d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 0x0a2e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 0x0a2f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 0x0a30
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 0x0a31
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 0x0a32
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 0x0a33
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 0x0a34
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 0x0a35
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 0x0a36
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 0x0a37
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 0x0a38
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 0x0a39
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 0x0a3a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 0x0a3b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 0x0a3c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 0x0a3d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 0x0a3e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 0x0a3f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 0x0a40
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 0x0a41
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 0x0a42
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 0x0a43
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL 0x0a44
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS 0x0a45
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT 0x0a46
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 0x0a48
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 0x0a49
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 0x0a4a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 0x0a4b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 0x0a4c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 0x0a4d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 0x0a4e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 0x0a4f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 0x0a50
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 0x0a51
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 0x0a52
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 0x0a53
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 0x0a54
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 0x0a55
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 0x0a56
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 0x0a57
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 0x0a58
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 0x0a59
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 0x0a5a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 0x0a5b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 0x0a5c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 0x0a5d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 0x0a5e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 0x0a5f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 0x0a60
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 0x0a61
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 0x0a62
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 0x0a63
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 0x0a64
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 0x0a65
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 0x0a66
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 0x0a67
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 0x0a68
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 0x0a69
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 0x0a6a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 0x0a6b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 0x0a6c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 0x0a6d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 0x0a6e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 0x0a6f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 0x0a70
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 0x0a71
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 0x0a72
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 0x0a73
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 0x0a74
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 0x0a75
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 0x0a76
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 0x0a77
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 0x0a78
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 0x0a79
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 0x0a7a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 0x0a7b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 0x0a7c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 0x0a7d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 0x0a7e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 0x0a7f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 0x0a80
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 0x0a81
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 0x0a82
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 0x0a83
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 0x0a84
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 0x0a85
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 0x0a86
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 0x0a87
+#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE 0x0b00
+#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL 0x0b01
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE 0x0b02
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT 0x0b03
+#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE 0x0b04
+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE 0x0b05
+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE 0x0b06
+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT 0x0b07
+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE 0x0b08
+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT 0x0b09
+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE 0x0b0a
+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT 0x0b0b
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE 0x0b0c
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT 0x0b0d
+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE 0x0b0e
+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST 0x0b0f
+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST 0x0b10
+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b11
+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b12
+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b13
+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b14
+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE 0x0b15
+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST 0x0b16
+#define SMIAPP_REG_U8_EDOF_MODE 0x0b80
+#define SMIAPP_REG_U8_SHARPNESS 0x0b83
+#define SMIAPP_REG_U8_DENOISING 0x0b84
+#define SMIAPP_REG_U8_MODULE_SPECIFIC 0x0b85
+#define SMIAPP_REG_U16_DEPTH_OF_FIELD (0x0b86 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_DISTANCE (0x0b88 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL 0x0b8a
+#define SMIAPP_REG_U16_COLOUR_TEMPERATURE (0x0b8c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE 0x0bc0
+#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING (0x0bc2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START (0x0bc4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START (0x0bc6 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH (0x0bc8 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT (0x0bca | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 0x0c00
+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 0x0c01
+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 0x0c02
+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 0x0c03
+#define SMIAPP_REG_U16_TRDY_CTRL (0x0c04 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TRDOUT_CTRL (0x0c06 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL (0x0c08 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL (0x0c0a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL (0x0c0c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL (0x0c0e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL (0x0c10 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT 0x0c12
+#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_MODE_RS 0x0c1a
+#define SMIAPP_REG_U8_FLASH_TRIGGER_RS 0x0c1b
+#define SMIAPP_REG_U8_FLASH_STATUS 0x0c1c
+#define SMIAPP_REG_U8_SA_STROBE_MODE 0x0c1d
+#define SMIAPP_REG_U16_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_SA_STROBE_TRIGGER 0x0c24
+#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS 0x0c25
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL (0x0c26 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL (0x0c28 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL 0x0c2a
+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL 0x0c2b
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL (0x0c2c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL (0x0c2e | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_LOW_LEVEL_CTRL 0x0c80
+#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT (0x0c82 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 (0x0c84 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT 0x0c86
+#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 (0x0c88 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT 0x0c8a
+#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 (0x0c8c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT 0x0c8e
+#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL 0x0d00
+#define SMIAPP_REG_U8_OPERATION_MODE 0x0d01
+#define SMIAPP_REG_U8_ACT_STATE1 0x0d02
+#define SMIAPP_REG_U8_ACT_STATE2 0x0d03
+#define SMIAPP_REG_U16_FOCUS_CHANGE (0x0d80 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL (0x0d82 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 (0x0d84 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 (0x0d86 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 0x0d88
+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 0x0d89
+#define SMIAPP_REG_U8_POSITION 0x0d8a
+#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL 0x0e00
+#define SMIAPP_REG_U8_BRACKETING_LUT_MODE 0x0e01
+#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL 0x0e02
+#define SMIAPP_REG_U8_LUT_PARAMETERS_START 0x0e10
+#define SMIAPP_REG_U8_LUT_PARAMETERS_END 0x0eff
+#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY (0x1080 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ (0x1100 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ (0x1104 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ (0x110c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ (0x1110 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ (0x1118 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ (0x111c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ (0x1124 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ (0x1128 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ (0x112c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ (0x1130 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c
+#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ (0x1164 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ (0x1168 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ (0x1170 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ (0x1174 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_X_ADDR_MIN (0x1180 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_MAX (0x1184 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_EVEN_INC (0x11c2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_ODD_INC (0x11c4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_M_MIN (0x1204 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_M_MAX (0x1206 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_N_MIN (0x1208 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_N_MAX (0x120a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY (0x120c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY 0x120e
+#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY (0x1300 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED (0x1400 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED (0x1402 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED (0x1404 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN (0x1406 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN (0x1408 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN (0x140a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE (0x140c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE (0x140e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE (0x1410 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS (0x1500 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY 0x1502
+#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY 0x1600
+#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY 0x1601
+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY 0x1602
+#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY 0x1603
+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY 0x1604
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS (0x1608 | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS (0x160c | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS (0x1610 | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS (0x1614 | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY 0x1618
+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_BINNING_CAPABILITY 0x1710
+#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY 0x1711
+#define SMIAPP_REG_U8_BINNING_SUBTYPES 0x1712
+#define SMIAPP_REG_U8_BINNING_TYPE_n(n) (0x1713 + (n)) /* 1 <= n <= 237 */
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY 0x1800
+#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY 0x1900
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY 0x1901
+#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY 0x1902
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903
+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_EDOF_CAPABILITY 0x1980
+#define SMIAPP_REG_U8_ESTIMATION_FRAMES 0x1981
+#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ 0x1982
+#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ 0x1983
+#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ 0x1984
+#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ 0x1985
+#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ 0x1986
+#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY 0x1987
+#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM 0x1988
+#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY 0x19c0
+#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY 0x19c1
+#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD (0x19c2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE (0x19c4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN (0x1a00 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY 0x1a02
+#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR (0x1b02 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY 0x1b04
+#define SMIAPP_REG_U16_ACTUATOR_TYPE (0x1b40 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS 0x1b42
+#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS (0x1b44 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 0x1c00
+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 0x1c01
+#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE 0x1c02
+
+/* Register bit definitions */
+#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0)
+#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1)
+
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1)
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3)
+
+#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2)
+
+#define SMIAPP_SOFTWARE_RESET BIT(0)
+
+#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
+#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1)
+
+#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0
+#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1
+#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2
+
+#define SMIAPP_DPHY_CTRL_AUTOMATIC 0
+/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */
+#define SMIAPP_DPHY_CTRL_UI 1
+#define SMIAPP_DPHY_CTRL_REGISTER 2
+
+#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1
+#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2
+
+#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0
+#define SMIAPP_MODE_SELECT_STREAMING 1
+
+#define SMIAPP_SCALING_MODE_NONE 0
+#define SMIAPP_SCALING_MODE_HORIZONTAL 1
+#define SMIAPP_SCALING_MODE_BOTH 2
+
+#define SMIAPP_SCALING_CAPABILITY_NONE 0
+#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1
+#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */
+
+/* digital crop right before scaler */
+#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0
+#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1
+
+#define SMIAPP_BINNING_CAPABILITY_NO 0
+#define SMIAPP_BINNING_CAPABILITY_YES 1
+
+/* Maximum number of binning subtypes */
+#define SMIAPP_BINNING_SUBTYPES 253
+
+#define SMIAPP_PIXEL_ORDER_GRBG 0
+#define SMIAPP_PIXEL_ORDER_RGGB 1
+#define SMIAPP_PIXEL_ORDER_BGGR 2
+#define SMIAPP_PIXEL_ORDER_GBRG 3
+
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16
+
+#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01
+#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4
+
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff
+
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff
+
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5
+
+#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0
+#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1
+
+/* Scaling N factor */
+#define SMIAPP_SCALE_N 16
+
+#endif /* __SMIAPP_REG_DEFS_H__ */
diff --git a/drivers/media/i2c/dw9768.c b/drivers/media/i2c/dw9768.c
index 45cdd924b565..8b8cb4b077b5 100644
--- a/drivers/media/i2c/dw9768.c
+++ b/drivers/media/i2c/dw9768.c
@@ -315,8 +315,7 @@ static int dw9768_release(struct dw9768 *dw9768)
static int dw9768_runtime_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct dw9768 *dw9768 = sd_to_dw9768(sd);
dw9768_release(dw9768);
@@ -328,8 +327,7 @@ static int dw9768_runtime_suspend(struct device *dev)
static int dw9768_runtime_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct dw9768 *dw9768 = sd_to_dw9768(sd);
int ret;
diff --git a/drivers/media/i2c/et8ek8/et8ek8_driver.c b/drivers/media/i2c/et8ek8/et8ek8_driver.c
index 256acf73d5ea..122af761c8e3 100644
--- a/drivers/media/i2c/et8ek8/et8ek8_driver.c
+++ b/drivers/media/i2c/et8ek8/et8ek8_driver.c
@@ -1237,7 +1237,7 @@ static ssize_t
et8ek8_priv_mem_read(struct device *dev, struct device_attribute *attr,
char *buf)
{
- struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
struct et8ek8_sensor *sensor = to_et8ek8_sensor(subdev);
#if PAGE_SIZE < ET8EK8_PRIV_MEM_SIZE
@@ -1374,8 +1374,7 @@ static const struct v4l2_subdev_internal_ops et8ek8_internal_ops = {
*/
static int __maybe_unused et8ek8_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
struct et8ek8_sensor *sensor = to_et8ek8_sensor(subdev);
if (!sensor->power_count)
@@ -1386,8 +1385,7 @@ static int __maybe_unused et8ek8_suspend(struct device *dev)
static int __maybe_unused et8ek8_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
struct et8ek8_sensor *sensor = to_et8ek8_sensor(subdev);
if (!sensor->power_count)
diff --git a/drivers/media/i2c/hi556.c b/drivers/media/i2c/hi556.c
index c66cd1446c0f..c74736845d7a 100644
--- a/drivers/media/i2c/hi556.c
+++ b/drivers/media/i2c/hi556.c
@@ -839,8 +839,7 @@ static int hi556_set_stream(struct v4l2_subdev *sd, int enable)
static int __maybe_unused hi556_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct hi556 *hi556 = to_hi556(sd);
mutex_lock(&hi556->mutex);
@@ -854,8 +853,7 @@ static int __maybe_unused hi556_suspend(struct device *dev)
static int __maybe_unused hi556_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct hi556 *hi556 = to_hi556(sd);
int ret;
diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c
index 1ef5af9a8c8b..cee1a4817af9 100644
--- a/drivers/media/i2c/imx214.c
+++ b/drivers/media/i2c/imx214.c
@@ -786,7 +786,7 @@ static int imx214_s_stream(struct v4l2_subdev *subdev, int enable)
if (ret < 0)
goto err_rpm_put;
} else {
- ret = imx214_start_streaming(imx214);
+ ret = imx214_stop_streaming(imx214);
if (ret < 0)
goto err_rpm_put;
pm_runtime_put(imx214->dev);
diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index 1cee45e35355..e7791a0848b3 100644
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -262,8 +262,6 @@ static const struct imx219_reg mode_1920_1080_regs[] = {
{0x4793, 0x10},
{0x4797, 0x0e},
{0x479b, 0x0e},
- {0x0162, 0x0d},
- {0x0163, 0x78},
};
static const struct imx219_reg mode_1640_1232_regs[] = {
@@ -473,8 +471,8 @@ static const struct imx219_mode supported_modes[] = {
.width = 3280,
.height = 2464,
.crop = {
- .left = 0,
- .top = 0,
+ .left = IMX219_PIXEL_ARRAY_LEFT,
+ .top = IMX219_PIXEL_ARRAY_TOP,
.width = 3280,
.height = 2464
},
@@ -489,8 +487,8 @@ static const struct imx219_mode supported_modes[] = {
.width = 1920,
.height = 1080,
.crop = {
- .left = 680,
- .top = 692,
+ .left = 688,
+ .top = 700,
.width = 1920,
.height = 1080
},
@@ -505,8 +503,8 @@ static const struct imx219_mode supported_modes[] = {
.width = 1640,
.height = 1232,
.crop = {
- .left = 0,
- .top = 0,
+ .left = IMX219_PIXEL_ARRAY_LEFT,
+ .top = IMX219_PIXEL_ARRAY_TOP,
.width = 3280,
.height = 2464
},
@@ -521,8 +519,8 @@ static const struct imx219_mode supported_modes[] = {
.width = 640,
.height = 480,
.crop = {
- .left = 1000,
- .top = 752,
+ .left = 1008,
+ .top = 760,
.width = 1280,
.height = 960
},
@@ -1008,6 +1006,7 @@ static int imx219_get_selection(struct v4l2_subdev *sd,
return 0;
case V4L2_SEL_TGT_CROP_DEFAULT:
+ case V4L2_SEL_TGT_CROP_BOUNDS:
sel->r.top = IMX219_PIXEL_ARRAY_TOP;
sel->r.left = IMX219_PIXEL_ARRAY_LEFT;
sel->r.width = IMX219_PIXEL_ARRAY_WIDTH;
@@ -1114,22 +1113,21 @@ err_unlock:
/* Power/clock management functions */
static int imx219_power_on(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx219 *imx219 = to_imx219(sd);
int ret;
ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
imx219->supplies);
if (ret) {
- dev_err(&client->dev, "%s: failed to enable regulators\n",
+ dev_err(dev, "%s: failed to enable regulators\n",
__func__);
return ret;
}
ret = clk_prepare_enable(imx219->xclk);
if (ret) {
- dev_err(&client->dev, "%s: failed to enable clock\n",
+ dev_err(dev, "%s: failed to enable clock\n",
__func__);
goto reg_off;
}
@@ -1148,8 +1146,7 @@ reg_off:
static int imx219_power_off(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx219 *imx219 = to_imx219(sd);
gpiod_set_value_cansleep(imx219->reset_gpio, 0);
@@ -1161,8 +1158,7 @@ static int imx219_power_off(struct device *dev)
static int __maybe_unused imx219_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx219 *imx219 = to_imx219(sd);
if (imx219->streaming)
@@ -1173,8 +1169,7 @@ static int __maybe_unused imx219_suspend(struct device *dev)
static int __maybe_unused imx219_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx219 *imx219 = to_imx219(sd);
int ret;
@@ -1498,7 +1493,8 @@ static int imx219_probe(struct i2c_client *client)
/* Initialize subdev */
imx219->sd.internal_ops = &imx219_internal_ops;
- imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
+ V4L2_SUBDEV_FL_HAS_EVENTS;
imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
/* Initialize source pad */
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c
index ccb55fd1d506..df62c69a48c0 100644
--- a/drivers/media/i2c/imx258.c
+++ b/drivers/media/i2c/imx258.c
@@ -1305,6 +1305,6 @@ module_i2c_driver(imx258_i2c_driver);
MODULE_AUTHOR("Yeh, Andy <andy.yeh@intel.com>");
MODULE_AUTHOR("Chiang, Alan");
-MODULE_AUTHOR("Chen, Jason <jasonx.z.chen@intel.com>");
+MODULE_AUTHOR("Chen, Jason");
MODULE_DESCRIPTION("Sony IMX258 sensor driver");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/imx274.c b/drivers/media/i2c/imx274.c
index e6aa9f32b6a8..54642d5f2d5b 100644
--- a/drivers/media/i2c/imx274.c
+++ b/drivers/media/i2c/imx274.c
@@ -18,7 +18,9 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/v4l2-mediabus.h>
#include <linux/videodev2.h>
@@ -65,7 +67,6 @@
*/
#define IMX274_MIN_EXPOSURE_TIME (4 * 260 / 72)
-#define IMX274_DEFAULT_BINNING IMX274_BINNING_OFF
#define IMX274_MAX_WIDTH (3840)
#define IMX274_MAX_HEIGHT (2160)
#define IMX274_MAX_FRAME_RATE (120)
@@ -131,6 +132,15 @@
#define IMX274_TABLE_WAIT_MS 0
#define IMX274_TABLE_END 1
+/* regulator supplies */
+static const char * const imx274_supply_names[] = {
+ "vddl", /* IF (1.2V) supply */
+ "vdig", /* Digital Core (1.8V) supply */
+ "vana", /* Analog (2.8V) supply */
+};
+
+#define IMX274_NUM_SUPPLIES ARRAY_SIZE(imx274_supply_names)
+
/*
* imx274 I2C operation related structure
*/
@@ -145,12 +155,6 @@ static const struct regmap_config imx274_regmap_config = {
.cache_type = REGCACHE_RBTREE,
};
-enum imx274_binning {
- IMX274_BINNING_OFF,
- IMX274_BINNING_2_1,
- IMX274_BINNING_3_1,
-};
-
/*
* Parameters for each imx274 readout mode.
*
@@ -158,7 +162,8 @@ enum imx274_binning {
* implemented modes.
*
* @init_regs: registers to initialize the mode
- * @bin_ratio: downscale factor (e.g. 3 for 3:1 binning)
+ * @wbin_ratio: width downscale factor (e.g. 3 for 1280; 3 = 3840/1280)
+ * @hbin_ratio: height downscale factor (e.g. 3 for 720; 3 = 2160/720)
* @min_frame_len: Minimum frame length for each mode (see "Frame Rate
* Adjustment (CSI-2)" in the datasheet)
* @min_SHR: Minimum SHR register value (see "Shutter Setting (CSI-2)" in the
@@ -169,7 +174,8 @@ enum imx274_binning {
*/
struct imx274_mode {
const struct reg_8 *init_regs;
- unsigned int bin_ratio;
+ u8 wbin_ratio;
+ u8 hbin_ratio;
int min_frame_len;
int min_SHR;
int max_fps;
@@ -333,6 +339,46 @@ static const struct reg_8 imx274_mode5_1280x720_raw10[] = {
};
/*
+ * Vertical 2/8 subsampling horizontal 3 binning
+ * imx274 mode6(refer to datasheet) register configuration with
+ * 1280x540 resolution, raw10 data and mipi four lane output
+ */
+static const struct reg_8 imx274_mode6_1280x540_raw10[] = {
+ {0x3004, 0x04}, /* mode setting */
+ {0x3005, 0x31},
+ {0x3006, 0x00},
+ {0x3007, 0x02}, /* mode setting */
+
+ {0x3018, 0xA2}, /* output XVS, HVS */
+
+ {0x306B, 0x05},
+ {0x30E2, 0x04}, /* mode setting */
+
+ {0x30EE, 0x01},
+ {0x3342, 0x0A},
+ {0x3343, 0x00},
+ {0x3344, 0x16},
+ {0x3345, 0x00},
+ {0x33A6, 0x01},
+ {0x3528, 0x0E},
+ {0x3554, 0x1F},
+ {0x3555, 0x01},
+ {0x3556, 0x01},
+ {0x3557, 0x01},
+ {0x3558, 0x01},
+ {0x3559, 0x00},
+ {0x355A, 0x00},
+ {0x35BA, 0x0E},
+ {0x366A, 0x1B},
+ {0x366B, 0x1A},
+ {0x366C, 0x19},
+ {0x366D, 0x17},
+ {0x3A41, 0x04},
+
+ {IMX274_TABLE_END, 0x00}
+};
+
+/*
* imx274 first step register configuration for
* starting stream
*/
@@ -445,7 +491,8 @@ static const struct reg_8 imx274_tp_regs[] = {
static const struct imx274_mode imx274_modes[] = {
{
/* mode 1, 4K */
- .bin_ratio = 1,
+ .wbin_ratio = 1, /* 3840 */
+ .hbin_ratio = 1, /* 2160 */
.init_regs = imx274_mode1_3840x2160_raw10,
.min_frame_len = 4550,
.min_SHR = 12,
@@ -454,7 +501,8 @@ static const struct imx274_mode imx274_modes[] = {
},
{
/* mode 3, 1080p */
- .bin_ratio = 2,
+ .wbin_ratio = 2, /* 1920 */
+ .hbin_ratio = 2, /* 1080 */
.init_regs = imx274_mode3_1920x1080_raw10,
.min_frame_len = 2310,
.min_SHR = 8,
@@ -463,13 +511,24 @@ static const struct imx274_mode imx274_modes[] = {
},
{
/* mode 5, 720p */
- .bin_ratio = 3,
+ .wbin_ratio = 3, /* 1280 */
+ .hbin_ratio = 3, /* 720 */
.init_regs = imx274_mode5_1280x720_raw10,
.min_frame_len = 2310,
.min_SHR = 8,
.max_fps = 120,
.nocpiop = 112,
},
+ {
+ /* mode 6, 540p */
+ .wbin_ratio = 3, /* 1280 */
+ .hbin_ratio = 4, /* 540 */
+ .init_regs = imx274_mode6_1280x540_raw10,
+ .min_frame_len = 2310,
+ .min_SHR = 4,
+ .max_fps = 120,
+ .nocpiop = 112,
+ },
};
/*
@@ -501,6 +560,8 @@ struct imx274_ctrls {
* @frame_rate: V4L2 frame rate structure
* @regmap: Pointer to regmap structure
* @reset_gpio: Pointer to reset gpio
+ * @supplies: List of analog and digital supply regulators
+ * @inck: Pointer to sensor input clock
* @lock: Mutex structure
* @mode: Parameters for the selected readout mode
*/
@@ -514,6 +575,8 @@ struct stimx274 {
struct v4l2_fract frame_interval;
struct regmap *regmap;
struct gpio_desc *reset_gpio;
+ struct regulator_bulk_data supplies[IMX274_NUM_SUPPLIES];
+ struct clk *inck;
struct mutex lock; /* mutex lock for operations */
const struct imx274_mode *mode;
};
@@ -726,6 +789,12 @@ static int imx274_start_stream(struct stimx274 *priv)
{
int err = 0;
+ err = __v4l2_ctrl_handler_setup(&priv->ctrls.handler);
+ if (err) {
+ dev_err(&priv->client->dev, "Error %d setup controls\n", err);
+ return err;
+ }
+
/*
* Refer to "Standby Cancel Sequence when using CSI-2" in
* imx274 datasheet, it should wait 10ms or more here.
@@ -767,6 +836,66 @@ static void imx274_reset(struct stimx274 *priv, int rst)
usleep_range(IMX274_RESET_DELAY1, IMX274_RESET_DELAY2);
}
+static int imx274_power_on(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct stimx274 *imx274 = to_imx274(sd);
+ int ret;
+
+ /* keep sensor in reset before power on */
+ imx274_reset(imx274, 0);
+
+ ret = clk_prepare_enable(imx274->inck);
+ if (ret) {
+ dev_err(&imx274->client->dev,
+ "Failed to enable input clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = regulator_bulk_enable(IMX274_NUM_SUPPLIES, imx274->supplies);
+ if (ret) {
+ dev_err(&imx274->client->dev,
+ "Failed to enable regulators: %d\n", ret);
+ goto fail_reg;
+ }
+
+ udelay(2);
+ imx274_reset(imx274, 1);
+
+ return 0;
+
+fail_reg:
+ clk_disable_unprepare(imx274->inck);
+ return ret;
+}
+
+static int imx274_power_off(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct stimx274 *imx274 = to_imx274(sd);
+
+ imx274_reset(imx274, 0);
+
+ regulator_bulk_disable(IMX274_NUM_SUPPLIES, imx274->supplies);
+
+ clk_disable_unprepare(imx274->inck);
+
+ return 0;
+}
+
+static int imx274_regulators_get(struct device *dev, struct stimx274 *imx274)
+{
+ unsigned int i;
+
+ for (i = 0; i < IMX274_NUM_SUPPLIES; i++)
+ imx274->supplies[i].supply = imx274_supply_names[i];
+
+ return devm_regulator_bulk_get(dev, IMX274_NUM_SUPPLIES,
+ imx274->supplies);
+}
+
/**
* imx274_s_ctrl - This is used to set the imx274 V4L2 controls
* @ctrl: V4L2 control to be set
@@ -781,6 +910,9 @@ static int imx274_s_ctrl(struct v4l2_ctrl *ctrl)
struct stimx274 *imx274 = to_imx274(sd);
int ret = -EINVAL;
+ if (!pm_runtime_get_if_in_use(&imx274->client->dev))
+ return 0;
+
dev_dbg(&imx274->client->dev,
"%s : s_ctrl: %s, value: %d\n", __func__,
ctrl->name, ctrl->val);
@@ -811,6 +943,8 @@ static int imx274_s_ctrl(struct v4l2_ctrl *ctrl)
break;
}
+ pm_runtime_put(&imx274->client->dev);
+
return ret;
}
@@ -892,12 +1026,13 @@ static int __imx274_change_compose(struct stimx274 *imx274,
}
for (i = 0; i < ARRAY_SIZE(imx274_modes); i++) {
- unsigned int ratio = imx274_modes[i].bin_ratio;
+ u8 wratio = imx274_modes[i].wbin_ratio;
+ u8 hratio = imx274_modes[i].hbin_ratio;
int goodness = imx274_binning_goodness(
imx274,
- cur_crop->width / ratio, *width,
- cur_crop->height / ratio, *height,
+ cur_crop->width / wratio, *width,
+ cur_crop->height / hratio, *height,
flags);
if (goodness >= best_goodness) {
@@ -906,14 +1041,14 @@ static int __imx274_change_compose(struct stimx274 *imx274,
}
}
- *width = cur_crop->width / best_mode->bin_ratio;
- *height = cur_crop->height / best_mode->bin_ratio;
+ *width = cur_crop->width / best_mode->wbin_ratio;
+ *height = cur_crop->height / best_mode->hbin_ratio;
if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
imx274->mode = best_mode;
- dev_dbg(dev, "%s: selected %u:1 binning\n",
- __func__, best_mode->bin_ratio);
+ dev_dbg(dev, "%s: selected %ux%u binning\n",
+ __func__, best_mode->wbin_ratio, best_mode->hbin_ratio);
tgt_fmt->width = *width;
tgt_fmt->height = *height;
@@ -1163,7 +1298,7 @@ static int imx274_apply_trimming(struct stimx274 *imx274)
(-imx274->crop.top / 2) : (imx274->crop.top / 2);
v_cut = (IMX274_MAX_HEIGHT - imx274->crop.height) / 2;
write_v_size = imx274->crop.height + 22;
- y_out_size = imx274->crop.height + 14;
+ y_out_size = imx274->crop.height;
err = imx274_write_mbreg(imx274, IMX274_HMAX_REG_LSB, hmax, 2);
if (!err)
@@ -1271,10 +1406,8 @@ unlock:
*
* Return: 0 on success, errors otherwise
*/
-static int imx274_load_default(struct stimx274 *priv)
+static void imx274_load_default(struct stimx274 *priv)
{
- int ret;
-
/* load default control values */
priv->frame_interval.numerator = 1;
priv->frame_interval.denominator = IMX274_DEF_FRAME_RATE;
@@ -1282,29 +1415,6 @@ static int imx274_load_default(struct stimx274 *priv)
priv->ctrls.gain->val = IMX274_DEF_GAIN;
priv->ctrls.vflip->val = 0;
priv->ctrls.test_pattern->val = TEST_PATTERN_DISABLED;
-
- /* update frame rate */
- ret = imx274_set_frame_interval(priv,
- priv->frame_interval);
- if (ret)
- return ret;
-
- /* update exposure time */
- ret = v4l2_ctrl_s_ctrl(priv->ctrls.exposure, priv->ctrls.exposure->val);
- if (ret)
- return ret;
-
- /* update gain */
- ret = v4l2_ctrl_s_ctrl(priv->ctrls.gain, priv->ctrls.gain->val);
- if (ret)
- return ret;
-
- /* update vflip */
- ret = v4l2_ctrl_s_ctrl(priv->ctrls.vflip, priv->ctrls.vflip->val);
- if (ret)
- return ret;
-
- return 0;
}
/**
@@ -1329,6 +1439,13 @@ static int imx274_s_stream(struct v4l2_subdev *sd, int on)
mutex_lock(&imx274->lock);
if (on) {
+ ret = pm_runtime_get_sync(&imx274->client->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&imx274->client->dev);
+ mutex_unlock(&imx274->lock);
+ return ret;
+ }
+
/* load mode registers */
ret = imx274_mode_regs(imx274);
if (ret)
@@ -1349,12 +1466,6 @@ static int imx274_s_stream(struct v4l2_subdev *sd, int on)
if (ret)
goto fail;
- /* update exposure time */
- ret = __v4l2_ctrl_s_ctrl(imx274->ctrls.exposure,
- imx274->ctrls.exposure->val);
- if (ret)
- goto fail;
-
/* start stream */
ret = imx274_start_stream(imx274);
if (ret)
@@ -1364,6 +1475,8 @@ static int imx274_s_stream(struct v4l2_subdev *sd, int on)
ret = imx274_write_table(imx274, imx274_stop);
if (ret)
goto fail;
+
+ pm_runtime_put(&imx274->client->dev);
}
mutex_unlock(&imx274->lock);
@@ -1371,6 +1484,7 @@ static int imx274_s_stream(struct v4l2_subdev *sd, int on)
return 0;
fail:
+ pm_runtime_put(&imx274->client->dev);
mutex_unlock(&imx274->lock);
dev_err(&imx274->client->dev, "s_stream failed\n");
return ret;
@@ -1836,12 +1950,23 @@ static int imx274_probe(struct i2c_client *client)
mutex_init(&imx274->lock);
+ imx274->inck = devm_clk_get_optional(&client->dev, "inck");
+ if (IS_ERR(imx274->inck))
+ return PTR_ERR(imx274->inck);
+
+ ret = imx274_regulators_get(&client->dev, imx274);
+ if (ret) {
+ dev_err(&client->dev,
+ "Failed to get power regulators, err: %d\n", ret);
+ return ret;
+ }
+
/* initialize format */
- imx274->mode = &imx274_modes[IMX274_DEFAULT_BINNING];
+ imx274->mode = &imx274_modes[0];
imx274->crop.width = IMX274_MAX_WIDTH;
imx274->crop.height = IMX274_MAX_HEIGHT;
- imx274->format.width = imx274->crop.width / imx274->mode->bin_ratio;
- imx274->format.height = imx274->crop.height / imx274->mode->bin_ratio;
+ imx274->format.width = imx274->crop.width / imx274->mode->wbin_ratio;
+ imx274->format.height = imx274->crop.height / imx274->mode->hbin_ratio;
imx274->format.field = V4L2_FIELD_NONE;
imx274->format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
imx274->format.colorspace = V4L2_COLORSPACE_SRGB;
@@ -1883,15 +2008,20 @@ static int imx274_probe(struct i2c_client *client)
goto err_me;
}
- /* pull sensor out of reset */
- imx274_reset(imx274, 1);
+ /* power on the sensor */
+ ret = imx274_power_on(&client->dev);
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "%s : imx274 power on failed\n", __func__);
+ goto err_me;
+ }
/* initialize controls */
ret = v4l2_ctrl_handler_init(&imx274->ctrls.handler, 4);
if (ret < 0) {
dev_err(&client->dev,
"%s : ctrl handler init Failed\n", __func__);
- goto err_me;
+ goto err_power_off;
}
imx274->ctrls.handler.lock = &imx274->lock;
@@ -1927,22 +2057,8 @@ static int imx274_probe(struct i2c_client *client)
goto err_ctrls;
}
- /* setup default controls */
- ret = v4l2_ctrl_handler_setup(&imx274->ctrls.handler);
- if (ret) {
- dev_err(&client->dev,
- "Error %d setup default controls\n", ret);
- goto err_ctrls;
- }
-
/* load default control values */
- ret = imx274_load_default(imx274);
- if (ret) {
- dev_err(&client->dev,
- "%s : imx274_load_default failed %d\n",
- __func__, ret);
- goto err_ctrls;
- }
+ imx274_load_default(imx274);
/* register subdevice */
ret = v4l2_async_register_subdev(sd);
@@ -1953,11 +2069,17 @@ static int imx274_probe(struct i2c_client *client)
goto err_ctrls;
}
+ pm_runtime_set_active(&client->dev);
+ pm_runtime_enable(&client->dev);
+ pm_runtime_idle(&client->dev);
+
dev_info(&client->dev, "imx274 : imx274 probe success !\n");
return 0;
err_ctrls:
v4l2_ctrl_handler_free(&imx274->ctrls.handler);
+err_power_off:
+ imx274_power_off(&client->dev);
err_me:
media_entity_cleanup(&sd->entity);
err_regmap:
@@ -1970,19 +2092,27 @@ static int imx274_remove(struct i2c_client *client)
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct stimx274 *imx274 = to_imx274(sd);
- /* stop stream */
- imx274_write_table(imx274, imx274_stop);
+ pm_runtime_disable(&client->dev);
+ if (!pm_runtime_status_suspended(&client->dev))
+ imx274_power_off(&client->dev);
+ pm_runtime_set_suspended(&client->dev);
v4l2_async_unregister_subdev(sd);
v4l2_ctrl_handler_free(&imx274->ctrls.handler);
+
media_entity_cleanup(&sd->entity);
mutex_destroy(&imx274->lock);
return 0;
}
+static const struct dev_pm_ops imx274_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx274_power_off, imx274_power_on, NULL)
+};
+
static struct i2c_driver imx274_i2c_driver = {
.driver = {
.name = DRIVER_NAME,
+ .pm = &imx274_pm_ops,
.of_match_table = imx274_of_id_table,
},
.probe_new = imx274_probe,
diff --git a/drivers/media/i2c/imx290.c b/drivers/media/i2c/imx290.c
index adcddf3204f7..6319a42057d2 100644
--- a/drivers/media/i2c/imx290.c
+++ b/drivers/media/i2c/imx290.c
@@ -842,20 +842,19 @@ exit:
static int imx290_power_on(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx290 *imx290 = to_imx290(sd);
int ret;
ret = clk_prepare_enable(imx290->xclk);
if (ret) {
- dev_err(imx290->dev, "Failed to enable clock\n");
+ dev_err(dev, "Failed to enable clock\n");
return ret;
}
ret = regulator_bulk_enable(IMX290_NUM_SUPPLIES, imx290->supplies);
if (ret) {
- dev_err(imx290->dev, "Failed to enable regulators\n");
+ dev_err(dev, "Failed to enable regulators\n");
clk_disable_unprepare(imx290->xclk);
return ret;
}
@@ -872,8 +871,7 @@ static int imx290_power_on(struct device *dev)
static int imx290_power_off(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx290 *imx290 = to_imx290(sd);
clk_disable_unprepare(imx290->xclk);
diff --git a/drivers/media/i2c/imx319.c b/drivers/media/i2c/imx319.c
index 17c2e4b41221..8473c0bbb35d 100644
--- a/drivers/media/i2c/imx319.c
+++ b/drivers/media/i2c/imx319.c
@@ -2179,8 +2179,7 @@ err_unlock:
static int __maybe_unused imx319_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx319 *imx319 = to_imx319(sd);
if (imx319->streaming)
@@ -2191,8 +2190,7 @@ static int __maybe_unused imx319_suspend(struct device *dev)
static int __maybe_unused imx319_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx319 *imx319 = to_imx319(sd);
int ret;
@@ -2535,7 +2533,7 @@ static const struct dev_pm_ops imx319_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(imx319_suspend, imx319_resume)
};
-static const struct acpi_device_id imx319_acpi_ids[] = {
+static const struct acpi_device_id imx319_acpi_ids[] __maybe_unused = {
{ "SONY319A" },
{ /* sentinel */ }
};
diff --git a/drivers/media/i2c/imx355.c b/drivers/media/i2c/imx355.c
index bed293b60e50..700f7467fb31 100644
--- a/drivers/media/i2c/imx355.c
+++ b/drivers/media/i2c/imx355.c
@@ -1480,8 +1480,7 @@ err_unlock:
static int __maybe_unused imx355_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx355 *imx355 = to_imx355(sd);
if (imx355->streaming)
@@ -1492,8 +1491,7 @@ static int __maybe_unused imx355_suspend(struct device *dev)
static int __maybe_unused imx355_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct imx355 *imx355 = to_imx355(sd);
int ret;
@@ -1835,7 +1833,7 @@ static const struct dev_pm_ops imx355_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(imx355_suspend, imx355_resume)
};
-static const struct acpi_device_id imx355_acpi_ids[] = {
+static const struct acpi_device_id imx355_acpi_ids[] __maybe_unused = {
{ "SONY355A" },
{ /* sentinel */ }
};
diff --git a/drivers/media/i2c/max2175.c b/drivers/media/i2c/max2175.c
index 03b4ed3a61b8..661208c9bfc5 100644
--- a/drivers/media/i2c/max2175.c
+++ b/drivers/media/i2c/max2175.c
@@ -503,7 +503,7 @@ static void max2175_set_bbfilter(struct max2175 *ctx)
}
}
-static bool max2175_set_csm_mode(struct max2175 *ctx,
+static int max2175_set_csm_mode(struct max2175 *ctx,
enum max2175_csm_mode new_mode)
{
int ret = max2175_poll_csm_ready(ctx);
diff --git a/drivers/media/i2c/max9271.c b/drivers/media/i2c/max9271.c
index 0f6f7a092a46..c247db569bab 100644
--- a/drivers/media/i2c/max9271.c
+++ b/drivers/media/i2c/max9271.c
@@ -223,12 +223,12 @@ int max9271_enable_gpios(struct max9271_device *dev, u8 gpio_mask)
{
int ret;
- ret = max9271_read(dev, 0x0f);
+ ret = max9271_read(dev, 0x0e);
if (ret < 0)
return 0;
/* BIT(0) reserved: GPO is always enabled. */
- ret |= gpio_mask | BIT(0);
+ ret |= (gpio_mask & ~BIT(0));
ret = max9271_write(dev, 0x0e, ret);
if (ret < 0) {
dev_err(&dev->client->dev, "Failed to enable gpio (%d)\n", ret);
@@ -245,12 +245,12 @@ int max9271_disable_gpios(struct max9271_device *dev, u8 gpio_mask)
{
int ret;
- ret = max9271_read(dev, 0x0f);
+ ret = max9271_read(dev, 0x0e);
if (ret < 0)
return 0;
/* BIT(0) reserved: GPO cannot be disabled */
- ret &= (~gpio_mask | BIT(0));
+ ret &= ~(gpio_mask | BIT(0));
ret = max9271_write(dev, 0x0e, ret);
if (ret < 0) {
dev_err(&dev->client->dev, "Failed to disable gpio (%d)\n", ret);
diff --git a/drivers/media/i2c/msp3400-kthreads.c b/drivers/media/i2c/msp3400-kthreads.c
index 52e506f86de5..ecabc0e1d32e 100644
--- a/drivers/media/i2c/msp3400-kthreads.c
+++ b/drivers/media/i2c/msp3400-kthreads.c
@@ -549,8 +549,10 @@ restart:
val = msp_read_dsp(client, 0x1b);
if (val > 32767)
val -= 65536;
- if (val1 < val)
- val1 = val, max1 = i;
+ if (val1 < val) {
+ val1 = val;
+ max1 = i;
+ }
dev_dbg_lvl(&client->dev, 1, msp_debug,
"carrier1 val: %5d / %s\n", val, cd[i].name);
}
@@ -586,8 +588,10 @@ restart:
val = msp_read_dsp(client, 0x1b);
if (val > 32767)
val -= 65536;
- if (val2 < val)
- val2 = val, max2 = i;
+ if (val2 < val) {
+ val2 = val;
+ max2 = i;
+ }
dev_dbg_lvl(&client->dev, 1, msp_debug,
"carrier2 val: %5d / %s\n", val, cd[i].name);
}
diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c
index dc23b9ed510a..a633b934d93e 100644
--- a/drivers/media/i2c/mt9p031.c
+++ b/drivers/media/i2c/mt9p031.c
@@ -346,8 +346,7 @@ static void mt9p031_power_off(struct mt9p031 *mt9p031)
regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators),
mt9p031->regulators);
- if (mt9p031->clk)
- clk_disable_unprepare(mt9p031->clk);
+ clk_disable_unprepare(mt9p031->clk);
}
static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on)
diff --git a/drivers/media/i2c/ov02a10.c b/drivers/media/i2c/ov02a10.c
new file mode 100644
index 000000000000..8683ffd3287a
--- /dev/null
+++ b/drivers/media/i2c/ov02a10.c
@@ -0,0 +1,1015 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <media/media-entity.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-subdev.h>
+
+#define OV02A10_ID 0x2509
+#define OV02A10_ID_MASK GENMASK(15, 0)
+
+#define OV02A10_REG_CHIP_ID 0x02
+
+/* Bit[1] vertical upside down */
+/* Bit[0] horizontal mirror */
+#define REG_MIRROR_FLIP_CONTROL 0x3f
+
+/* Orientation */
+#define REG_MIRROR_FLIP_ENABLE 0x03
+
+/* Bit[2:0] MIPI transmission speed select */
+#define TX_SPEED_AREA_SEL 0xa1
+#define OV02A10_MIPI_TX_SPEED_DEFAULT 0x04
+
+#define REG_PAGE_SWITCH 0xfd
+#define REG_GLOBAL_EFFECTIVE 0x01
+#define REG_ENABLE BIT(0)
+
+#define REG_SC_CTRL_MODE 0xac
+#define SC_CTRL_MODE_STANDBY 0x00
+#define SC_CTRL_MODE_STREAMING 0x01
+
+/* Exposure control */
+#define OV02A10_EXP_SHIFT 8
+#define OV02A10_REG_EXPOSURE_H 0x03
+#define OV02A10_REG_EXPOSURE_L 0x04
+#define OV02A10_EXPOSURE_MIN 4
+#define OV02A10_EXPOSURE_MAX_MARGIN 4
+#define OV02A10_EXPOSURE_STEP 1
+
+/* Vblanking control */
+#define OV02A10_VTS_SHIFT 8
+#define OV02A10_REG_VTS_H 0x05
+#define OV02A10_REG_VTS_L 0x06
+#define OV02A10_VTS_MAX 0x209f
+#define OV02A10_BASE_LINES 1224
+
+/* Analog gain control */
+#define OV02A10_REG_GAIN 0x24
+#define OV02A10_GAIN_MIN 0x10
+#define OV02A10_GAIN_MAX 0xf8
+#define OV02A10_GAIN_STEP 0x01
+#define OV02A10_GAIN_DEFAULT 0x40
+
+/* Test pattern control */
+#define OV02A10_REG_TEST_PATTERN 0xb6
+
+#define HZ_PER_MHZ 1000000L
+#define OV02A10_LINK_FREQ_390MHZ (390 * HZ_PER_MHZ)
+#define OV02A10_ECLK_FREQ (24 * HZ_PER_MHZ)
+
+/* Number of lanes supported by this driver */
+#define OV02A10_DATA_LANES 1
+
+/* Bits per sample of sensor output */
+#define OV02A10_BITS_PER_SAMPLE 10
+
+static const char * const ov02a10_supply_names[] = {
+ "dovdd", /* Digital I/O power */
+ "avdd", /* Analog power */
+ "dvdd", /* Digital core power */
+};
+
+struct ov02a10_reg {
+ u8 addr;
+ u8 val;
+};
+
+struct ov02a10_reg_list {
+ u32 num_of_regs;
+ const struct ov02a10_reg *regs;
+};
+
+struct ov02a10_mode {
+ u32 width;
+ u32 height;
+ u32 exp_def;
+ u32 hts_def;
+ u32 vts_def;
+ const struct ov02a10_reg_list reg_list;
+};
+
+struct ov02a10 {
+ u32 eclk_freq;
+ /* Indication of MIPI transmission speed select */
+ u32 mipi_clock_voltage;
+
+ struct clk *eclk;
+ struct gpio_desc *pd_gpio;
+ struct gpio_desc *rst_gpio;
+ struct regulator_bulk_data supplies[ARRAY_SIZE(ov02a10_supply_names)];
+
+ bool streaming;
+ bool upside_down;
+
+ /*
+ * Serialize control access, get/set format, get selection
+ * and start streaming.
+ */
+ struct mutex mutex;
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+ struct v4l2_mbus_framefmt fmt;
+ struct v4l2_ctrl_handler ctrl_handler;
+ struct v4l2_ctrl *exposure;
+
+ const struct ov02a10_mode *cur_mode;
+};
+
+static inline struct ov02a10 *to_ov02a10(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct ov02a10, subdev);
+}
+
+/*
+ * eclk 24Mhz
+ * pclk 39Mhz
+ * linelength 934(0x3a6)
+ * framelength 1390(0x56E)
+ * grabwindow_width 1600
+ * grabwindow_height 1200
+ * max_framerate 30fps
+ * mipi_datarate per lane 780Mbps
+ */
+static const struct ov02a10_reg ov02a10_1600x1200_regs[] = {
+ {0xfd, 0x01},
+ {0xac, 0x00},
+ {0xfd, 0x00},
+ {0x2f, 0x29},
+ {0x34, 0x00},
+ {0x35, 0x21},
+ {0x30, 0x15},
+ {0x33, 0x01},
+ {0xfd, 0x01},
+ {0x44, 0x00},
+ {0x2a, 0x4c},
+ {0x2b, 0x1e},
+ {0x2c, 0x60},
+ {0x25, 0x11},
+ {0x03, 0x01},
+ {0x04, 0xae},
+ {0x09, 0x00},
+ {0x0a, 0x02},
+ {0x06, 0xa6},
+ {0x31, 0x00},
+ {0x24, 0x40},
+ {0x01, 0x01},
+ {0xfb, 0x73},
+ {0xfd, 0x01},
+ {0x16, 0x04},
+ {0x1c, 0x09},
+ {0x21, 0x42},
+ {0x12, 0x04},
+ {0x13, 0x10},
+ {0x11, 0x40},
+ {0x33, 0x81},
+ {0xd0, 0x00},
+ {0xd1, 0x01},
+ {0xd2, 0x00},
+ {0x50, 0x10},
+ {0x51, 0x23},
+ {0x52, 0x20},
+ {0x53, 0x10},
+ {0x54, 0x02},
+ {0x55, 0x20},
+ {0x56, 0x02},
+ {0x58, 0x48},
+ {0x5d, 0x15},
+ {0x5e, 0x05},
+ {0x66, 0x66},
+ {0x68, 0x68},
+ {0x6b, 0x00},
+ {0x6c, 0x00},
+ {0x6f, 0x40},
+ {0x70, 0x40},
+ {0x71, 0x0a},
+ {0x72, 0xf0},
+ {0x73, 0x10},
+ {0x75, 0x80},
+ {0x76, 0x10},
+ {0x84, 0x00},
+ {0x85, 0x10},
+ {0x86, 0x10},
+ {0x87, 0x00},
+ {0x8a, 0x22},
+ {0x8b, 0x22},
+ {0x19, 0xf1},
+ {0x29, 0x01},
+ {0xfd, 0x01},
+ {0x9d, 0x16},
+ {0xa0, 0x29},
+ {0xa1, 0x04},
+ {0xad, 0x62},
+ {0xae, 0x00},
+ {0xaf, 0x85},
+ {0xb1, 0x01},
+ {0x8e, 0x06},
+ {0x8f, 0x40},
+ {0x90, 0x04},
+ {0x91, 0xb0},
+ {0x45, 0x01},
+ {0x46, 0x00},
+ {0x47, 0x6c},
+ {0x48, 0x03},
+ {0x49, 0x8b},
+ {0x4a, 0x00},
+ {0x4b, 0x07},
+ {0x4c, 0x04},
+ {0x4d, 0xb7},
+ {0xf0, 0x40},
+ {0xf1, 0x40},
+ {0xf2, 0x40},
+ {0xf3, 0x40},
+ {0x3f, 0x00},
+ {0xfd, 0x01},
+ {0x05, 0x00},
+ {0x06, 0xa6},
+ {0xfd, 0x01},
+};
+
+static const char * const ov02a10_test_pattern_menu[] = {
+ "Disabled",
+ "Eight Vertical Colour Bars",
+};
+
+static const s64 link_freq_menu_items[] = {
+ OV02A10_LINK_FREQ_390MHZ,
+};
+
+static u64 to_pixel_rate(u32 f_index)
+{
+ u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV02A10_DATA_LANES;
+
+ do_div(pixel_rate, OV02A10_BITS_PER_SAMPLE);
+
+ return pixel_rate;
+}
+
+static const struct ov02a10_mode supported_modes[] = {
+ {
+ .width = 1600,
+ .height = 1200,
+ .exp_def = 0x01ae,
+ .hts_def = 0x03a6,
+ .vts_def = 0x056e,
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(ov02a10_1600x1200_regs),
+ .regs = ov02a10_1600x1200_regs,
+ },
+ },
+};
+
+static int ov02a10_write_array(struct ov02a10 *ov02a10,
+ const struct ov02a10_reg_list *r_list)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < r_list->num_of_regs; i++) {
+ ret = i2c_smbus_write_byte_data(client, r_list->regs[i].addr,
+ r_list->regs[i].val);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static void ov02a10_fill_fmt(const struct ov02a10_mode *mode,
+ struct v4l2_mbus_framefmt *fmt)
+{
+ fmt->width = mode->width;
+ fmt->height = mode->height;
+ fmt->field = V4L2_FIELD_NONE;
+}
+
+static int ov02a10_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
+ struct v4l2_mbus_framefmt *frame_fmt;
+ int ret = 0;
+
+ mutex_lock(&ov02a10->mutex);
+
+ if (ov02a10->streaming && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ ret = -EBUSY;
+ goto out_unlock;
+ }
+
+ /* Only one sensor mode supported */
+ mbus_fmt->code = ov02a10->fmt.code;
+ ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt);
+
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
+ frame_fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
+ else
+ frame_fmt = &ov02a10->fmt;
+
+ *frame_fmt = *mbus_fmt;
+
+out_unlock:
+ mutex_unlock(&ov02a10->mutex);
+ return ret;
+}
+
+static int ov02a10_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
+
+ mutex_lock(&ov02a10->mutex);
+
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+ fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
+ } else {
+ fmt->format = ov02a10->fmt;
+ mbus_fmt->code = ov02a10->fmt.code;
+ ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt);
+ }
+
+ mutex_unlock(&ov02a10->mutex);
+
+ return 0;
+}
+
+static int ov02a10_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ if (code->index != 0)
+ return -EINVAL;
+
+ code->code = ov02a10->fmt.code;
+
+ return 0;
+}
+
+static int ov02a10_enum_frame_sizes(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ if (fse->index >= ARRAY_SIZE(supported_modes))
+ return -EINVAL;
+
+ fse->min_width = supported_modes[fse->index].width;
+ fse->max_width = supported_modes[fse->index].width;
+ fse->max_height = supported_modes[fse->index].height;
+ fse->min_height = supported_modes[fse->index].height;
+
+ return 0;
+}
+
+static int ov02a10_check_sensor_id(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ u16 chip_id;
+ int ret;
+
+ /* Validate the chip ID */
+ ret = i2c_smbus_read_word_swapped(client, OV02A10_REG_CHIP_ID);
+ if (ret < 0)
+ return ret;
+
+ chip_id = le16_to_cpu(ret);
+
+ if ((chip_id & OV02A10_ID_MASK) != OV02A10_ID) {
+ dev_err(&client->dev, "unexpected sensor id(0x%04x)\n", chip_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ov02a10_power_on(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ int ret;
+
+ gpiod_set_value_cansleep(ov02a10->rst_gpio, 1);
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, 1);
+
+ ret = clk_prepare_enable(ov02a10->eclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable eclk\n");
+ return ret;
+ }
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(ov02a10_supply_names),
+ ov02a10->supplies);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable regulators\n");
+ goto disable_clk;
+ }
+ usleep_range(5000, 6000);
+
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, 0);
+ usleep_range(5000, 6000);
+
+ gpiod_set_value_cansleep(ov02a10->rst_gpio, 0);
+ usleep_range(5000, 6000);
+
+ ret = ov02a10_check_sensor_id(ov02a10);
+ if (ret)
+ goto disable_regulator;
+
+ return 0;
+
+disable_regulator:
+ regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names),
+ ov02a10->supplies);
+disable_clk:
+ clk_disable_unprepare(ov02a10->eclk);
+
+ return ret;
+}
+
+static int ov02a10_power_off(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ gpiod_set_value_cansleep(ov02a10->rst_gpio, 1);
+ clk_disable_unprepare(ov02a10->eclk);
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, 1);
+ regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names),
+ ov02a10->supplies);
+
+ return 0;
+}
+
+static int __ov02a10_start_stream(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ const struct ov02a10_reg_list *reg_list;
+ int ret;
+
+ /* Apply default values of current mode */
+ reg_list = &ov02a10->cur_mode->reg_list;
+ ret = ov02a10_write_array(ov02a10, reg_list);
+ if (ret)
+ return ret;
+
+ /* Apply customized values from user */
+ ret = __v4l2_ctrl_handler_setup(ov02a10->subdev.ctrl_handler);
+ if (ret)
+ return ret;
+
+ /* Set orientation to 180 degree */
+ if (ov02a10->upside_down) {
+ ret = i2c_smbus_write_byte_data(client, REG_MIRROR_FLIP_CONTROL,
+ REG_MIRROR_FLIP_ENABLE);
+ if (ret < 0) {
+ dev_err(&client->dev, "failed to set orientation\n");
+ return ret;
+ }
+ ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Set MIPI TX speed according to DT property */
+ if (ov02a10->mipi_clock_voltage != OV02A10_MIPI_TX_SPEED_DEFAULT) {
+ ret = i2c_smbus_write_byte_data(client, TX_SPEED_AREA_SEL,
+ ov02a10->mipi_clock_voltage);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Set stream on register */
+ return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
+ SC_CTRL_MODE_STREAMING);
+}
+
+static int __ov02a10_stop_stream(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+
+ return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
+ SC_CTRL_MODE_STANDBY);
+}
+
+static int ov02a10_entity_init_cfg(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg)
+{
+ struct v4l2_subdev_format fmt = {
+ .which = V4L2_SUBDEV_FORMAT_TRY,
+ .format = {
+ .width = 1600,
+ .height = 1200,
+ }
+ };
+
+ ov02a10_set_fmt(sd, cfg, &fmt);
+
+ return 0;
+}
+
+static int ov02a10_s_stream(struct v4l2_subdev *sd, int on)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ mutex_lock(&ov02a10->mutex);
+
+ if (ov02a10->streaming == on) {
+ ret = 0;
+ goto unlock_and_return;
+ }
+
+ if (on) {
+ ret = pm_runtime_get_sync(&client->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&client->dev);
+ goto unlock_and_return;
+ }
+
+ ret = __ov02a10_start_stream(ov02a10);
+ if (ret) {
+ __ov02a10_stop_stream(ov02a10);
+ ov02a10->streaming = !on;
+ goto err_rpm_put;
+ }
+ } else {
+ __ov02a10_stop_stream(ov02a10);
+ pm_runtime_put(&client->dev);
+ }
+
+ ov02a10->streaming = on;
+ mutex_unlock(&ov02a10->mutex);
+
+ return 0;
+
+err_rpm_put:
+ pm_runtime_put(&client->dev);
+unlock_and_return:
+ mutex_unlock(&ov02a10->mutex);
+
+ return ret;
+}
+
+static const struct dev_pm_ops ov02a10_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(ov02a10_power_off, ov02a10_power_on, NULL)
+};
+
+static int ov02a10_set_exposure(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_H,
+ val >> OV02A10_EXP_SHIFT);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_L, val);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_gain(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_GAIN, val);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_vblank(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ u32 vts = val + ov02a10->cur_mode->height - OV02A10_BASE_LINES;
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_H,
+ vts >> OV02A10_VTS_SHIFT);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_L, vts);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_test_pattern(struct ov02a10 *ov02a10, int pattern)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_TEST_PATTERN,
+ pattern);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
+ SC_CTRL_MODE_STREAMING);
+}
+
+static int ov02a10_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ov02a10 *ov02a10 = container_of(ctrl->handler,
+ struct ov02a10, ctrl_handler);
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ s64 max_expo;
+ int ret;
+
+ /* Propagate change of current control to all related controls */
+ if (ctrl->id == V4L2_CID_VBLANK) {
+ /* Update max exposure while meeting expected vblanking */
+ max_expo = ov02a10->cur_mode->height + ctrl->val -
+ OV02A10_EXPOSURE_MAX_MARGIN;
+ __v4l2_ctrl_modify_range(ov02a10->exposure,
+ ov02a10->exposure->minimum, max_expo,
+ ov02a10->exposure->step,
+ ov02a10->exposure->default_value);
+ }
+
+ /* V4L2 controls values will be applied only when power is already up */
+ if (!pm_runtime_get_if_in_use(&client->dev))
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_EXPOSURE:
+ ret = ov02a10_set_exposure(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_ANALOGUE_GAIN:
+ ret = ov02a10_set_gain(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_VBLANK:
+ ret = ov02a10_set_vblank(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_TEST_PATTERN:
+ ret = ov02a10_set_test_pattern(ov02a10, ctrl->val);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ };
+
+ pm_runtime_put(&client->dev);
+
+ return ret;
+}
+
+static const struct v4l2_subdev_video_ops ov02a10_video_ops = {
+ .s_stream = ov02a10_s_stream,
+};
+
+static const struct v4l2_subdev_pad_ops ov02a10_pad_ops = {
+ .init_cfg = ov02a10_entity_init_cfg,
+ .enum_mbus_code = ov02a10_enum_mbus_code,
+ .enum_frame_size = ov02a10_enum_frame_sizes,
+ .get_fmt = ov02a10_get_fmt,
+ .set_fmt = ov02a10_set_fmt,
+};
+
+static const struct v4l2_subdev_ops ov02a10_subdev_ops = {
+ .video = &ov02a10_video_ops,
+ .pad = &ov02a10_pad_ops,
+};
+
+static const struct media_entity_operations ov02a10_subdev_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct v4l2_ctrl_ops ov02a10_ctrl_ops = {
+ .s_ctrl = ov02a10_set_ctrl,
+};
+
+static int ov02a10_initialize_controls(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ const struct ov02a10_mode *mode;
+ struct v4l2_ctrl_handler *handler;
+ struct v4l2_ctrl *ctrl;
+ s64 exposure_max;
+ s64 vblank_def;
+ s64 pixel_rate;
+ s64 h_blank;
+ int ret;
+
+ handler = &ov02a10->ctrl_handler;
+ mode = ov02a10->cur_mode;
+ ret = v4l2_ctrl_handler_init(handler, 7);
+ if (ret)
+ return ret;
+
+ handler->lock = &ov02a10->mutex;
+
+ ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0,
+ link_freq_menu_items);
+ if (ctrl)
+ ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ pixel_rate = to_pixel_rate(0);
+ v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1,
+ pixel_rate);
+
+ h_blank = mode->hts_def - mode->width;
+ v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK, h_blank, h_blank, 1,
+ h_blank);
+
+ vblank_def = mode->vts_def - mode->height;
+ v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops, V4L2_CID_VBLANK,
+ vblank_def, OV02A10_VTS_MAX - mode->height, 1,
+ vblank_def);
+
+ exposure_max = mode->vts_def - 4;
+ ov02a10->exposure = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_EXPOSURE,
+ OV02A10_EXPOSURE_MIN,
+ exposure_max,
+ OV02A10_EXPOSURE_STEP,
+ mode->exp_def);
+
+ v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_ANALOGUE_GAIN, OV02A10_GAIN_MIN,
+ OV02A10_GAIN_MAX, OV02A10_GAIN_STEP,
+ OV02A10_GAIN_DEFAULT);
+
+ v4l2_ctrl_new_std_menu_items(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ov02a10_test_pattern_menu) - 1,
+ 0, 0, ov02a10_test_pattern_menu);
+
+ if (handler->error) {
+ ret = handler->error;
+ dev_err(&client->dev, "failed to init controls(%d)\n", ret);
+ goto err_free_handler;
+ }
+
+ ov02a10->subdev.ctrl_handler = handler;
+
+ return 0;
+
+err_free_handler:
+ v4l2_ctrl_handler_free(handler);
+
+ return ret;
+}
+
+static int ov02a10_check_hwcfg(struct device *dev, struct ov02a10 *ov02a10)
+{
+ struct fwnode_handle *ep;
+ struct fwnode_handle *fwnode = dev_fwnode(dev);
+ struct v4l2_fwnode_endpoint bus_cfg = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY,
+ };
+ unsigned int i, j;
+ u32 clk_volt;
+ int ret;
+
+ if (!fwnode)
+ return -EINVAL;
+
+ ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
+ if (!ep)
+ return -ENXIO;
+
+ ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ fwnode_handle_put(ep);
+ if (ret)
+ return ret;
+
+ /* Optional indication of MIPI clock voltage unit */
+ ret = fwnode_property_read_u32(ep, "ovti,mipi-clock-voltage",
+ &clk_volt);
+
+ if (!ret)
+ ov02a10->mipi_clock_voltage = clk_volt;
+
+ for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
+ for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
+ if (link_freq_menu_items[i] ==
+ bus_cfg.link_frequencies[j])
+ break;
+ }
+
+ if (j == bus_cfg.nr_of_link_frequencies) {
+ dev_err(dev, "no link frequency %lld supported\n",
+ link_freq_menu_items[i]);
+ ret = -EINVAL;
+ break;
+ }
+ }
+
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+
+ return ret;
+}
+
+static int ov02a10_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct ov02a10 *ov02a10;
+ unsigned int i;
+ unsigned int rotation;
+ int ret;
+
+ ov02a10 = devm_kzalloc(dev, sizeof(*ov02a10), GFP_KERNEL);
+ if (!ov02a10)
+ return -ENOMEM;
+
+ ret = ov02a10_check_hwcfg(dev, ov02a10);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to check HW configuration\n");
+
+ v4l2_i2c_subdev_init(&ov02a10->subdev, client, &ov02a10_subdev_ops);
+
+ ov02a10->mipi_clock_voltage = OV02A10_MIPI_TX_SPEED_DEFAULT;
+ ov02a10->fmt.code = MEDIA_BUS_FMT_SBGGR10_1X10;
+
+ /* Optional indication of physical rotation of sensor */
+ rotation = 0;
+ device_property_read_u32(dev, "rotation", &rotation);
+ if (rotation == 180) {
+ ov02a10->upside_down = true;
+ ov02a10->fmt.code = MEDIA_BUS_FMT_SRGGB10_1X10;
+ }
+
+ ov02a10->eclk = devm_clk_get(dev, "eclk");
+ if (IS_ERR(ov02a10->eclk))
+ return dev_err_probe(dev, PTR_ERR(ov02a10->eclk),
+ "failed to get eclk\n");
+
+ ret = device_property_read_u32(dev, "clock-frequency",
+ &ov02a10->eclk_freq);
+ if (ret < 0)
+ return dev_err_probe(dev, ret,
+ "failed to get eclk frequency\n");
+
+ ret = clk_set_rate(ov02a10->eclk, ov02a10->eclk_freq);
+ if (ret < 0)
+ return dev_err_probe(dev, ret,
+ "failed to set eclk frequency (24MHz)\n");
+
+ if (clk_get_rate(ov02a10->eclk) != OV02A10_ECLK_FREQ)
+ dev_warn(dev, "eclk mismatched, mode is based on 24MHz\n");
+
+ ov02a10->pd_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_HIGH);
+ if (IS_ERR(ov02a10->pd_gpio))
+ return dev_err_probe(dev, PTR_ERR(ov02a10->pd_gpio),
+ "failed to get powerdown-gpios\n");
+
+ ov02a10->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(ov02a10->rst_gpio))
+ return dev_err_probe(dev, PTR_ERR(ov02a10->rst_gpio),
+ "failed to get reset-gpios\n");
+
+ for (i = 0; i < ARRAY_SIZE(ov02a10_supply_names); i++)
+ ov02a10->supplies[i].supply = ov02a10_supply_names[i];
+
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02a10_supply_names),
+ ov02a10->supplies);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get regulators\n");
+
+ mutex_init(&ov02a10->mutex);
+
+ /* Set default mode */
+ ov02a10->cur_mode = &supported_modes[0];
+
+ ret = ov02a10_initialize_controls(ov02a10);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to initialize controls\n");
+ goto err_destroy_mutex;
+ }
+
+ /* Initialize subdev */
+ ov02a10->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ ov02a10->subdev.entity.ops = &ov02a10_subdev_entity_ops;
+ ov02a10->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ov02a10->pad.flags = MEDIA_PAD_FL_SOURCE;
+
+ ret = media_entity_pads_init(&ov02a10->subdev.entity, 1, &ov02a10->pad);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "failed to initialize entity pads\n");
+ goto err_free_handler;
+ }
+
+ pm_runtime_enable(dev);
+ if (!pm_runtime_enabled(dev)) {
+ ret = ov02a10_power_on(dev);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "failed to power on\n");
+ goto err_clean_entity;
+ }
+ }
+
+ ret = v4l2_async_register_subdev(&ov02a10->subdev);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to register V4L2 subdev\n");
+ goto err_power_off;
+ }
+
+ return 0;
+
+err_power_off:
+ if (pm_runtime_enabled(dev))
+ pm_runtime_disable(dev);
+ else
+ ov02a10_power_off(dev);
+err_clean_entity:
+ media_entity_cleanup(&ov02a10->subdev.entity);
+err_free_handler:
+ v4l2_ctrl_handler_free(ov02a10->subdev.ctrl_handler);
+err_destroy_mutex:
+ mutex_destroy(&ov02a10->mutex);
+
+ return ret;
+}
+
+static int ov02a10_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ v4l2_async_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+ v4l2_ctrl_handler_free(sd->ctrl_handler);
+ pm_runtime_disable(&client->dev);
+ if (!pm_runtime_status_suspended(&client->dev))
+ ov02a10_power_off(&client->dev);
+ pm_runtime_set_suspended(&client->dev);
+ mutex_destroy(&ov02a10->mutex);
+
+ return 0;
+}
+
+static const struct of_device_id ov02a10_of_match[] = {
+ { .compatible = "ovti,ov02a10" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ov02a10_of_match);
+
+static struct i2c_driver ov02a10_i2c_driver = {
+ .driver = {
+ .name = "ov02a10",
+ .pm = &ov02a10_pm_ops,
+ .of_match_table = ov02a10_of_match,
+ },
+ .probe_new = &ov02a10_probe,
+ .remove = &ov02a10_remove,
+};
+module_i2c_driver(ov02a10_i2c_driver);
+
+MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
+MODULE_DESCRIPTION("OmniVision OV02A10 sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/ov13858.c b/drivers/media/i2c/ov13858.c
index 236ad2c816b7..2f3be7a80cef 100644
--- a/drivers/media/i2c/ov13858.c
+++ b/drivers/media/i2c/ov13858.c
@@ -1505,8 +1505,7 @@ err_unlock:
static int __maybe_unused ov13858_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov13858 *ov13858 = to_ov13858(sd);
if (ov13858->streaming)
@@ -1517,8 +1516,7 @@ static int __maybe_unused ov13858_suspend(struct device *dev)
static int __maybe_unused ov13858_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov13858 *ov13858 = to_ov13858(sd);
int ret;
diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c
index 59cdbc33658c..178dfe985a25 100644
--- a/drivers/media/i2c/ov2680.c
+++ b/drivers/media/i2c/ov2680.c
@@ -1111,8 +1111,7 @@ static int ov2680_remove(struct i2c_client *client)
static int __maybe_unused ov2680_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov2680_dev *sensor = to_ov2680_dev(sd);
if (sensor->is_streaming)
@@ -1123,8 +1122,7 @@ static int __maybe_unused ov2680_suspend(struct device *dev)
static int __maybe_unused ov2680_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov2680_dev *sensor = to_ov2680_dev(sd);
int ret;
diff --git a/drivers/media/i2c/ov2685.c b/drivers/media/i2c/ov2685.c
index 6814583d9606..49a2dcedb347 100644
--- a/drivers/media/i2c/ov2685.c
+++ b/drivers/media/i2c/ov2685.c
@@ -506,8 +506,7 @@ static int ov2685_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
static int __maybe_unused ov2685_runtime_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov2685 *ov2685 = to_ov2685(sd);
return __ov2685_power_on(ov2685);
@@ -515,8 +514,7 @@ static int __maybe_unused ov2685_runtime_resume(struct device *dev)
static int __maybe_unused ov2685_runtime_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov2685 *ov2685 = to_ov2685(sd);
__ov2685_power_off(ov2685);
diff --git a/drivers/media/i2c/ov2740.c b/drivers/media/i2c/ov2740.c
index bd0d45b0d43f..b41a90c2aed5 100644
--- a/drivers/media/i2c/ov2740.c
+++ b/drivers/media/i2c/ov2740.c
@@ -37,7 +37,7 @@
/* Exposure controls from sensor */
#define OV2740_REG_EXPOSURE 0x3500
-#define OV2740_EXPOSURE_MIN 8
+#define OV2740_EXPOSURE_MIN 4
#define OV2740_EXPOSURE_MAX_MARGIN 8
#define OV2740_EXPOSURE_STEP 1
@@ -71,9 +71,10 @@
#define OV2740_REG_OTP_CUSTOMER 0x7010
struct nvm_data {
- char *nvm_buffer;
+ struct i2c_client *client;
struct nvmem_device *nvmem;
struct regmap *regmap;
+ char *nvm_buffer;
};
enum {
@@ -335,6 +336,9 @@ struct ov2740 {
/* Streaming on/off */
bool streaming;
+
+ /* NVM data inforamtion */
+ struct nvm_data *nvm;
};
static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
@@ -594,13 +598,112 @@ static void ov2740_update_pad_format(const struct ov2740_mode *mode,
fmt->field = V4L2_FIELD_NONE;
}
+static int ov2740_load_otp_data(struct nvm_data *nvm)
+{
+ struct i2c_client *client;
+ struct ov2740 *ov2740;
+ u32 isp_ctrl00 = 0;
+ u32 isp_ctrl01 = 0;
+ int ret;
+
+ if (!nvm)
+ return -EINVAL;
+
+ if (nvm->nvm_buffer)
+ return 0;
+
+ client = nvm->client;
+ ov2740 = to_ov2740(i2c_get_clientdata(client));
+
+ nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
+ if (!nvm->nvm_buffer)
+ return -ENOMEM;
+
+ ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
+ if (ret) {
+ dev_err(&client->dev, "failed to read ISP CTRL00\n");
+ goto err;
+ }
+
+ ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
+ if (ret) {
+ dev_err(&client->dev, "failed to read ISP CTRL01\n");
+ goto err;
+ }
+
+ /* Clear bit 5 of ISP CTRL00 */
+ ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
+ isp_ctrl00 & ~BIT(5));
+ if (ret) {
+ dev_err(&client->dev, "failed to set ISP CTRL00\n");
+ goto err;
+ }
+
+ /* Clear bit 7 of ISP CTRL01 */
+ ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
+ isp_ctrl01 & ~BIT(7));
+ if (ret) {
+ dev_err(&client->dev, "failed to set ISP CTRL01\n");
+ goto err;
+ }
+
+ ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
+ OV2740_MODE_STREAMING);
+ if (ret) {
+ dev_err(&client->dev, "failed to set streaming mode\n");
+ goto err;
+ }
+
+ /*
+ * Users are not allowed to access OTP-related registers and memory
+ * during the 20 ms period after streaming starts (0x100 = 0x01).
+ */
+ msleep(20);
+
+ ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
+ nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
+ if (ret) {
+ dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
+ goto err;
+ }
+
+ ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
+ OV2740_MODE_STANDBY);
+ if (ret) {
+ dev_err(&client->dev, "failed to set streaming mode\n");
+ goto err;
+ }
+
+ ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
+ if (ret) {
+ dev_err(&client->dev, "failed to set ISP CTRL01\n");
+ goto err;
+ }
+
+ ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
+ if (ret) {
+ dev_err(&client->dev, "failed to set ISP CTRL00\n");
+ goto err;
+ }
+
+ return 0;
+err:
+ kfree(nvm->nvm_buffer);
+ nvm->nvm_buffer = NULL;
+
+ return ret;
+}
+
static int ov2740_start_streaming(struct ov2740 *ov2740)
{
struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
+ struct nvm_data *nvm = ov2740->nvm;
const struct ov2740_reg_list *reg_list;
int link_freq_index;
int ret = 0;
+ ov2740_load_otp_data(nvm);
+
link_freq_index = ov2740->cur_mode->link_freq_index;
reg_list = &link_freq_configs[link_freq_index].reg_list;
ret = ov2740_write_reg_list(ov2740, reg_list);
@@ -674,8 +777,7 @@ static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
static int __maybe_unused ov2740_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov2740 *ov2740 = to_ov2740(sd);
mutex_lock(&ov2740->mutex);
@@ -689,8 +791,7 @@ static int __maybe_unused ov2740_suspend(struct device *dev)
static int __maybe_unused ov2740_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov2740 *ov2740 = to_ov2740(sd);
int ret = 0;
@@ -932,96 +1033,52 @@ static int ov2740_remove(struct i2c_client *client)
return 0;
}
-static int ov2740_load_otp_data(struct i2c_client *client, struct nvm_data *nvm)
+static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
+ size_t count)
{
- struct ov2740 *ov2740 = to_ov2740(i2c_get_clientdata(client));
- u32 isp_ctrl00 = 0;
- u32 isp_ctrl01 = 0;
- int ret;
-
- ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
- if (ret) {
- dev_err(&client->dev, "failed to read ISP CTRL00\n");
- goto exit;
- }
- ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
- if (ret) {
- dev_err(&client->dev, "failed to read ISP CTRL01\n");
- goto exit;
- }
-
- /* Clear bit 5 of ISP CTRL00 */
- ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
- isp_ctrl00 & ~BIT(5));
- if (ret) {
- dev_err(&client->dev, "failed to write ISP CTRL00\n");
- goto exit;
- }
+ struct nvm_data *nvm = priv;
+ struct v4l2_subdev *sd = i2c_get_clientdata(nvm->client);
+ struct device *dev = &nvm->client->dev;
+ struct ov2740 *ov2740 = to_ov2740(sd);
+ int ret = 0;
- /* Clear bit 7 of ISP CTRL01 */
- ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
- isp_ctrl01 & ~BIT(7));
- if (ret) {
- dev_err(&client->dev, "failed to write ISP CTRL01\n");
- goto exit;
- }
+ mutex_lock(&ov2740->mutex);
- ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
- OV2740_MODE_STREAMING);
- if (ret) {
- dev_err(&client->dev, "failed to start streaming\n");
+ if (nvm->nvm_buffer) {
+ memcpy(val, nvm->nvm_buffer + off, count);
goto exit;
}
- /*
- * Users are not allowed to access OTP-related registers and memory
- * during the 20 ms period after streaming starts (0x100 = 0x01).
- */
- msleep(20);
-
- ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
- nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
- if (ret) {
- dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(dev);
goto exit;
}
- ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
- OV2740_MODE_STANDBY);
- ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
- ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
+ ret = ov2740_load_otp_data(nvm);
+ if (!ret)
+ memcpy(val, nvm->nvm_buffer + off, count);
+ pm_runtime_put(dev);
exit:
+ mutex_unlock(&ov2740->mutex);
return ret;
}
-static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
- size_t count)
-{
- struct nvm_data *nvm = priv;
-
- memcpy(val, nvm->nvm_buffer + off, count);
-
- return 0;
-}
-
-static int ov2740_register_nvmem(struct i2c_client *client)
+static int ov2740_register_nvmem(struct i2c_client *client,
+ struct ov2740 *ov2740)
{
struct nvm_data *nvm;
struct regmap_config regmap_config = { };
struct nvmem_config nvmem_config = { };
struct regmap *regmap;
struct device *dev = &client->dev;
- int ret = 0;
+ int ret;
nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
if (!nvm)
return -ENOMEM;
- nvm->nvm_buffer = devm_kzalloc(dev, CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
- if (!nvm->nvm_buffer)
- return -ENOMEM;
-
regmap_config.val_bits = 8;
regmap_config.reg_bits = 16;
regmap_config.disable_locking = true;
@@ -1030,12 +1087,7 @@ static int ov2740_register_nvmem(struct i2c_client *client)
return PTR_ERR(regmap);
nvm->regmap = regmap;
-
- ret = ov2740_load_otp_data(client, nvm);
- if (ret) {
- dev_err(dev, "failed to load OTP data, ret %d\n", ret);
- return ret;
- }
+ nvm->client = client;
nvmem_config.name = dev_name(dev);
nvmem_config.dev = dev;
@@ -1053,7 +1105,11 @@ static int ov2740_register_nvmem(struct i2c_client *client)
nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
- return PTR_ERR_OR_ZERO(nvm->nvmem);
+ ret = PTR_ERR_OR_ZERO(nvm->nvmem);
+ if (!ret)
+ ov2740->nvm = nvm;
+
+ return ret;
}
static int ov2740_probe(struct i2c_client *client)
@@ -1105,7 +1161,7 @@ static int ov2740_probe(struct i2c_client *client)
goto probe_error_media_entity_cleanup;
}
- ret = ov2740_register_nvmem(client);
+ ret = ov2740_register_nvmem(client, ov2740);
if (ret)
dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
index 8d0254d0e5ea..14f3afa7721a 100644
--- a/drivers/media/i2c/ov5640.c
+++ b/drivers/media/i2c/ov5640.c
@@ -98,7 +98,8 @@
#define OV5640_REG_AVG_READOUT 0x56a1
enum ov5640_mode_id {
- OV5640_MODE_QCIF_176_144 = 0,
+ OV5640_MODE_QQVGA_160_120 = 0,
+ OV5640_MODE_QCIF_176_144,
OV5640_MODE_QVGA_320_240,
OV5640_MODE_VGA_640_480,
OV5640_MODE_NTSC_720_480,
@@ -416,6 +417,24 @@ static const struct reg_value ov5640_setting_QVGA_320_240[] = {
{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
};
+static const struct reg_value ov5640_setting_QQVGA_160_120[] = {
+ {0x3c07, 0x08, 0, 0},
+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
+ {0x3814, 0x31, 0, 0},
+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
+ {0x3810, 0x00, 0, 0},
+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
+ {0x4407, 0x04, 0, 0}, {0x5001, 0xa3, 0, 0},
+};
+
static const struct reg_value ov5640_setting_QCIF_176_144[] = {
{0x3c07, 0x08, 0, 0},
{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
@@ -552,6 +571,11 @@ static const struct ov5640_mode_info ov5640_mode_init_data = {
static const struct ov5640_mode_info
ov5640_mode_data[OV5640_NUM_MODES] = {
+ {OV5640_MODE_QQVGA_160_120, SUBSAMPLING,
+ 160, 1896, 120, 984,
+ ov5640_setting_QQVGA_160_120,
+ ARRAY_SIZE(ov5640_setting_QQVGA_160_120),
+ OV5640_30_FPS},
{OV5640_MODE_QCIF_176_144, SUBSAMPLING,
176, 1896, 144, 984,
ov5640_setting_QCIF_176_144,
@@ -1216,20 +1240,6 @@ static int ov5640_set_autogain(struct ov5640_dev *sensor, bool on)
BIT(1), on ? 0 : BIT(1));
}
-static int ov5640_set_stream_bt656(struct ov5640_dev *sensor, bool on)
-{
- int ret;
-
- ret = ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00,
- on ? 0x1 : 0x00);
- if (ret)
- return ret;
-
- return ov5640_write_reg(sensor, OV5640_REG_SYS_CTRL0, on ?
- OV5640_REG_SYS_CTRL0_SW_PWUP :
- OV5640_REG_SYS_CTRL0_SW_PWDN);
-}
-
static int ov5640_set_stream_dvp(struct ov5640_dev *sensor, bool on)
{
return ov5640_write_reg(sensor, OV5640_REG_SYS_CTRL0, on ?
@@ -1994,13 +2004,13 @@ static int ov5640_set_power_mipi(struct ov5640_dev *sensor, bool on)
static int ov5640_set_power_dvp(struct ov5640_dev *sensor, bool on)
{
unsigned int flags = sensor->ep.bus.parallel.flags;
- u8 pclk_pol = 0;
- u8 hsync_pol = 0;
- u8 vsync_pol = 0;
+ bool bt656 = sensor->ep.bus_type == V4L2_MBUS_BT656;
+ u8 polarities = 0;
int ret;
if (!on) {
/* Reset settings to their default values. */
+ ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00, 0x00);
ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x58);
ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00, 0x20);
ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE01, 0x00);
@@ -2024,7 +2034,35 @@ static int ov5640_set_power_dvp(struct ov5640_dev *sensor, bool on)
* - VSYNC: active high
* - HREF: active low
* - PCLK: active low
+ *
+ * VSYNC & HREF are not configured if BT656 bus mode is selected
*/
+
+ /*
+ * BT656 embedded synchronization configuration
+ *
+ * CCIR656 CTRL00
+ * - [7]: SYNC code selection (0: auto generate sync code,
+ * 1: sync code from regs 0x4732-0x4735)
+ * - [6]: f value in CCIR656 SYNC code when fixed f value
+ * - [5]: Fixed f value
+ * - [4:3]: Blank toggle data options (00: data=1'h040/1'h200,
+ * 01: data from regs 0x4736-0x4738, 10: always keep 0)
+ * - [1]: Clip data disable
+ * - [0]: CCIR656 mode enable
+ *
+ * Default CCIR656 SAV/EAV mode with default codes
+ * SAV=0xff000080 & EAV=0xff00009d is enabled here with settings:
+ * - CCIR656 mode enable
+ * - auto generation of sync codes
+ * - blank toggle data 1'h040/1'h200
+ * - clip reserved data (0x00 & 0xff changed to 0x01 & 0xfe)
+ */
+ ret = ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00,
+ bt656 ? 0x01 : 0x00);
+ if (ret)
+ return ret;
+
/*
* configure parallel port control lines polarity
*
@@ -2035,29 +2073,26 @@ static int ov5640_set_power_dvp(struct ov5640_dev *sensor, bool on)
* datasheet and hardware, 0 is active high
* and 1 is active low...)
*/
- if (sensor->ep.bus_type == V4L2_MBUS_PARALLEL) {
- if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
- pclk_pol = 1;
+ if (!bt656) {
if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
- hsync_pol = 1;
+ polarities |= BIT(1);
if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
- vsync_pol = 1;
-
- ret = ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00,
- (pclk_pol << 5) | (hsync_pol << 1) |
- vsync_pol);
-
- if (ret)
- return ret;
+ polarities |= BIT(0);
}
+ if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
+ polarities |= BIT(5);
+
+ ret = ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00, polarities);
+ if (ret)
+ return ret;
/*
- * powerdown MIPI TX/RX PHY & disable MIPI
+ * powerdown MIPI TX/RX PHY & enable DVP
*
* MIPI CONTROL 00
- * 4: PWDN PHY TX
- * 3: PWDN PHY RX
- * 2: MIPI enable
+ * [4] = 1 : Power down MIPI HS Tx
+ * [3] = 1 : Power down MIPI LS Rx
+ * [2] = 0 : DVP enable (MIPI disable)
*/
ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x18);
if (ret)
@@ -2074,8 +2109,7 @@ static int ov5640_set_power_dvp(struct ov5640_dev *sensor, bool on)
* - [3:0]: D[9:6] output enable
*/
ret = ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE01,
- sensor->ep.bus_type == V4L2_MBUS_PARALLEL ?
- 0x7f : 0x1f);
+ bt656 ? 0x1f : 0x7f);
if (ret)
return ret;
@@ -2925,8 +2959,6 @@ static int ov5640_s_stream(struct v4l2_subdev *sd, int enable)
if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY)
ret = ov5640_set_stream_mipi(sensor, enable);
- else if (sensor->ep.bus_type == V4L2_MBUS_BT656)
- ret = ov5640_set_stream_bt656(sensor, enable);
else
ret = ov5640_set_stream_dvp(sensor, enable);
diff --git a/drivers/media/i2c/ov5670.c b/drivers/media/i2c/ov5670.c
index f26252e35e08..148fd4e05029 100644
--- a/drivers/media/i2c/ov5670.c
+++ b/drivers/media/i2c/ov5670.c
@@ -2373,8 +2373,7 @@ unlock_and_return:
static int __maybe_unused ov5670_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov5670 *ov5670 = to_ov5670(sd);
if (ov5670->streaming)
@@ -2385,8 +2384,7 @@ static int __maybe_unused ov5670_suspend(struct device *dev)
static int __maybe_unused ov5670_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov5670 *ov5670 = to_ov5670(sd);
int ret;
diff --git a/drivers/media/i2c/ov5675.c b/drivers/media/i2c/ov5675.c
index 9540ce8918f0..5e35808037ad 100644
--- a/drivers/media/i2c/ov5675.c
+++ b/drivers/media/i2c/ov5675.c
@@ -889,8 +889,7 @@ static int ov5675_set_stream(struct v4l2_subdev *sd, int enable)
static int __maybe_unused ov5675_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov5675 *ov5675 = to_ov5675(sd);
mutex_lock(&ov5675->mutex);
@@ -904,8 +903,7 @@ static int __maybe_unused ov5675_suspend(struct device *dev)
static int __maybe_unused ov5675_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov5675 *ov5675 = to_ov5675(sd);
int ret;
diff --git a/drivers/media/i2c/ov5695.c b/drivers/media/i2c/ov5695.c
index cc678d9d2e0d..bbccb6f9582f 100644
--- a/drivers/media/i2c/ov5695.c
+++ b/drivers/media/i2c/ov5695.c
@@ -1033,8 +1033,7 @@ static void __ov5695_power_off(struct ov5695 *ov5695)
static int __maybe_unused ov5695_runtime_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov5695 *ov5695 = to_ov5695(sd);
return __ov5695_power_on(ov5695);
@@ -1042,8 +1041,7 @@ static int __maybe_unused ov5695_runtime_resume(struct device *dev)
static int __maybe_unused ov5695_runtime_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov5695 *ov5695 = to_ov5695(sd);
__ov5695_power_off(ov5695);
diff --git a/drivers/media/i2c/ov7670.c b/drivers/media/i2c/ov7670.c
index b42b289faaef..d2df811b1a40 100644
--- a/drivers/media/i2c/ov7670.c
+++ b/drivers/media/i2c/ov7670.c
@@ -561,6 +561,7 @@ static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
unsigned char *value)
{
struct ov7670_info *info = to_state(sd);
+
if (info->use_smbus)
return ov7670_read_smbus(sd, reg, value);
else
@@ -571,6 +572,7 @@ static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
unsigned char value)
{
struct ov7670_info *info = to_state(sd);
+
if (info->use_smbus)
return ov7670_write_smbus(sd, reg, value);
else
@@ -597,6 +599,7 @@ static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
{
while (vals->reg_num != 0xff || vals->value != 0xff) {
int ret = ov7670_write(sd, vals->reg_num, vals->value);
+
if (ret < 0)
return ret;
vals++;
@@ -921,27 +924,38 @@ static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
{
int ret;
unsigned char v;
-/*
- * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
- * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
- * a mystery "edge offset" value in the top two bits of href.
- */
- ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
- ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
- ret += ov7670_read(sd, REG_HREF, &v);
+ /*
+ * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
+ * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
+ * a mystery "edge offset" value in the top two bits of href.
+ */
+ ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
+ if (ret)
+ return ret;
+ ret = ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
+ if (ret)
+ return ret;
+ ret = ov7670_read(sd, REG_HREF, &v);
+ if (ret)
+ return ret;
v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
msleep(10);
- ret += ov7670_write(sd, REG_HREF, v);
-/*
- * Vertical: similar arrangement, but only 10 bits.
- */
- ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
- ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
- ret += ov7670_read(sd, REG_VREF, &v);
+ ret = ov7670_write(sd, REG_HREF, v);
+ if (ret)
+ return ret;
+ /* Vertical: similar arrangement, but only 10 bits. */
+ ret = ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
+ if (ret)
+ return ret;
+ ret = ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
+ if (ret)
+ return ret;
+ ret = ov7670_read(sd, REG_VREF, &v);
+ if (ret)
+ return ret;
v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
msleep(10);
- ret += ov7670_write(sd, REG_VREF, v);
- return ret;
+ return ov7670_write(sd, REG_VREF, v);
}
@@ -1245,6 +1259,7 @@ static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
*/
for (i = 0; i < n_win_sizes; i++) {
struct ov7670_win_size *win = &info->devtype->win_sizes[i];
+
if (info->min_width && win->width < info->min_width)
continue;
if (info->min_height && win->height < info->min_height)
@@ -1285,17 +1300,17 @@ static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
raw = 0xff;
else
raw = (-1 * matrix[i]) & 0xff;
- }
- else {
+ } else {
if (matrix[i] > 255)
raw = 0xff;
else
raw = matrix[i] & 0xff;
}
- ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
+ ret = ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
+ if (ret)
+ return ret;
}
- ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
- return ret;
+ return ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
}
@@ -1381,11 +1396,9 @@ static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
{
struct ov7670_info *info = to_state(sd);
int matrix[CMATRIX_LEN];
- int ret;
ov7670_calc_cmatrix(info, matrix, sat, hue);
- ret = ov7670_store_cmatrix(sd, matrix);
- return ret;
+ return ov7670_store_cmatrix(sd, matrix);
}
@@ -1403,14 +1416,12 @@ static unsigned char ov7670_abs_to_sm(unsigned char v)
static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
{
unsigned char com8 = 0, v;
- int ret;
ov7670_read(sd, REG_COM8, &com8);
com8 &= ~COM8_AEC;
ov7670_write(sd, REG_COM8, com8);
v = ov7670_abs_to_sm(value);
- ret = ov7670_write(sd, REG_BRIGHT, v);
- return ret;
+ return ov7670_write(sd, REG_BRIGHT, v);
}
static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
@@ -1424,13 +1435,14 @@ static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
int ret;
ret = ov7670_read(sd, REG_MVFP, &v);
+ if (ret)
+ return ret;
if (value)
v |= MVFP_MIRROR;
else
v &= ~MVFP_MIRROR;
msleep(10); /* FIXME */
- ret += ov7670_write(sd, REG_MVFP, v);
- return ret;
+ return ov7670_write(sd, REG_MVFP, v);
}
static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
@@ -1439,13 +1451,14 @@ static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
int ret;
ret = ov7670_read(sd, REG_MVFP, &v);
+ if (ret)
+ return ret;
if (value)
v |= MVFP_FLIP;
else
v &= ~MVFP_FLIP;
msleep(10); /* FIXME */
- ret += ov7670_write(sd, REG_MVFP, v);
- return ret;
+ return ov7670_write(sd, REG_MVFP, v);
}
/*
@@ -1460,8 +1473,10 @@ static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
unsigned char gain;
ret = ov7670_read(sd, REG_GAIN, &gain);
+ if (ret)
+ return ret;
*value = gain;
- return ret;
+ return 0;
}
static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
@@ -1470,12 +1485,13 @@ static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
unsigned char com8;
ret = ov7670_write(sd, REG_GAIN, value & 0xff);
+ if (ret)
+ return ret;
/* Have to turn off AGC as well */
- if (ret == 0) {
- ret = ov7670_read(sd, REG_COM8, &com8);
- ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
- }
- return ret;
+ ret = ov7670_read(sd, REG_COM8, &com8);
+ if (ret)
+ return ret;
+ return ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
}
/*
@@ -1680,13 +1696,13 @@ static int ov7670_s_power(struct v4l2_subdev *sd, int on)
return 0;
if (on) {
- ov7670_power_on (sd);
+ ov7670_power_on(sd);
ov7670_init(sd, 0);
ov7670_apply_fmt(sd);
ov7675_apply_framerate(sd);
v4l2_ctrl_handler_setup(&info->hdl);
} else {
- ov7670_power_off (sd);
+ ov7670_power_off(sd);
}
return 0;
diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c
index 2cc6a678069a..d94cf2d39c2a 100644
--- a/drivers/media/i2c/ov772x.c
+++ b/drivers/media/i2c/ov772x.c
@@ -31,6 +31,7 @@
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-event.h>
+#include <media/v4l2-fwnode.h>
#include <media/v4l2-image-sizes.h>
#include <media/v4l2-subdev.h>
@@ -226,7 +227,7 @@
/* COM3 */
#define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
-#define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
+#define IMG_MASK (VFLIP_IMG | HFLIP_IMG | SCOLOR_TEST)
#define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
#define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
@@ -424,6 +425,7 @@ struct ov772x_priv {
const struct ov772x_win_size *win;
struct v4l2_ctrl *vflip_ctrl;
struct v4l2_ctrl *hflip_ctrl;
+ unsigned int test_pattern;
/* band_filter = COM8[5] ? 256 - BDBASE : 0 */
struct v4l2_ctrl *band_filter_ctrl;
unsigned int fps;
@@ -434,6 +436,7 @@ struct ov772x_priv {
#ifdef CONFIG_MEDIA_CONTROLLER
struct media_pad pad;
#endif
+ enum v4l2_mbus_type bus_type;
};
/*
@@ -538,6 +541,11 @@ static const struct ov772x_win_size ov772x_win_sizes[] = {
},
};
+static const char * const ov772x_test_pattern_menu[] = {
+ "Disabled",
+ "Vertical Color Bar Type 1",
+};
+
/*
* frame rate settings lists
*/
@@ -581,6 +589,14 @@ static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
if (priv->streaming == enable)
goto done;
+ if (priv->bus_type == V4L2_MBUS_BT656) {
+ ret = regmap_update_bits(priv->regmap, COM7, ITU656_ON_OFF,
+ enable ?
+ ITU656_ON_OFF : ~ITU656_ON_OFF);
+ if (ret)
+ goto done;
+ }
+
ret = regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE,
enable ? 0 : SOFT_SLEEP_MODE);
if (ret)
@@ -800,6 +816,9 @@ static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
}
return ret;
+ case V4L2_CID_TEST_PATTERN:
+ priv->test_pattern = ctrl->val;
+ return 0;
}
return -EINVAL;
@@ -1098,6 +1117,8 @@ static int ov772x_set_params(struct ov772x_priv *priv,
val ^= VFLIP_IMG;
if (priv->hflip_ctrl->val)
val ^= HFLIP_IMG;
+ if (priv->test_pattern)
+ val |= SCOLOR_TEST;
ret = regmap_update_bits(priv->regmap, COM3, SWAP_MASK | IMG_MASK, val);
if (ret < 0)
@@ -1348,6 +1369,46 @@ static const struct v4l2_subdev_ops ov772x_subdev_ops = {
.pad = &ov772x_subdev_pad_ops,
};
+static int ov772x_parse_dt(struct i2c_client *client,
+ struct ov772x_priv *priv)
+{
+ struct v4l2_fwnode_endpoint bus_cfg = {
+ .bus_type = V4L2_MBUS_PARALLEL
+ };
+ struct fwnode_handle *ep;
+ int ret;
+
+ ep = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
+ if (!ep) {
+ dev_err(&client->dev, "Endpoint node not found\n");
+ return -EINVAL;
+ }
+
+ /*
+ * For backward compatibility with older DTS where the
+ * bus-type property was not mandatory, assume
+ * V4L2_MBUS_PARALLEL as it was the only supported bus at the
+ * time. v4l2_fwnode_endpoint_alloc_parse() will not fail if
+ * 'bus-type' is not specified.
+ */
+ ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ if (ret) {
+ bus_cfg = (struct v4l2_fwnode_endpoint)
+ { .bus_type = V4L2_MBUS_BT656 };
+ ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ if (ret)
+ goto error_fwnode_put;
+ }
+
+ priv->bus_type = bus_cfg.bus_type;
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+
+error_fwnode_put:
+ fwnode_handle_put(ep);
+
+ return ret;
+}
+
/*
* i2c_driver function
*/
@@ -1394,6 +1455,10 @@ static int ov772x_probe(struct i2c_client *client)
priv->band_filter_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
V4L2_CID_BAND_STOP_FILTER,
0, 256, 1, 0);
+ v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov772x_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ov772x_test_pattern_menu) - 1,
+ 0, 0, ov772x_test_pattern_menu);
priv->subdev.ctrl_handler = &priv->hdl;
if (priv->hdl.error) {
ret = priv->hdl.error;
@@ -1415,6 +1480,10 @@ static int ov772x_probe(struct i2c_client *client)
goto error_clk_put;
}
+ ret = ov772x_parse_dt(client, priv);
+ if (ret)
+ goto error_clk_put;
+
ret = ov772x_video_probe(priv);
if (ret < 0)
goto error_gpio_put;
diff --git a/drivers/media/i2c/ov7740.c b/drivers/media/i2c/ov7740.c
index 5832461c032d..47a9003d29d6 100644
--- a/drivers/media/i2c/ov7740.c
+++ b/drivers/media/i2c/ov7740.c
@@ -1176,8 +1176,7 @@ static int ov7740_remove(struct i2c_client *client)
static int __maybe_unused ov7740_runtime_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
ov7740_set_power(ov7740, 0);
@@ -1187,8 +1186,7 @@ static int __maybe_unused ov7740_runtime_suspend(struct device *dev)
static int __maybe_unused ov7740_runtime_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
return ov7740_set_power(ov7740, 1);
diff --git a/drivers/media/i2c/ov8856.c b/drivers/media/i2c/ov8856.c
index 2f4ceaa80593..d8cefd3d4045 100644
--- a/drivers/media/i2c/ov8856.c
+++ b/drivers/media/i2c/ov8856.c
@@ -1417,8 +1417,7 @@ static void __ov8856_power_off(struct ov8856 *ov8856)
static int __maybe_unused ov8856_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov8856 *ov8856 = to_ov8856(sd);
mutex_lock(&ov8856->mutex);
@@ -1433,8 +1432,7 @@ static int __maybe_unused ov8856_suspend(struct device *dev)
static int __maybe_unused ov8856_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct ov8856 *ov8856 = to_ov8856(sd);
int ret;
diff --git a/drivers/media/i2c/ov9734.c b/drivers/media/i2c/ov9734.c
new file mode 100644
index 000000000000..e212465489e8
--- /dev/null
+++ b/drivers/media/i2c/ov9734.c
@@ -0,0 +1,1020 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 Intel Corporation.
+
+#include <asm/unaligned.h>
+#include <linux/acpi.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-fwnode.h>
+
+#define OV9734_LINK_FREQ_180MHZ 180000000ULL
+#define OV9734_SCLK 36000000LL
+#define OV9734_MCLK 19200000
+/* ov9734 only support 1-lane mipi output */
+#define OV9734_DATA_LANES 1
+#define OV9734_RGB_DEPTH 10
+
+#define OV9734_REG_CHIP_ID 0x300a
+#define OV9734_CHIP_ID 0x9734
+
+#define OV9734_REG_MODE_SELECT 0x0100
+#define OV9734_MODE_STANDBY 0x00
+#define OV9734_MODE_STREAMING 0x01
+
+/* vertical-timings from sensor */
+#define OV9734_REG_VTS 0x380e
+#define OV9734_VTS_30FPS 0x0322
+#define OV9734_VTS_30FPS_MIN 0x0322
+#define OV9734_VTS_MAX 0x7fff
+
+/* horizontal-timings from sensor */
+#define OV9734_REG_HTS 0x380c
+
+/* Exposure controls from sensor */
+#define OV9734_REG_EXPOSURE 0x3500
+#define OV9734_EXPOSURE_MIN 4
+#define OV9734_EXPOSURE_MAX_MARGIN 4
+#define OV9734_EXPOSURE_STEP 1
+
+/* Analog gain controls from sensor */
+#define OV9734_REG_ANALOG_GAIN 0x350a
+#define OV9734_ANAL_GAIN_MIN 16
+#define OV9734_ANAL_GAIN_MAX 248
+#define OV9734_ANAL_GAIN_STEP 1
+
+/* Digital gain controls from sensor */
+#define OV9734_REG_MWB_R_GAIN 0x5180
+#define OV9734_REG_MWB_G_GAIN 0x5182
+#define OV9734_REG_MWB_B_GAIN 0x5184
+#define OV9734_DGTL_GAIN_MIN 256
+#define OV9734_DGTL_GAIN_MAX 1023
+#define OV9734_DGTL_GAIN_STEP 1
+#define OV9734_DGTL_GAIN_DEFAULT 256
+
+/* Test Pattern Control */
+#define OV9734_REG_TEST_PATTERN 0x5080
+#define OV9734_TEST_PATTERN_ENABLE BIT(7)
+#define OV9734_TEST_PATTERN_BAR_SHIFT 2
+
+enum {
+ OV9734_LINK_FREQ_180MHZ_INDEX,
+};
+
+struct ov9734_reg {
+ u16 address;
+ u8 val;
+};
+
+struct ov9734_reg_list {
+ u32 num_of_regs;
+ const struct ov9734_reg *regs;
+};
+
+struct ov9734_link_freq_config {
+ const struct ov9734_reg_list reg_list;
+};
+
+struct ov9734_mode {
+ /* Frame width in pixels */
+ u32 width;
+
+ /* Frame height in pixels */
+ u32 height;
+
+ /* Horizontal timining size */
+ u32 hts;
+
+ /* Default vertical timining size */
+ u32 vts_def;
+
+ /* Min vertical timining size */
+ u32 vts_min;
+
+ /* Link frequency needed for this resolution */
+ u32 link_freq_index;
+
+ /* Sensor register settings for this resolution */
+ const struct ov9734_reg_list reg_list;
+};
+
+static const struct ov9734_reg mipi_data_rate_360mbps[] = {
+ {0x3030, 0x19},
+ {0x3080, 0x02},
+ {0x3081, 0x4b},
+ {0x3082, 0x04},
+ {0x3083, 0x00},
+ {0x3084, 0x02},
+ {0x3085, 0x01},
+ {0x3086, 0x01},
+ {0x3089, 0x01},
+ {0x308a, 0x00},
+ {0x301e, 0x15},
+ {0x3103, 0x01},
+};
+
+static const struct ov9734_reg mode_1296x734_regs[] = {
+ {0x3001, 0x00},
+ {0x3002, 0x00},
+ {0x3007, 0x00},
+ {0x3010, 0x00},
+ {0x3011, 0x08},
+ {0x3014, 0x22},
+ {0x3600, 0x55},
+ {0x3601, 0x02},
+ {0x3605, 0x22},
+ {0x3611, 0xe7},
+ {0x3654, 0x10},
+ {0x3655, 0x77},
+ {0x3656, 0x77},
+ {0x3657, 0x07},
+ {0x3658, 0x22},
+ {0x3659, 0x22},
+ {0x365a, 0x02},
+ {0x3784, 0x05},
+ {0x3785, 0x55},
+ {0x37c0, 0x07},
+ {0x3800, 0x00},
+ {0x3801, 0x04},
+ {0x3802, 0x00},
+ {0x3803, 0x04},
+ {0x3804, 0x05},
+ {0x3805, 0x0b},
+ {0x3806, 0x02},
+ {0x3807, 0xdb},
+ {0x3808, 0x05},
+ {0x3809, 0x00},
+ {0x380a, 0x02},
+ {0x380b, 0xd0},
+ {0x380c, 0x05},
+ {0x380d, 0xc6},
+ {0x380e, 0x03},
+ {0x380f, 0x22},
+ {0x3810, 0x00},
+ {0x3811, 0x04},
+ {0x3812, 0x00},
+ {0x3813, 0x04},
+ {0x3816, 0x00},
+ {0x3817, 0x00},
+ {0x3818, 0x00},
+ {0x3819, 0x04},
+ {0x3820, 0x18},
+ {0x3821, 0x00},
+ {0x382c, 0x06},
+ {0x3500, 0x00},
+ {0x3501, 0x31},
+ {0x3502, 0x00},
+ {0x3503, 0x03},
+ {0x3504, 0x00},
+ {0x3505, 0x00},
+ {0x3509, 0x10},
+ {0x350a, 0x00},
+ {0x350b, 0x40},
+ {0x3d00, 0x00},
+ {0x3d01, 0x00},
+ {0x3d02, 0x00},
+ {0x3d03, 0x00},
+ {0x3d04, 0x00},
+ {0x3d05, 0x00},
+ {0x3d06, 0x00},
+ {0x3d07, 0x00},
+ {0x3d08, 0x00},
+ {0x3d09, 0x00},
+ {0x3d0a, 0x00},
+ {0x3d0b, 0x00},
+ {0x3d0c, 0x00},
+ {0x3d0d, 0x00},
+ {0x3d0e, 0x00},
+ {0x3d0f, 0x00},
+ {0x3d80, 0x00},
+ {0x3d81, 0x00},
+ {0x3d82, 0x38},
+ {0x3d83, 0xa4},
+ {0x3d84, 0x00},
+ {0x3d85, 0x00},
+ {0x3d86, 0x1f},
+ {0x3d87, 0x03},
+ {0x3d8b, 0x00},
+ {0x3d8f, 0x00},
+ {0x4001, 0xe0},
+ {0x4009, 0x0b},
+ {0x4300, 0x03},
+ {0x4301, 0xff},
+ {0x4304, 0x00},
+ {0x4305, 0x00},
+ {0x4309, 0x00},
+ {0x4600, 0x00},
+ {0x4601, 0x80},
+ {0x4800, 0x00},
+ {0x4805, 0x00},
+ {0x4821, 0x50},
+ {0x4823, 0x50},
+ {0x4837, 0x2d},
+ {0x4a00, 0x00},
+ {0x4f00, 0x80},
+ {0x4f01, 0x10},
+ {0x4f02, 0x00},
+ {0x4f03, 0x00},
+ {0x4f04, 0x00},
+ {0x4f05, 0x00},
+ {0x4f06, 0x00},
+ {0x4f07, 0x00},
+ {0x4f08, 0x00},
+ {0x4f09, 0x00},
+ {0x5000, 0x2f},
+ {0x500c, 0x00},
+ {0x500d, 0x00},
+ {0x500e, 0x00},
+ {0x500f, 0x00},
+ {0x5010, 0x00},
+ {0x5011, 0x00},
+ {0x5012, 0x00},
+ {0x5013, 0x00},
+ {0x5014, 0x00},
+ {0x5015, 0x00},
+ {0x5016, 0x00},
+ {0x5017, 0x00},
+ {0x5080, 0x00},
+ {0x5180, 0x01},
+ {0x5181, 0x00},
+ {0x5182, 0x01},
+ {0x5183, 0x00},
+ {0x5184, 0x01},
+ {0x5185, 0x00},
+ {0x5708, 0x06},
+ {0x380f, 0x2a},
+ {0x5780, 0x3e},
+ {0x5781, 0x0f},
+ {0x5782, 0x44},
+ {0x5783, 0x02},
+ {0x5784, 0x01},
+ {0x5785, 0x01},
+ {0x5786, 0x00},
+ {0x5787, 0x04},
+ {0x5788, 0x02},
+ {0x5789, 0x0f},
+ {0x578a, 0xfd},
+ {0x578b, 0xf5},
+ {0x578c, 0xf5},
+ {0x578d, 0x03},
+ {0x578e, 0x08},
+ {0x578f, 0x0c},
+ {0x5790, 0x08},
+ {0x5791, 0x04},
+ {0x5792, 0x00},
+ {0x5793, 0x52},
+ {0x5794, 0xa3},
+ {0x5000, 0x3f},
+ {0x3801, 0x00},
+ {0x3803, 0x00},
+ {0x3805, 0x0f},
+ {0x3807, 0xdf},
+ {0x3809, 0x10},
+ {0x380b, 0xde},
+ {0x3811, 0x00},
+ {0x3813, 0x01},
+};
+
+static const char * const ov9734_test_pattern_menu[] = {
+ "Disabled",
+ "Standard Color Bar",
+ "Top-Bottom Darker Color Bar",
+ "Right-Left Darker Color Bar",
+ "Bottom-Top Darker Color Bar",
+};
+
+static const s64 link_freq_menu_items[] = {
+ OV9734_LINK_FREQ_180MHZ,
+};
+
+static const struct ov9734_link_freq_config link_freq_configs[] = {
+ [OV9734_LINK_FREQ_180MHZ_INDEX] = {
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps),
+ .regs = mipi_data_rate_360mbps,
+ }
+ },
+};
+
+static const struct ov9734_mode supported_modes[] = {
+ {
+ .width = 1296,
+ .height = 734,
+ .hts = 0x5c6,
+ .vts_def = OV9734_VTS_30FPS,
+ .vts_min = OV9734_VTS_30FPS_MIN,
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(mode_1296x734_regs),
+ .regs = mode_1296x734_regs,
+ },
+ .link_freq_index = OV9734_LINK_FREQ_180MHZ_INDEX,
+ },
+};
+
+struct ov9734 {
+ struct v4l2_subdev sd;
+ struct media_pad pad;
+ struct v4l2_ctrl_handler ctrl_handler;
+
+ /* V4L2 Controls */
+ struct v4l2_ctrl *link_freq;
+ struct v4l2_ctrl *pixel_rate;
+ struct v4l2_ctrl *vblank;
+ struct v4l2_ctrl *hblank;
+ struct v4l2_ctrl *exposure;
+
+ /* Current mode */
+ const struct ov9734_mode *cur_mode;
+
+ /* To serialize asynchronus callbacks */
+ struct mutex mutex;
+
+ /* Streaming on/off */
+ bool streaming;
+};
+
+static inline struct ov9734 *to_ov9734(struct v4l2_subdev *subdev)
+{
+ return container_of(subdev, struct ov9734, sd);
+}
+
+static u64 to_pixel_rate(u32 f_index)
+{
+ u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV9734_DATA_LANES;
+
+ do_div(pixel_rate, OV9734_RGB_DEPTH);
+
+ return pixel_rate;
+}
+
+static u64 to_pixels_per_line(u32 hts, u32 f_index)
+{
+ u64 ppl = hts * to_pixel_rate(f_index);
+
+ do_div(ppl, OV9734_SCLK);
+
+ return ppl;
+}
+
+static int ov9734_read_reg(struct ov9734 *ov9734, u16 reg, u16 len, u32 *val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
+ struct i2c_msg msgs[2];
+ u8 addr_buf[2];
+ u8 data_buf[4] = {0};
+ int ret;
+
+ if (len > sizeof(data_buf))
+ return -EINVAL;
+
+ put_unaligned_be16(reg, addr_buf);
+ msgs[0].addr = client->addr;
+ msgs[0].flags = 0;
+ msgs[0].len = sizeof(addr_buf);
+ msgs[0].buf = addr_buf;
+ msgs[1].addr = client->addr;
+ msgs[1].flags = I2C_M_RD;
+ msgs[1].len = len;
+ msgs[1].buf = &data_buf[sizeof(data_buf) - len];
+
+ ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+ if (ret != ARRAY_SIZE(msgs))
+ return ret < 0 ? ret : -EIO;
+
+ *val = get_unaligned_be32(data_buf);
+
+ return 0;
+}
+
+static int ov9734_write_reg(struct ov9734 *ov9734, u16 reg, u16 len, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
+ u8 buf[6];
+ int ret = 0;
+
+ if (len > 4)
+ return -EINVAL;
+
+ put_unaligned_be16(reg, buf);
+ put_unaligned_be32(val << 8 * (4 - len), buf + 2);
+
+ ret = i2c_master_send(client, buf, len + 2);
+ if (ret != len + 2)
+ return ret < 0 ? ret : -EIO;
+
+ return 0;
+}
+
+static int ov9734_write_reg_list(struct ov9734 *ov9734,
+ const struct ov9734_reg_list *r_list)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < r_list->num_of_regs; i++) {
+ ret = ov9734_write_reg(ov9734, r_list->regs[i].address, 1,
+ r_list->regs[i].val);
+ if (ret) {
+ dev_err_ratelimited(&client->dev,
+ "write reg 0x%4.4x return err = %d",
+ r_list->regs[i].address, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int ov9734_update_digital_gain(struct ov9734 *ov9734, u32 d_gain)
+{
+ int ret;
+
+ ret = ov9734_write_reg(ov9734, OV9734_REG_MWB_R_GAIN, 2, d_gain);
+ if (ret)
+ return ret;
+
+ ret = ov9734_write_reg(ov9734, OV9734_REG_MWB_G_GAIN, 2, d_gain);
+ if (ret)
+ return ret;
+
+ return ov9734_write_reg(ov9734, OV9734_REG_MWB_B_GAIN, 2, d_gain);
+}
+
+static int ov9734_test_pattern(struct ov9734 *ov9734, u32 pattern)
+{
+ if (pattern)
+ pattern = (pattern - 1) << OV9734_TEST_PATTERN_BAR_SHIFT |
+ OV9734_TEST_PATTERN_ENABLE;
+
+ return ov9734_write_reg(ov9734, OV9734_REG_TEST_PATTERN, 1, pattern);
+}
+
+static int ov9734_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ov9734 *ov9734 = container_of(ctrl->handler,
+ struct ov9734, ctrl_handler);
+ struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
+ s64 exposure_max;
+ int ret = 0;
+
+ /* Propagate change of current control to all related controls */
+ if (ctrl->id == V4L2_CID_VBLANK) {
+ /* Update max exposure while meeting expected vblanking */
+ exposure_max = ov9734->cur_mode->height + ctrl->val -
+ OV9734_EXPOSURE_MAX_MARGIN;
+ __v4l2_ctrl_modify_range(ov9734->exposure,
+ ov9734->exposure->minimum,
+ exposure_max, ov9734->exposure->step,
+ exposure_max);
+ }
+
+ /* V4L2 controls values will be applied only when power is already up */
+ if (!pm_runtime_get_if_in_use(&client->dev))
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_ANALOGUE_GAIN:
+ ret = ov9734_write_reg(ov9734, OV9734_REG_ANALOG_GAIN,
+ 2, ctrl->val);
+ break;
+
+ case V4L2_CID_DIGITAL_GAIN:
+ ret = ov9734_update_digital_gain(ov9734, ctrl->val);
+ break;
+
+ case V4L2_CID_EXPOSURE:
+ /* 4 least significant bits of expsoure are fractional part */
+ ret = ov9734_write_reg(ov9734, OV9734_REG_EXPOSURE,
+ 3, ctrl->val << 4);
+ break;
+
+ case V4L2_CID_VBLANK:
+ ret = ov9734_write_reg(ov9734, OV9734_REG_VTS, 2,
+ ov9734->cur_mode->height + ctrl->val);
+ break;
+
+ case V4L2_CID_TEST_PATTERN:
+ ret = ov9734_test_pattern(ov9734, ctrl->val);
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ pm_runtime_put(&client->dev);
+
+ return ret;
+}
+
+static const struct v4l2_ctrl_ops ov9734_ctrl_ops = {
+ .s_ctrl = ov9734_set_ctrl,
+};
+
+static int ov9734_init_controls(struct ov9734 *ov9734)
+{
+ struct v4l2_ctrl_handler *ctrl_hdlr;
+ const struct ov9734_mode *cur_mode;
+ s64 exposure_max, h_blank, pixel_rate;
+ u32 vblank_min, vblank_max, vblank_default;
+ int ret, size;
+
+ ctrl_hdlr = &ov9734->ctrl_handler;
+ ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
+ if (ret)
+ return ret;
+
+ ctrl_hdlr->lock = &ov9734->mutex;
+ cur_mode = ov9734->cur_mode;
+ size = ARRAY_SIZE(link_freq_menu_items);
+ ov9734->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov9734_ctrl_ops,
+ V4L2_CID_LINK_FREQ,
+ size - 1, 0,
+ link_freq_menu_items);
+ if (ov9734->link_freq)
+ ov9734->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ pixel_rate = to_pixel_rate(OV9734_LINK_FREQ_180MHZ_INDEX);
+ ov9734->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops,
+ V4L2_CID_PIXEL_RATE, 0,
+ pixel_rate, 1, pixel_rate);
+ vblank_min = cur_mode->vts_min - cur_mode->height;
+ vblank_max = OV9734_VTS_MAX - cur_mode->height;
+ vblank_default = cur_mode->vts_def - cur_mode->height;
+ ov9734->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops,
+ V4L2_CID_VBLANK, vblank_min,
+ vblank_max, 1, vblank_default);
+ h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
+ h_blank -= cur_mode->width;
+ ov9734->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops,
+ V4L2_CID_HBLANK, h_blank, h_blank, 1,
+ h_blank);
+ if (ov9734->hblank)
+ ov9734->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
+ OV9734_ANAL_GAIN_MIN, OV9734_ANAL_GAIN_MAX,
+ OV9734_ANAL_GAIN_STEP, OV9734_ANAL_GAIN_MIN);
+ v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
+ OV9734_DGTL_GAIN_MIN, OV9734_DGTL_GAIN_MAX,
+ OV9734_DGTL_GAIN_STEP, OV9734_DGTL_GAIN_DEFAULT);
+ exposure_max = ov9734->cur_mode->vts_def - OV9734_EXPOSURE_MAX_MARGIN;
+ ov9734->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov9734_ctrl_ops,
+ V4L2_CID_EXPOSURE,
+ OV9734_EXPOSURE_MIN, exposure_max,
+ OV9734_EXPOSURE_STEP,
+ exposure_max);
+ v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov9734_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ov9734_test_pattern_menu) - 1,
+ 0, 0, ov9734_test_pattern_menu);
+ if (ctrl_hdlr->error)
+ return ctrl_hdlr->error;
+
+ ov9734->sd.ctrl_handler = ctrl_hdlr;
+
+ return 0;
+}
+
+static void ov9734_update_pad_format(const struct ov9734_mode *mode,
+ struct v4l2_mbus_framefmt *fmt)
+{
+ fmt->width = mode->width;
+ fmt->height = mode->height;
+ fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
+ fmt->field = V4L2_FIELD_NONE;
+}
+
+static int ov9734_start_streaming(struct ov9734 *ov9734)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
+ const struct ov9734_reg_list *reg_list;
+ int link_freq_index, ret;
+
+ link_freq_index = ov9734->cur_mode->link_freq_index;
+ reg_list = &link_freq_configs[link_freq_index].reg_list;
+ ret = ov9734_write_reg_list(ov9734, reg_list);
+ if (ret) {
+ dev_err(&client->dev, "failed to set plls");
+ return ret;
+ }
+
+ reg_list = &ov9734->cur_mode->reg_list;
+ ret = ov9734_write_reg_list(ov9734, reg_list);
+ if (ret) {
+ dev_err(&client->dev, "failed to set mode");
+ return ret;
+ }
+
+ ret = __v4l2_ctrl_handler_setup(ov9734->sd.ctrl_handler);
+ if (ret)
+ return ret;
+
+ ret = ov9734_write_reg(ov9734, OV9734_REG_MODE_SELECT,
+ 1, OV9734_MODE_STREAMING);
+ if (ret)
+ dev_err(&client->dev, "failed to start stream");
+
+ return ret;
+}
+
+static void ov9734_stop_streaming(struct ov9734 *ov9734)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
+
+ if (ov9734_write_reg(ov9734, OV9734_REG_MODE_SELECT,
+ 1, OV9734_MODE_STANDBY))
+ dev_err(&client->dev, "failed to stop stream");
+}
+
+static int ov9734_set_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct ov9734 *ov9734 = to_ov9734(sd);
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+ int ret = 0;
+
+ mutex_lock(&ov9734->mutex);
+ if (ov9734->streaming == enable) {
+ mutex_unlock(&ov9734->mutex);
+ return 0;
+ }
+
+ if (enable) {
+ ret = pm_runtime_get_sync(&client->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&client->dev);
+ mutex_unlock(&ov9734->mutex);
+ return ret;
+ }
+
+ ret = ov9734_start_streaming(ov9734);
+ if (ret) {
+ enable = 0;
+ ov9734_stop_streaming(ov9734);
+ pm_runtime_put(&client->dev);
+ }
+ } else {
+ ov9734_stop_streaming(ov9734);
+ pm_runtime_put(&client->dev);
+ }
+
+ ov9734->streaming = enable;
+ mutex_unlock(&ov9734->mutex);
+
+ return ret;
+}
+
+static int __maybe_unused ov9734_suspend(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov9734 *ov9734 = to_ov9734(sd);
+
+ mutex_lock(&ov9734->mutex);
+ if (ov9734->streaming)
+ ov9734_stop_streaming(ov9734);
+
+ mutex_unlock(&ov9734->mutex);
+
+ return 0;
+}
+
+static int __maybe_unused ov9734_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov9734 *ov9734 = to_ov9734(sd);
+ int ret = 0;
+
+ mutex_lock(&ov9734->mutex);
+ if (!ov9734->streaming)
+ goto exit;
+
+ ret = ov9734_start_streaming(ov9734);
+ if (ret) {
+ ov9734->streaming = false;
+ ov9734_stop_streaming(ov9734);
+ }
+
+exit:
+ mutex_unlock(&ov9734->mutex);
+ return ret;
+}
+
+static int ov9734_set_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ov9734 *ov9734 = to_ov9734(sd);
+ const struct ov9734_mode *mode;
+ s32 vblank_def, h_blank;
+
+ mode = v4l2_find_nearest_size(supported_modes,
+ ARRAY_SIZE(supported_modes), width,
+ height, fmt->format.width,
+ fmt->format.height);
+
+ mutex_lock(&ov9734->mutex);
+ ov9734_update_pad_format(mode, &fmt->format);
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+ *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
+ } else {
+ ov9734->cur_mode = mode;
+ __v4l2_ctrl_s_ctrl(ov9734->link_freq, mode->link_freq_index);
+ __v4l2_ctrl_s_ctrl_int64(ov9734->pixel_rate,
+ to_pixel_rate(mode->link_freq_index));
+
+ /* Update limits and set FPS to default */
+ vblank_def = mode->vts_def - mode->height;
+ __v4l2_ctrl_modify_range(ov9734->vblank,
+ mode->vts_min - mode->height,
+ OV9734_VTS_MAX - mode->height, 1,
+ vblank_def);
+ __v4l2_ctrl_s_ctrl(ov9734->vblank, vblank_def);
+ h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
+ mode->width;
+ __v4l2_ctrl_modify_range(ov9734->hblank, h_blank, h_blank, 1,
+ h_blank);
+ }
+
+ mutex_unlock(&ov9734->mutex);
+
+ return 0;
+}
+
+static int ov9734_get_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ov9734 *ov9734 = to_ov9734(sd);
+
+ mutex_lock(&ov9734->mutex);
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
+ fmt->format = *v4l2_subdev_get_try_format(&ov9734->sd, cfg,
+ fmt->pad);
+ else
+ ov9734_update_pad_format(ov9734->cur_mode, &fmt->format);
+
+ mutex_unlock(&ov9734->mutex);
+
+ return 0;
+}
+
+static int ov9734_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->index > 0)
+ return -EINVAL;
+
+ code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
+
+ return 0;
+}
+
+static int ov9734_enum_frame_size(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ if (fse->index >= ARRAY_SIZE(supported_modes))
+ return -EINVAL;
+
+ if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
+ return -EINVAL;
+
+ fse->min_width = supported_modes[fse->index].width;
+ fse->max_width = fse->min_width;
+ fse->min_height = supported_modes[fse->index].height;
+ fse->max_height = fse->min_height;
+
+ return 0;
+}
+
+static int ov9734_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ struct ov9734 *ov9734 = to_ov9734(sd);
+
+ mutex_lock(&ov9734->mutex);
+ ov9734_update_pad_format(&supported_modes[0],
+ v4l2_subdev_get_try_format(sd, fh->pad, 0));
+ mutex_unlock(&ov9734->mutex);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_video_ops ov9734_video_ops = {
+ .s_stream = ov9734_set_stream,
+};
+
+static const struct v4l2_subdev_pad_ops ov9734_pad_ops = {
+ .set_fmt = ov9734_set_format,
+ .get_fmt = ov9734_get_format,
+ .enum_mbus_code = ov9734_enum_mbus_code,
+ .enum_frame_size = ov9734_enum_frame_size,
+};
+
+static const struct v4l2_subdev_ops ov9734_subdev_ops = {
+ .video = &ov9734_video_ops,
+ .pad = &ov9734_pad_ops,
+};
+
+static const struct media_entity_operations ov9734_subdev_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct v4l2_subdev_internal_ops ov9734_internal_ops = {
+ .open = ov9734_open,
+};
+
+static int ov9734_identify_module(struct ov9734 *ov9734)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov9734->sd);
+ int ret;
+ u32 val;
+
+ ret = ov9734_read_reg(ov9734, OV9734_REG_CHIP_ID, 2, &val);
+ if (ret)
+ return ret;
+
+ if (val != OV9734_CHIP_ID) {
+ dev_err(&client->dev, "chip id mismatch: %x!=%x",
+ OV9734_CHIP_ID, val);
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static int ov9734_check_hwcfg(struct device *dev)
+{
+ struct fwnode_handle *ep;
+ struct fwnode_handle *fwnode = dev_fwnode(dev);
+ struct v4l2_fwnode_endpoint bus_cfg = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY
+ };
+ u32 mclk;
+ int ret;
+ unsigned int i, j;
+
+ if (!fwnode)
+ return -ENXIO;
+
+ ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
+ if (ret)
+ return ret;
+
+ if (mclk != OV9734_MCLK) {
+ dev_err(dev, "external clock %d is not supported", mclk);
+ return -EINVAL;
+ }
+
+ ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
+ if (!ep)
+ return -ENXIO;
+
+ ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ fwnode_handle_put(ep);
+ if (ret)
+ return ret;
+
+ if (!bus_cfg.nr_of_link_frequencies) {
+ dev_err(dev, "no link frequencies defined");
+ ret = -EINVAL;
+ goto check_hwcfg_error;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
+ for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
+ if (link_freq_menu_items[i] ==
+ bus_cfg.link_frequencies[j])
+ break;
+ }
+
+ if (j == bus_cfg.nr_of_link_frequencies) {
+ dev_err(dev, "no link frequency %lld supported",
+ link_freq_menu_items[i]);
+ ret = -EINVAL;
+ goto check_hwcfg_error;
+ }
+ }
+
+check_hwcfg_error:
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+
+ return ret;
+}
+
+static int ov9734_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov9734 *ov9734 = to_ov9734(sd);
+
+ v4l2_async_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+ v4l2_ctrl_handler_free(sd->ctrl_handler);
+ pm_runtime_disable(&client->dev);
+ mutex_destroy(&ov9734->mutex);
+
+ return 0;
+}
+
+static int ov9734_probe(struct i2c_client *client)
+{
+ struct ov9734 *ov9734;
+ int ret;
+
+ ret = ov9734_check_hwcfg(&client->dev);
+ if (ret) {
+ dev_err(&client->dev, "failed to check HW configuration: %d",
+ ret);
+ return ret;
+ }
+
+ ov9734 = devm_kzalloc(&client->dev, sizeof(*ov9734), GFP_KERNEL);
+ if (!ov9734)
+ return -ENOMEM;
+
+ v4l2_i2c_subdev_init(&ov9734->sd, client, &ov9734_subdev_ops);
+ ret = ov9734_identify_module(ov9734);
+ if (ret) {
+ dev_err(&client->dev, "failed to find sensor: %d", ret);
+ return ret;
+ }
+
+ mutex_init(&ov9734->mutex);
+ ov9734->cur_mode = &supported_modes[0];
+ ret = ov9734_init_controls(ov9734);
+ if (ret) {
+ dev_err(&client->dev, "failed to init controls: %d", ret);
+ goto probe_error_v4l2_ctrl_handler_free;
+ }
+
+ ov9734->sd.internal_ops = &ov9734_internal_ops;
+ ov9734->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ ov9734->sd.entity.ops = &ov9734_subdev_entity_ops;
+ ov9734->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ov9734->pad.flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_pads_init(&ov9734->sd.entity, 1, &ov9734->pad);
+ if (ret) {
+ dev_err(&client->dev, "failed to init entity pads: %d", ret);
+ goto probe_error_v4l2_ctrl_handler_free;
+ }
+
+ ret = v4l2_async_register_subdev_sensor_common(&ov9734->sd);
+ if (ret < 0) {
+ dev_err(&client->dev, "failed to register V4L2 subdev: %d",
+ ret);
+ goto probe_error_media_entity_cleanup;
+ }
+
+ /*
+ * Device is already turned on by i2c-core with ACPI domain PM.
+ * Enable runtime PM and turn off the device.
+ */
+ pm_runtime_set_active(&client->dev);
+ pm_runtime_enable(&client->dev);
+ pm_runtime_idle(&client->dev);
+
+ return 0;
+
+probe_error_media_entity_cleanup:
+ media_entity_cleanup(&ov9734->sd.entity);
+
+probe_error_v4l2_ctrl_handler_free:
+ v4l2_ctrl_handler_free(ov9734->sd.ctrl_handler);
+ mutex_destroy(&ov9734->mutex);
+
+ return ret;
+}
+
+static const struct dev_pm_ops ov9734_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(ov9734_suspend, ov9734_resume)
+};
+
+static const struct acpi_device_id ov9734_acpi_ids[] = {
+ { "OVTI9734", },
+ {}
+};
+
+MODULE_DEVICE_TABLE(acpi, ov9734_acpi_ids);
+
+static struct i2c_driver ov9734_i2c_driver = {
+ .driver = {
+ .name = "ov9734",
+ .pm = &ov9734_pm_ops,
+ .acpi_match_table = ov9734_acpi_ids,
+ },
+ .probe_new = ov9734_probe,
+ .remove = ov9734_remove,
+};
+
+module_i2c_driver(ov9734_i2c_driver);
+
+MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
+MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
+MODULE_DESCRIPTION("OmniVision OV9734 sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/rdacm20.c b/drivers/media/i2c/rdacm20.c
index 1ed928c4ca70..16bcb764b0e0 100644
--- a/drivers/media/i2c/rdacm20.c
+++ b/drivers/media/i2c/rdacm20.c
@@ -487,9 +487,18 @@ static int rdacm20_initialize(struct rdacm20_device *dev)
* Reset the sensor by cycling the OV10635 reset signal connected to the
* MAX9271 GPIO1 and verify communication with the OV10635.
*/
- max9271_clear_gpios(dev->serializer, MAX9271_GPIO1OUT);
+ ret = max9271_enable_gpios(dev->serializer, MAX9271_GPIO1OUT);
+ if (ret)
+ return ret;
+
+ ret = max9271_clear_gpios(dev->serializer, MAX9271_GPIO1OUT);
+ if (ret)
+ return ret;
usleep_range(10000, 15000);
- max9271_set_gpios(dev->serializer, MAX9271_GPIO1OUT);
+
+ ret = max9271_set_gpios(dev->serializer, MAX9271_GPIO1OUT);
+ if (ret)
+ return ret;
usleep_range(10000, 15000);
again:
diff --git a/drivers/media/i2c/smiapp-pll.c b/drivers/media/i2c/smiapp-pll.c
deleted file mode 100644
index 690abe8cbdb2..000000000000
--- a/drivers/media/i2c/smiapp-pll.c
+++ /dev/null
@@ -1,482 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * drivers/media/i2c/smiapp-pll.c
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#include <linux/device.h>
-#include <linux/gcd.h>
-#include <linux/lcm.h>
-#include <linux/module.h>
-
-#include "smiapp-pll.h"
-
-/* Return an even number or one. */
-static inline uint32_t clk_div_even(uint32_t a)
-{
- return max_t(uint32_t, 1, a & ~1);
-}
-
-/* Return an even number or one. */
-static inline uint32_t clk_div_even_up(uint32_t a)
-{
- if (a == 1)
- return 1;
- return (a + 1) & ~1;
-}
-
-static inline uint32_t is_one_or_even(uint32_t a)
-{
- if (a == 1)
- return 1;
- if (a & 1)
- return 0;
-
- return 1;
-}
-
-static int bounds_check(struct device *dev, uint32_t val,
- uint32_t min, uint32_t max, char *str)
-{
- if (val >= min && val <= max)
- return 0;
-
- dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max);
-
- return -EINVAL;
-}
-
-static void print_pll(struct device *dev, struct smiapp_pll *pll)
-{
- dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div);
- dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier);
- if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
- dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div);
- dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div);
- }
- dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div);
- dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div);
-
- dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
- dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
- dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
- if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
- dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
- pll->op.sys_clk_freq_hz);
- dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
- pll->op.pix_clk_freq_hz);
- }
- dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz);
- dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz);
-}
-
-static int check_all_bounds(struct device *dev,
- const struct smiapp_pll_limits *limits,
- const struct smiapp_pll_branch_limits *op_limits,
- struct smiapp_pll *pll,
- struct smiapp_pll_branch *op_pll)
-{
- int rval;
-
- rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
- limits->min_pll_ip_freq_hz,
- limits->max_pll_ip_freq_hz,
- "pll_ip_clk_freq_hz");
- if (!rval)
- rval = bounds_check(
- dev, pll->pll_multiplier,
- limits->min_pll_multiplier, limits->max_pll_multiplier,
- "pll_multiplier");
- if (!rval)
- rval = bounds_check(
- dev, pll->pll_op_clk_freq_hz,
- limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz,
- "pll_op_clk_freq_hz");
- if (!rval)
- rval = bounds_check(
- dev, op_pll->sys_clk_div,
- op_limits->min_sys_clk_div, op_limits->max_sys_clk_div,
- "op_sys_clk_div");
- if (!rval)
- rval = bounds_check(
- dev, op_pll->sys_clk_freq_hz,
- op_limits->min_sys_clk_freq_hz,
- op_limits->max_sys_clk_freq_hz,
- "op_sys_clk_freq_hz");
- if (!rval)
- rval = bounds_check(
- dev, op_pll->pix_clk_freq_hz,
- op_limits->min_pix_clk_freq_hz,
- op_limits->max_pix_clk_freq_hz,
- "op_pix_clk_freq_hz");
-
- /*
- * If there are no OP clocks, the VT clocks are contained in
- * the OP clock struct.
- */
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
- return rval;
-
- if (!rval)
- rval = bounds_check(
- dev, pll->vt.sys_clk_freq_hz,
- limits->vt.min_sys_clk_freq_hz,
- limits->vt.max_sys_clk_freq_hz,
- "vt_sys_clk_freq_hz");
- if (!rval)
- rval = bounds_check(
- dev, pll->vt.pix_clk_freq_hz,
- limits->vt.min_pix_clk_freq_hz,
- limits->vt.max_pix_clk_freq_hz,
- "vt_pix_clk_freq_hz");
-
- return rval;
-}
-
-/*
- * Heuristically guess the PLL tree for a given common multiplier and
- * divisor. Begin with the operational timing and continue to video
- * timing once operational timing has been verified.
- *
- * @mul is the PLL multiplier and @div is the common divisor
- * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
- * multiplier will be a multiple of @mul.
- *
- * @return Zero on success, error code on error.
- */
-static int __smiapp_pll_calculate(
- struct device *dev, const struct smiapp_pll_limits *limits,
- const struct smiapp_pll_branch_limits *op_limits,
- struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul,
- uint32_t div, uint32_t lane_op_clock_ratio)
-{
- uint32_t sys_div;
- uint32_t best_pix_div = INT_MAX >> 1;
- uint32_t vt_op_binning_div;
- /*
- * Higher multipliers (and divisors) are often required than
- * necessitated by the external clock and the output clocks.
- * There are limits for all values in the clock tree. These
- * are the minimum and maximum multiplier for mul.
- */
- uint32_t more_mul_min, more_mul_max;
- uint32_t more_mul_factor;
- uint32_t min_vt_div, max_vt_div, vt_div;
- uint32_t min_sys_div, max_sys_div;
- unsigned int i;
-
- /*
- * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
- * too high.
- */
- dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div);
-
- /* Don't go above max pll multiplier. */
- more_mul_max = limits->max_pll_multiplier / mul;
- dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n",
- more_mul_max);
- /* Don't go above max pll op frequency. */
- more_mul_max =
- min_t(uint32_t,
- more_mul_max,
- limits->max_pll_op_freq_hz
- / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul));
- dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n",
- more_mul_max);
- /* Don't go above the division capability of op sys clock divider. */
- more_mul_max = min(more_mul_max,
- op_limits->max_sys_clk_div * pll->pre_pll_clk_div
- / div);
- dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
- more_mul_max);
- /* Ensure we won't go above min_pll_multiplier. */
- more_mul_max = min(more_mul_max,
- DIV_ROUND_UP(limits->max_pll_multiplier, mul));
- dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
- more_mul_max);
-
- /* Ensure we won't go below min_pll_op_freq_hz. */
- more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz,
- pll->ext_clk_freq_hz / pll->pre_pll_clk_div
- * mul);
- dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n",
- more_mul_min);
- /* Ensure we won't go below min_pll_multiplier. */
- more_mul_min = max(more_mul_min,
- DIV_ROUND_UP(limits->min_pll_multiplier, mul));
- dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n",
- more_mul_min);
-
- if (more_mul_min > more_mul_max) {
- dev_dbg(dev,
- "unable to compute more_mul_min and more_mul_max\n");
- return -EINVAL;
- }
-
- more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
- dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
- more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div);
- dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
- more_mul_factor);
- i = roundup(more_mul_min, more_mul_factor);
- if (!is_one_or_even(i))
- i <<= 1;
-
- dev_dbg(dev, "final more_mul: %u\n", i);
- if (i > more_mul_max) {
- dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
- return -EINVAL;
- }
-
- pll->pll_multiplier = mul * i;
- op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div;
- dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div);
-
- pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
- / pll->pre_pll_clk_div;
-
- pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz
- * pll->pll_multiplier;
-
- /* Derive pll_op_clk_freq_hz. */
- op_pll->sys_clk_freq_hz =
- pll->pll_op_clk_freq_hz / op_pll->sys_clk_div;
-
- op_pll->pix_clk_div = pll->bits_per_pixel;
- dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div);
-
- op_pll->pix_clk_freq_hz =
- op_pll->sys_clk_freq_hz / op_pll->pix_clk_div;
-
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
- /* No OP clocks --- VT clocks are used instead. */
- goto out_skip_vt_calc;
- }
-
- /*
- * Some sensors perform analogue binning and some do this
- * digitally. The ones doing this digitally can be roughly be
- * found out using this formula. The ones doing this digitally
- * should run at higher clock rate, so smaller divisor is used
- * on video timing side.
- */
- if (limits->min_line_length_pck_bin > limits->min_line_length_pck
- / pll->binning_horizontal)
- vt_op_binning_div = pll->binning_horizontal;
- else
- vt_op_binning_div = 1;
- dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
-
- /*
- * Profile 2 supports vt_pix_clk_div E [4, 10]
- *
- * Horizontal binning can be used as a base for difference in
- * divisors. One must make sure that horizontal blanking is
- * enough to accommodate the CSI-2 sync codes.
- *
- * Take scaling factor into account as well.
- *
- * Find absolute limits for the factor of vt divider.
- */
- dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
- min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div
- * pll->scale_n,
- lane_op_clock_ratio * vt_op_binning_div
- * pll->scale_m);
-
- /* Find smallest and biggest allowed vt divisor. */
- dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
- min_vt_div = max(min_vt_div,
- DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
- limits->vt.max_pix_clk_freq_hz));
- dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
- min_vt_div);
- min_vt_div = max_t(uint32_t, min_vt_div,
- limits->vt.min_pix_clk_div
- * limits->vt.min_sys_clk_div);
- dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
-
- max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;
- dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
- max_vt_div = min(max_vt_div,
- DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
- limits->vt.min_pix_clk_freq_hz));
- dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
- max_vt_div);
-
- /*
- * Find limitsits for sys_clk_div. Not all values are possible
- * with all values of pix_clk_div.
- */
- min_sys_div = limits->vt.min_sys_clk_div;
- dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
- min_sys_div = max(min_sys_div,
- DIV_ROUND_UP(min_vt_div,
- limits->vt.max_pix_clk_div));
- dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
- min_sys_div = max(min_sys_div,
- pll->pll_op_clk_freq_hz
- / limits->vt.max_sys_clk_freq_hz);
- dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
- min_sys_div = clk_div_even_up(min_sys_div);
- dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
-
- max_sys_div = limits->vt.max_sys_clk_div;
- dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
- max_sys_div = min(max_sys_div,
- DIV_ROUND_UP(max_vt_div,
- limits->vt.min_pix_clk_div));
- dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
- max_sys_div = min(max_sys_div,
- DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
- limits->vt.min_pix_clk_freq_hz));
- dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
-
- /*
- * Find pix_div such that a legal pix_div * sys_div results
- * into a value which is not smaller than div, the desired
- * divisor.
- */
- for (vt_div = min_vt_div; vt_div <= max_vt_div;
- vt_div += 2 - (vt_div & 1)) {
- for (sys_div = min_sys_div;
- sys_div <= max_sys_div;
- sys_div += 2 - (sys_div & 1)) {
- uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
-
- if (pix_div < limits->vt.min_pix_clk_div
- || pix_div > limits->vt.max_pix_clk_div) {
- dev_dbg(dev,
- "pix_div %u too small or too big (%u--%u)\n",
- pix_div,
- limits->vt.min_pix_clk_div,
- limits->vt.max_pix_clk_div);
- continue;
- }
-
- /* Check if this one is better. */
- if (pix_div * sys_div
- <= roundup(min_vt_div, best_pix_div))
- best_pix_div = pix_div;
- }
- if (best_pix_div < INT_MAX >> 1)
- break;
- }
-
- pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
- pll->vt.pix_clk_div = best_pix_div;
-
- pll->vt.sys_clk_freq_hz =
- pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div;
- pll->vt.pix_clk_freq_hz =
- pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div;
-
-out_skip_vt_calc:
- pll->pixel_rate_csi =
- op_pll->pix_clk_freq_hz * lane_op_clock_ratio;
- pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz;
-
- return check_all_bounds(dev, limits, op_limits, pll, op_pll);
-}
-
-int smiapp_pll_calculate(struct device *dev,
- const struct smiapp_pll_limits *limits,
- struct smiapp_pll *pll)
-{
- const struct smiapp_pll_branch_limits *op_limits = &limits->op;
- struct smiapp_pll_branch *op_pll = &pll->op;
- uint16_t min_pre_pll_clk_div;
- uint16_t max_pre_pll_clk_div;
- uint32_t lane_op_clock_ratio;
- uint32_t mul, div;
- unsigned int i;
- int rval = -EINVAL;
-
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
- /*
- * If there's no OP PLL at all, use the VT values
- * instead. The OP values are ignored for the rest of
- * the PLL calculation.
- */
- op_limits = &limits->vt;
- op_pll = &pll->vt;
- }
-
- if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
- lane_op_clock_ratio = pll->csi2.lanes;
- else
- lane_op_clock_ratio = 1;
- dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio);
-
- dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
- pll->binning_vertical);
-
- switch (pll->bus_type) {
- case SMIAPP_PLL_BUS_TYPE_CSI2:
- /* CSI transfers 2 bits per clock per lane; thus times 2 */
- pll->pll_op_clk_freq_hz = pll->link_freq * 2
- * (pll->csi2.lanes / lane_op_clock_ratio);
- break;
- case SMIAPP_PLL_BUS_TYPE_PARALLEL:
- pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
- / DIV_ROUND_UP(pll->bits_per_pixel,
- pll->parallel.bus_width);
- break;
- default:
- return -EINVAL;
- }
-
- /* Figure out limits for pre-pll divider based on extclk */
- dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n",
- limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
- max_pre_pll_clk_div =
- min_t(uint16_t, limits->max_pre_pll_clk_div,
- clk_div_even(pll->ext_clk_freq_hz /
- limits->min_pll_ip_freq_hz));
- min_pre_pll_clk_div =
- max_t(uint16_t, limits->min_pre_pll_clk_div,
- clk_div_even_up(
- DIV_ROUND_UP(pll->ext_clk_freq_hz,
- limits->max_pll_ip_freq_hz)));
- dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n",
- min_pre_pll_clk_div, max_pre_pll_clk_div);
-
- i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
- mul = div_u64(pll->pll_op_clk_freq_hz, i);
- div = pll->ext_clk_freq_hz / i;
- dev_dbg(dev, "mul %u / div %u\n", mul, div);
-
- min_pre_pll_clk_div =
- max_t(uint16_t, min_pre_pll_clk_div,
- clk_div_even_up(
- DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
- limits->max_pll_op_freq_hz)));
- dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n",
- min_pre_pll_clk_div, max_pre_pll_clk_div);
-
- for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
- pll->pre_pll_clk_div <= max_pre_pll_clk_div;
- pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
- rval = __smiapp_pll_calculate(dev, limits, op_limits, pll,
- op_pll, mul, div,
- lane_op_clock_ratio);
- if (rval)
- continue;
-
- print_pll(dev, pll);
- return 0;
- }
-
- dev_dbg(dev, "unable to compute pre_pll divisor\n");
-
- return rval;
-}
-EXPORT_SYMBOL_GPL(smiapp_pll_calculate);
-
-MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
-MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator");
-MODULE_LICENSE("GPL");
diff --git a/drivers/media/i2c/smiapp-pll.h b/drivers/media/i2c/smiapp-pll.h
deleted file mode 100644
index bd6902f54539..000000000000
--- a/drivers/media/i2c/smiapp-pll.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * drivers/media/i2c/smiapp-pll.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#ifndef SMIAPP_PLL_H
-#define SMIAPP_PLL_H
-
-/* CSI-2 or CCP-2 */
-#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00
-#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01
-
-/* op pix clock is for all lanes in total normally */
-#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
-#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
-
-struct smiapp_pll_branch {
- uint16_t sys_clk_div;
- uint16_t pix_clk_div;
- uint32_t sys_clk_freq_hz;
- uint32_t pix_clk_freq_hz;
-};
-
-struct smiapp_pll {
- /* input values */
- uint8_t bus_type;
- union {
- struct {
- uint8_t lanes;
- } csi2;
- struct {
- uint8_t bus_width;
- } parallel;
- };
- unsigned long flags;
- uint8_t binning_horizontal;
- uint8_t binning_vertical;
- uint8_t scale_m;
- uint8_t scale_n;
- uint8_t bits_per_pixel;
- uint32_t link_freq;
- uint32_t ext_clk_freq_hz;
-
- /* output values */
- uint16_t pre_pll_clk_div;
- uint16_t pll_multiplier;
- uint32_t pll_ip_clk_freq_hz;
- uint32_t pll_op_clk_freq_hz;
- struct smiapp_pll_branch vt;
- struct smiapp_pll_branch op;
-
- uint32_t pixel_rate_csi;
- uint32_t pixel_rate_pixel_array;
-};
-
-struct smiapp_pll_branch_limits {
- uint16_t min_sys_clk_div;
- uint16_t max_sys_clk_div;
- uint32_t min_sys_clk_freq_hz;
- uint32_t max_sys_clk_freq_hz;
- uint16_t min_pix_clk_div;
- uint16_t max_pix_clk_div;
- uint32_t min_pix_clk_freq_hz;
- uint32_t max_pix_clk_freq_hz;
-};
-
-struct smiapp_pll_limits {
- /* Strict PLL limits */
- uint32_t min_ext_clk_freq_hz;
- uint32_t max_ext_clk_freq_hz;
- uint16_t min_pre_pll_clk_div;
- uint16_t max_pre_pll_clk_div;
- uint32_t min_pll_ip_freq_hz;
- uint32_t max_pll_ip_freq_hz;
- uint16_t min_pll_multiplier;
- uint16_t max_pll_multiplier;
- uint32_t min_pll_op_freq_hz;
- uint32_t max_pll_op_freq_hz;
-
- struct smiapp_pll_branch_limits vt;
- struct smiapp_pll_branch_limits op;
-
- /* Other relevant limits */
- uint32_t min_line_length_pck_bin;
- uint32_t min_line_length_pck;
-};
-
-struct device;
-
-int smiapp_pll_calculate(struct device *dev,
- const struct smiapp_pll_limits *limits,
- struct smiapp_pll *pll);
-
-#endif /* SMIAPP_PLL_H */
diff --git a/drivers/media/i2c/smiapp/Kconfig b/drivers/media/i2c/smiapp/Kconfig
deleted file mode 100644
index 6893b532824f..000000000000
--- a/drivers/media/i2c/smiapp/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-config VIDEO_SMIAPP
- tristate "SMIA++/SMIA sensor support"
- depends on I2C && VIDEO_V4L2 && HAVE_CLK
- select MEDIA_CONTROLLER
- select VIDEO_V4L2_SUBDEV_API
- select VIDEO_SMIAPP_PLL
- select V4L2_FWNODE
- help
- This is a generic driver for SMIA++/SMIA camera modules.
diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
deleted file mode 100644
index 86f57a43f8e8..000000000000
--- a/drivers/media/i2c/smiapp/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-smiapp-objs += smiapp-core.o smiapp-regs.o \
- smiapp-quirk.o smiapp-limits.o
-obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
-
-ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
deleted file mode 100644
index 6fc0680a93d0..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ /dev/null
@@ -1,3175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * drivers/media/i2c/smiapp/smiapp-core.c
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2010--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- *
- * Based on smiapp driver by Vimarsh Zutshi
- * Based on jt8ev1.c by Vimarsh Zutshi
- * Based on smia-sensor.c by Tuukka Toivonen <tuukkat76@gmail.com>
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/gpio.h>
-#include <linux/gpio/consumer.h>
-#include <linux/module.h>
-#include <linux/pm_runtime.h>
-#include <linux/property.h>
-#include <linux/regulator/consumer.h>
-#include <linux/slab.h>
-#include <linux/smiapp.h>
-#include <linux/v4l2-mediabus.h>
-#include <media/v4l2-fwnode.h>
-#include <media/v4l2-device.h>
-
-#include "smiapp.h"
-
-#define SMIAPP_ALIGN_DIM(dim, flags) \
- ((flags) & V4L2_SEL_FLAG_GE \
- ? ALIGN((dim), 2) \
- : (dim) & ~1)
-
-/*
- * smiapp_module_idents - supported camera modules
- */
-static const struct smiapp_module_ident smiapp_module_idents[] = {
- SMIAPP_IDENT_L(0x01, 0x022b, -1, "vs6555"),
- SMIAPP_IDENT_L(0x01, 0x022e, -1, "vw6558"),
- SMIAPP_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
- SMIAPP_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"),
- SMIAPP_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"),
- SMIAPP_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk),
- SMIAPP_IDENT_L(0x0c, 0x213e, -1, "et8en2"),
- SMIAPP_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"),
- SMIAPP_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk),
- SMIAPP_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk),
- SMIAPP_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
-};
-
-/*
- *
- * Dynamic Capability Identification
- *
- */
-
-static u32 smiapp_get_limit(struct smiapp_sensor *sensor,
- unsigned int limit)
-{
- if (WARN_ON(limit >= SMIAPP_LIMIT_LAST))
- return 1;
-
- return sensor->limits[limit];
-}
-
-#define SMIA_LIM(sensor, limit) \
- smiapp_get_limit(sensor, SMIAPP_LIMIT_##limit)
-
-static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- unsigned int i;
- int rval;
-
- for (i = 0; i < SMIAPP_LIMIT_LAST; i++) {
- u32 val;
-
- rval = smiapp_read(
- sensor, smiapp_reg_limits[i].addr, &val);
- if (rval)
- return rval;
-
- sensor->limits[i] = val;
-
- dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
- smiapp_reg_limits[i].addr,
- smiapp_reg_limits[i].what, val, val);
- }
-
- if (SMIA_LIM(sensor, SCALER_N_MIN) == 0)
- smiapp_replace_limit(sensor, SMIAPP_LIMIT_SCALER_N_MIN, 16);
-
- return 0;
-}
-
-static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- u32 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
- unsigned int i;
- int pixel_count = 0;
- int line_count = 0;
- int rval;
-
- rval = smiapp_read(sensor, SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE,
- &fmt_model_type);
- if (rval)
- return rval;
-
- rval = smiapp_read(sensor, SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE,
- &fmt_model_subtype);
- if (rval)
- return rval;
-
- ncol_desc = (fmt_model_subtype
- & SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK)
- >> SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT;
- nrow_desc = fmt_model_subtype
- & SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK;
-
- dev_dbg(&client->dev, "format_model_type %s\n",
- fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE
- ? "2 byte" :
- fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE
- ? "4 byte" : "is simply bad");
-
- for (i = 0; i < ncol_desc + nrow_desc; i++) {
- u32 desc;
- u32 pixelcode;
- u32 pixels;
- char *which;
- char *what;
- u32 reg;
-
- if (fmt_model_type == SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE) {
- reg = SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(i);
- rval = smiapp_read(sensor, reg, &desc);
- if (rval)
- return rval;
-
- pixelcode =
- (desc
- & SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK)
- >> SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT;
- pixels = desc & SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK;
- } else if (fmt_model_type
- == SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE) {
- reg = SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(i);
- rval = smiapp_read(sensor, reg, &desc);
- if (rval)
- return rval;
-
- pixelcode =
- (desc
- & SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK)
- >> SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT;
- pixels = desc & SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK;
- } else {
- dev_dbg(&client->dev,
- "invalid frame format model type %d\n",
- fmt_model_type);
- return -EINVAL;
- }
-
- if (i < ncol_desc)
- which = "columns";
- else
- which = "rows";
-
- switch (pixelcode) {
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED:
- what = "embedded";
- break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY:
- what = "dummy";
- break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK:
- what = "black";
- break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK:
- what = "dark";
- break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE:
- what = "visible";
- break;
- default:
- what = "invalid";
- break;
- }
-
- dev_dbg(&client->dev,
- "0x%8.8x %s pixels: %d %s (pixelcode %u)\n", reg,
- what, pixels, which, pixelcode);
-
- if (i < ncol_desc) {
- if (pixelcode ==
- SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE)
- sensor->visible_pixel_start = pixel_count;
- pixel_count += pixels;
- continue;
- }
-
- /* Handle row descriptors */
- switch (pixelcode) {
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED:
- if (sensor->embedded_end)
- break;
- sensor->embedded_start = line_count;
- sensor->embedded_end = line_count + pixels;
- break;
- case SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE:
- sensor->image_start = line_count;
- break;
- }
- line_count += pixels;
- }
-
- if (sensor->embedded_end > sensor->image_start) {
- dev_dbg(&client->dev,
- "adjusting image start line to %u (was %u)\n",
- sensor->embedded_end, sensor->image_start);
- sensor->image_start = sensor->embedded_end;
- }
-
- dev_dbg(&client->dev, "embedded data from lines %d to %d\n",
- sensor->embedded_start, sensor->embedded_end);
- dev_dbg(&client->dev, "image data starts at line %d\n",
- sensor->image_start);
-
- return 0;
-}
-
-static int smiapp_pll_configure(struct smiapp_sensor *sensor)
-{
- struct smiapp_pll *pll = &sensor->pll;
- int rval;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
- if (rval < 0)
- return rval;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
- if (rval < 0)
- return rval;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div);
- if (rval < 0)
- return rval;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier);
- if (rval < 0)
- return rval;
-
- /* Lane op clock ratio does not apply here. */
- rval = smiapp_write(
- sensor, SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS,
- DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256));
- if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
- return rval;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div);
- if (rval < 0)
- return rval;
-
- return smiapp_write(
- sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div);
-}
-
-static int smiapp_pll_try(struct smiapp_sensor *sensor,
- struct smiapp_pll *pll)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_pll_limits lim = {
- .min_pre_pll_clk_div = SMIA_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
- .max_pre_pll_clk_div = SMIA_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
- .min_pll_ip_freq_hz = SMIA_LIM(sensor, MIN_PLL_IP_FREQ_HZ),
- .max_pll_ip_freq_hz = SMIA_LIM(sensor, MAX_PLL_IP_FREQ_HZ),
- .min_pll_multiplier = SMIA_LIM(sensor, MIN_PLL_MULTIPLIER),
- .max_pll_multiplier = SMIA_LIM(sensor, MAX_PLL_MULTIPLIER),
- .min_pll_op_freq_hz = SMIA_LIM(sensor, MIN_PLL_OP_FREQ_HZ),
- .max_pll_op_freq_hz = SMIA_LIM(sensor, MAX_PLL_OP_FREQ_HZ),
-
- .op.min_sys_clk_div = SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV),
- .op.max_sys_clk_div = SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV),
- .op.min_pix_clk_div = SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV),
- .op.max_pix_clk_div = SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV),
- .op.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_SYS_CLK_FREQ_HZ),
- .op.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_SYS_CLK_FREQ_HZ),
- .op.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_PIX_CLK_FREQ_HZ),
- .op.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_PIX_CLK_FREQ_HZ),
-
- .vt.min_sys_clk_div = SMIA_LIM(sensor, MIN_VT_SYS_CLK_DIV),
- .vt.max_sys_clk_div = SMIA_LIM(sensor, MAX_VT_SYS_CLK_DIV),
- .vt.min_pix_clk_div = SMIA_LIM(sensor, MIN_VT_PIX_CLK_DIV),
- .vt.max_pix_clk_div = SMIA_LIM(sensor, MAX_VT_PIX_CLK_DIV),
- .vt.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_SYS_CLK_FREQ_HZ),
- .vt.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_SYS_CLK_FREQ_HZ),
- .vt.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_PIX_CLK_FREQ_HZ),
- .vt.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_PIX_CLK_FREQ_HZ),
-
- .min_line_length_pck_bin = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
- .min_line_length_pck = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK),
- };
-
- return smiapp_pll_calculate(&client->dev, &lim, pll);
-}
-
-static int smiapp_pll_update(struct smiapp_sensor *sensor)
-{
- struct smiapp_pll *pll = &sensor->pll;
- int rval;
-
- pll->binning_horizontal = sensor->binning_horizontal;
- pll->binning_vertical = sensor->binning_vertical;
- pll->link_freq =
- sensor->link_freq->qmenu_int[sensor->link_freq->val];
- pll->scale_m = sensor->scale_m;
- pll->bits_per_pixel = sensor->csi_format->compressed;
-
- rval = smiapp_pll_try(sensor, pll);
- if (rval < 0)
- return rval;
-
- __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_parray,
- pll->pixel_rate_pixel_array);
- __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_csi, pll->pixel_rate_csi);
-
- return 0;
-}
-
-
-/*
- *
- * V4L2 Controls handling
- *
- */
-
-static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor)
-{
- struct v4l2_ctrl *ctrl = sensor->exposure;
- int max;
-
- max = sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
- + sensor->vblank->val
- - SMIA_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
-
- __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, ctrl->step, max);
-}
-
-/*
- * Order matters.
- *
- * 1. Bits-per-pixel, descending.
- * 2. Bits-per-pixel compressed, descending.
- * 3. Pixel order, same as in pixel_order_str. Formats for all four pixel
- * orders must be defined.
- */
-static const struct smiapp_csi_data_format smiapp_csi_data_formats[] = {
- { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, SMIAPP_PIXEL_ORDER_GBRG, },
- { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_GRBG, },
- { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_RGGB, },
- { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_BGGR, },
- { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, SMIAPP_PIXEL_ORDER_GBRG, },
-};
-
-static const char *pixel_order_str[] = { "GRBG", "RGGB", "BGGR", "GBRG" };
-
-#define to_csi_format_idx(fmt) (((unsigned long)(fmt) \
- - (unsigned long)smiapp_csi_data_formats) \
- / sizeof(*smiapp_csi_data_formats))
-
-static u32 smiapp_pixel_order(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int flip = 0;
-
- if (sensor->hflip) {
- if (sensor->hflip->val)
- flip |= SMIAPP_IMAGE_ORIENTATION_HFLIP;
-
- if (sensor->vflip->val)
- flip |= SMIAPP_IMAGE_ORIENTATION_VFLIP;
- }
-
- flip ^= sensor->hvflip_inv_mask;
-
- dev_dbg(&client->dev, "flip %d\n", flip);
- return sensor->default_pixel_order ^ flip;
-}
-
-static void smiapp_update_mbus_formats(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- unsigned int csi_format_idx =
- to_csi_format_idx(sensor->csi_format) & ~3;
- unsigned int internal_csi_format_idx =
- to_csi_format_idx(sensor->internal_csi_format) & ~3;
- unsigned int pixel_order = smiapp_pixel_order(sensor);
-
- sensor->mbus_frame_fmts =
- sensor->default_mbus_frame_fmts << pixel_order;
- sensor->csi_format =
- &smiapp_csi_data_formats[csi_format_idx + pixel_order];
- sensor->internal_csi_format =
- &smiapp_csi_data_formats[internal_csi_format_idx
- + pixel_order];
-
- BUG_ON(max(internal_csi_format_idx, csi_format_idx) + pixel_order
- >= ARRAY_SIZE(smiapp_csi_data_formats));
-
- dev_dbg(&client->dev, "new pixel order %s\n",
- pixel_order_str[pixel_order]);
-}
-
-static const char * const smiapp_test_patterns[] = {
- "Disabled",
- "Solid Colour",
- "Eight Vertical Colour Bars",
- "Colour Bars With Fade to Grey",
- "Pseudorandom Sequence (PN9)",
-};
-
-static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
-{
- struct smiapp_sensor *sensor =
- container_of(ctrl->handler, struct smiapp_subdev, ctrl_handler)
- ->sensor;
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int pm_status;
- u32 orient = 0;
- unsigned int i;
- int exposure;
- int rval;
-
- switch (ctrl->id) {
- case V4L2_CID_HFLIP:
- case V4L2_CID_VFLIP:
- if (sensor->streaming)
- return -EBUSY;
-
- if (sensor->hflip->val)
- orient |= SMIAPP_IMAGE_ORIENTATION_HFLIP;
-
- if (sensor->vflip->val)
- orient |= SMIAPP_IMAGE_ORIENTATION_VFLIP;
-
- orient ^= sensor->hvflip_inv_mask;
-
- smiapp_update_mbus_formats(sensor);
-
- break;
- case V4L2_CID_VBLANK:
- exposure = sensor->exposure->val;
-
- __smiapp_update_exposure_limits(sensor);
-
- if (exposure > sensor->exposure->maximum) {
- sensor->exposure->val = sensor->exposure->maximum;
- rval = smiapp_set_ctrl(sensor->exposure);
- if (rval < 0)
- return rval;
- }
-
- break;
- case V4L2_CID_LINK_FREQ:
- if (sensor->streaming)
- return -EBUSY;
-
- rval = smiapp_pll_update(sensor);
- if (rval)
- return rval;
-
- return 0;
- case V4L2_CID_TEST_PATTERN:
- for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++)
- v4l2_ctrl_activate(
- sensor->test_data[i],
- ctrl->val ==
- V4L2_SMIAPP_TEST_PATTERN_MODE_SOLID_COLOUR);
-
- break;
- }
-
- pm_status = pm_runtime_get_if_active(&client->dev, true);
- if (!pm_status)
- return 0;
-
- switch (ctrl->id) {
- case V4L2_CID_ANALOGUE_GAIN:
- rval = smiapp_write(
- sensor,
- SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL, ctrl->val);
-
- break;
- case V4L2_CID_EXPOSURE:
- rval = smiapp_write(
- sensor,
- SMIAPP_REG_U16_COARSE_INTEGRATION_TIME, ctrl->val);
-
- break;
- case V4L2_CID_HFLIP:
- case V4L2_CID_VFLIP:
- rval = smiapp_write(sensor, SMIAPP_REG_U8_IMAGE_ORIENTATION,
- orient);
-
- break;
- case V4L2_CID_VBLANK:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_FRAME_LENGTH_LINES,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
- + ctrl->val);
-
- break;
- case V4L2_CID_HBLANK:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_LINE_LENGTH_PCK,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width
- + ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_PATTERN_MODE, ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN_RED:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_RED, ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN_GREENR:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_GREENR, ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN_BLUE:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_BLUE, ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN_GREENB:
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TEST_DATA_GREENB, ctrl->val);
-
- break;
- case V4L2_CID_PIXEL_RATE:
- /* For v4l2_ctrl_s_ctrl_int64() used internally. */
- rval = 0;
-
- break;
- default:
- rval = -EINVAL;
- }
-
- if (pm_status > 0) {
- pm_runtime_mark_last_busy(&client->dev);
- pm_runtime_put_autosuspend(&client->dev);
- }
-
- return rval;
-}
-
-static const struct v4l2_ctrl_ops smiapp_ctrl_ops = {
- .s_ctrl = smiapp_set_ctrl,
-};
-
-static int smiapp_init_controls(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int rval;
-
- rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 12);
- if (rval)
- return rval;
-
- sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
-
- sensor->analog_gain = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_ANALOGUE_GAIN,
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN),
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MAX),
- max(SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_STEP), 1U),
- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN));
-
- /* Exposure limits will be updated soon, use just something here. */
- sensor->exposure = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_EXPOSURE, 0, 0, 1, 0);
-
- sensor->hflip = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_HFLIP, 0, 1, 1, 0);
- sensor->vflip = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_VFLIP, 0, 1, 1, 0);
-
- sensor->vblank = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_VBLANK, 0, 1, 1, 0);
-
- if (sensor->vblank)
- sensor->vblank->flags |= V4L2_CTRL_FLAG_UPDATE;
-
- sensor->hblank = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_HBLANK, 0, 1, 1, 0);
-
- if (sensor->hblank)
- sensor->hblank->flags |= V4L2_CTRL_FLAG_UPDATE;
-
- sensor->pixel_rate_parray = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
-
- v4l2_ctrl_new_std_menu_items(&sensor->pixel_array->ctrl_handler,
- &smiapp_ctrl_ops, V4L2_CID_TEST_PATTERN,
- ARRAY_SIZE(smiapp_test_patterns) - 1,
- 0, 0, smiapp_test_patterns);
-
- if (sensor->pixel_array->ctrl_handler.error) {
- dev_err(&client->dev,
- "pixel array controls initialization failed (%d)\n",
- sensor->pixel_array->ctrl_handler.error);
- return sensor->pixel_array->ctrl_handler.error;
- }
-
- sensor->pixel_array->sd.ctrl_handler =
- &sensor->pixel_array->ctrl_handler;
-
- v4l2_ctrl_cluster(2, &sensor->hflip);
-
- rval = v4l2_ctrl_handler_init(&sensor->src->ctrl_handler, 0);
- if (rval)
- return rval;
-
- sensor->src->ctrl_handler.lock = &sensor->mutex;
-
- sensor->pixel_rate_csi = v4l2_ctrl_new_std(
- &sensor->src->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
-
- if (sensor->src->ctrl_handler.error) {
- dev_err(&client->dev,
- "src controls initialization failed (%d)\n",
- sensor->src->ctrl_handler.error);
- return sensor->src->ctrl_handler.error;
- }
-
- sensor->src->sd.ctrl_handler = &sensor->src->ctrl_handler;
-
- return 0;
-}
-
-/*
- * For controls that require information on available media bus codes
- * and linke frequencies.
- */
-static int smiapp_init_late_controls(struct smiapp_sensor *sensor)
-{
- unsigned long *valid_link_freqs = &sensor->valid_link_freqs[
- sensor->csi_format->compressed - sensor->compressed_min_bpp];
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++) {
- int max_value = (1 << sensor->csi_format->width) - 1;
-
- sensor->test_data[i] = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler,
- &smiapp_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i,
- 0, max_value, 1, max_value);
- }
-
- sensor->link_freq = v4l2_ctrl_new_int_menu(
- &sensor->src->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs),
- __ffs(*valid_link_freqs), sensor->hwcfg->op_sys_clock);
-
- return sensor->src->ctrl_handler.error;
-}
-
-static void smiapp_free_controls(struct smiapp_sensor *sensor)
-{
- unsigned int i;
-
- for (i = 0; i < sensor->ssds_used; i++)
- v4l2_ctrl_handler_free(&sensor->ssds[i].ctrl_handler);
-}
-
-static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_pll *pll = &sensor->pll;
- u8 compressed_max_bpp = 0;
- unsigned int type, n;
- unsigned int i, pixel_order;
- int rval;
-
- rval = smiapp_read(
- sensor, SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE, &type);
- if (rval)
- return rval;
-
- dev_dbg(&client->dev, "data_format_model_type %d\n", type);
-
- rval = smiapp_read(sensor, SMIAPP_REG_U8_PIXEL_ORDER,
- &pixel_order);
- if (rval)
- return rval;
-
- if (pixel_order >= ARRAY_SIZE(pixel_order_str)) {
- dev_dbg(&client->dev, "bad pixel order %d\n", pixel_order);
- return -EINVAL;
- }
-
- dev_dbg(&client->dev, "pixel order %d (%s)\n", pixel_order,
- pixel_order_str[pixel_order]);
-
- switch (type) {
- case SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL:
- n = SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N;
- break;
- case SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED:
- n = SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N;
- break;
- default:
- return -EINVAL;
- }
-
- sensor->default_pixel_order = pixel_order;
- sensor->mbus_frame_fmts = 0;
-
- for (i = 0; i < n; i++) {
- unsigned int fmt, j;
-
- rval = smiapp_read(
- sensor,
- SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(i), &fmt);
- if (rval)
- return rval;
-
- dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n",
- i, fmt >> 8, (u8)fmt);
-
- for (j = 0; j < ARRAY_SIZE(smiapp_csi_data_formats); j++) {
- const struct smiapp_csi_data_format *f =
- &smiapp_csi_data_formats[j];
-
- if (f->pixel_order != SMIAPP_PIXEL_ORDER_GRBG)
- continue;
-
- if (f->width != fmt >> 8 || f->compressed != (u8)fmt)
- continue;
-
- dev_dbg(&client->dev, "jolly good! %d\n", j);
-
- sensor->default_mbus_frame_fmts |= 1 << j;
- }
- }
-
- /* Figure out which BPP values can be used with which formats. */
- pll->binning_horizontal = 1;
- pll->binning_vertical = 1;
- pll->scale_m = sensor->scale_m;
-
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
- sensor->compressed_min_bpp =
- min(smiapp_csi_data_formats[i].compressed,
- sensor->compressed_min_bpp);
- compressed_max_bpp =
- max(smiapp_csi_data_formats[i].compressed,
- compressed_max_bpp);
- }
-
- sensor->valid_link_freqs = devm_kcalloc(
- &client->dev,
- compressed_max_bpp - sensor->compressed_min_bpp + 1,
- sizeof(*sensor->valid_link_freqs), GFP_KERNEL);
- if (!sensor->valid_link_freqs)
- return -ENOMEM;
-
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
- const struct smiapp_csi_data_format *f =
- &smiapp_csi_data_formats[i];
- unsigned long *valid_link_freqs =
- &sensor->valid_link_freqs[
- f->compressed - sensor->compressed_min_bpp];
- unsigned int j;
-
- if (!(sensor->default_mbus_frame_fmts & 1 << i))
- continue;
-
- pll->bits_per_pixel = f->compressed;
-
- for (j = 0; sensor->hwcfg->op_sys_clock[j]; j++) {
- pll->link_freq = sensor->hwcfg->op_sys_clock[j];
-
- rval = smiapp_pll_try(sensor, pll);
- dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n",
- pll->link_freq, pll->bits_per_pixel,
- rval ? "not ok" : "ok");
- if (rval)
- continue;
-
- set_bit(j, valid_link_freqs);
- }
-
- if (!*valid_link_freqs) {
- dev_info(&client->dev,
- "no valid link frequencies for %u bpp\n",
- f->compressed);
- sensor->default_mbus_frame_fmts &= ~BIT(i);
- continue;
- }
-
- if (!sensor->csi_format
- || f->width > sensor->csi_format->width
- || (f->width == sensor->csi_format->width
- && f->compressed > sensor->csi_format->compressed)) {
- sensor->csi_format = f;
- sensor->internal_csi_format = f;
- }
- }
-
- if (!sensor->csi_format) {
- dev_err(&client->dev, "no supported mbus code found\n");
- return -EINVAL;
- }
-
- smiapp_update_mbus_formats(sensor);
-
- return 0;
-}
-
-static void smiapp_update_blanking(struct smiapp_sensor *sensor)
-{
- struct v4l2_ctrl *vblank = sensor->vblank;
- struct v4l2_ctrl *hblank = sensor->hblank;
- uint16_t min_fll, max_fll, min_llp, max_llp, min_lbp;
- int min, max;
-
- if (sensor->binning_vertical > 1 || sensor->binning_horizontal > 1) {
- min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
- max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
- min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
- max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
- min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
- } else {
- min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES);
- max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES);
- min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK);
- max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK);
- min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK);
- }
-
- min = max_t(int,
- SMIA_LIM(sensor, MIN_FRAME_BLANKING_LINES),
- min_fll -
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height);
- max = max_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height;
-
- __v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min);
-
- min = max_t(int,
- min_llp -
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width,
- min_lbp);
- max = max_llp - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width;
-
- __v4l2_ctrl_modify_range(hblank, min, max, hblank->step, min);
-
- __smiapp_update_exposure_limits(sensor);
-}
-
-static int smiapp_pll_blanking_update(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int rval;
-
- rval = smiapp_pll_update(sensor);
- if (rval < 0)
- return rval;
-
- /* Output from pixel array, including blanking */
- smiapp_update_blanking(sensor);
-
- dev_dbg(&client->dev, "vblank\t\t%d\n", sensor->vblank->val);
- dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val);
-
- dev_dbg(&client->dev, "real timeperframe\t100/%d\n",
- sensor->pll.pixel_rate_pixel_array /
- ((sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width
- + sensor->hblank->val) *
- (sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
- + sensor->vblank->val) / 100));
-
- return 0;
-}
-
-/*
- *
- * SMIA++ NVM handling
- *
- */
-
-static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
- u8 *status)
-{
- unsigned int i;
- int rval;
- u32 s;
-
- *status = 0;
-
- rval = smiapp_write(sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT, p);
- if (rval)
- return rval;
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL,
- SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN);
- if (rval)
- return rval;
-
- rval = smiapp_read(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS,
- &s);
- if (rval)
- return rval;
-
- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE) {
- *status = s;
- return -ENODATA;
- }
-
- if (SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
- SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL) {
- for (i = 1000; i > 0; i--) {
- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY)
- break;
-
- rval = smiapp_read(
- sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS,
- &s);
-
- if (rval)
- return rval;
- }
-
- if (!i)
- return -ETIMEDOUT;
- }
-
- for (i = 0; i < SMIAPP_NVM_PAGE_SIZE; i++) {
- u32 v;
-
- rval = smiapp_read(sensor,
- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 + i,
- &v);
- if (rval)
- return rval;
-
- *nvm++ = v;
- }
-
- return 0;
-}
-
-static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
- size_t nvm_size)
-{
- u8 status = 0;
- u32 p;
- int rval = 0, rval2;
-
- for (p = 0; p < nvm_size / SMIAPP_NVM_PAGE_SIZE && !rval; p++) {
- rval = smiapp_read_nvm_page(sensor, p, nvm, &status);
- nvm += SMIAPP_NVM_PAGE_SIZE;
- }
-
- if (rval == -ENODATA &&
- status & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE)
- rval = 0;
-
- rval2 = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL, 0);
- if (rval < 0)
- return rval;
- else
- return rval2 ?: p * SMIAPP_NVM_PAGE_SIZE;
-}
-
-/*
- *
- * SMIA++ CCI address control
- *
- */
-static int smiapp_change_cci_addr(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int rval;
- u32 val;
-
- client->addr = sensor->hwcfg->i2c_addr_dfl;
-
- rval = smiapp_write(sensor,
- SMIAPP_REG_U8_CCI_ADDRESS_CONTROL,
- sensor->hwcfg->i2c_addr_alt << 1);
- if (rval)
- return rval;
-
- client->addr = sensor->hwcfg->i2c_addr_alt;
-
- /* verify addr change went ok */
- rval = smiapp_read(sensor, SMIAPP_REG_U8_CCI_ADDRESS_CONTROL, &val);
- if (rval)
- return rval;
-
- if (val != sensor->hwcfg->i2c_addr_alt << 1)
- return -ENODEV;
-
- return 0;
-}
-
-/*
- *
- * SMIA++ Mode Control
- *
- */
-static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
-{
- struct smiapp_flash_strobe_parms *strobe_setup;
- unsigned int ext_freq = sensor->hwcfg->ext_clk;
- u32 tmp;
- u32 strobe_adjustment;
- u32 strobe_width_high_rs;
- int rval;
-
- strobe_setup = sensor->hwcfg->strobe_setup;
-
- /*
- * How to calculate registers related to strobe length. Please
- * do not change, or if you do at least know what you're
- * doing. :-)
- *
- * Sakari Ailus <sakari.ailus@iki.fi> 2010-10-25
- *
- * flash_strobe_length [us] / 10^6 = (tFlash_strobe_width_ctrl
- * / EXTCLK freq [Hz]) * flash_strobe_adjustment
- *
- * tFlash_strobe_width_ctrl E N, [1 - 0xffff]
- * flash_strobe_adjustment E N, [1 - 0xff]
- *
- * The formula above is written as below to keep it on one
- * line:
- *
- * l / 10^6 = w / e * a
- *
- * Let's mark w * a by x:
- *
- * x = w * a
- *
- * Thus, we get:
- *
- * x = l * e / 10^6
- *
- * The strobe width must be at least as long as requested,
- * thus rounding upwards is needed.
- *
- * x = (l * e + 10^6 - 1) / 10^6
- * -----------------------------
- *
- * Maximum possible accuracy is wanted at all times. Thus keep
- * a as small as possible.
- *
- * Calculate a, assuming maximum w, with rounding upwards:
- *
- * a = (x + (2^16 - 1) - 1) / (2^16 - 1)
- * -------------------------------------
- *
- * Thus, we also get w, with that a, with rounding upwards:
- *
- * w = (x + a - 1) / a
- * -------------------
- *
- * To get limits:
- *
- * x E [1, (2^16 - 1) * (2^8 - 1)]
- *
- * Substituting maximum x to the original formula (with rounding),
- * the maximum l is thus
- *
- * (2^16 - 1) * (2^8 - 1) * 10^6 = l * e + 10^6 - 1
- *
- * l = (10^6 * (2^16 - 1) * (2^8 - 1) - 10^6 + 1) / e
- * --------------------------------------------------
- *
- * flash_strobe_length must be clamped between 1 and
- * (10^6 * (2^16 - 1) * (2^8 - 1) - 10^6 + 1) / EXTCLK freq.
- *
- * Then,
- *
- * flash_strobe_adjustment = ((flash_strobe_length *
- * EXTCLK freq + 10^6 - 1) / 10^6 + (2^16 - 1) - 1) / (2^16 - 1)
- *
- * tFlash_strobe_width_ctrl = ((flash_strobe_length *
- * EXTCLK freq + 10^6 - 1) / 10^6 +
- * flash_strobe_adjustment - 1) / flash_strobe_adjustment
- */
- tmp = div_u64(1000000ULL * ((1 << 16) - 1) * ((1 << 8) - 1) -
- 1000000 + 1, ext_freq);
- strobe_setup->strobe_width_high_us =
- clamp_t(u32, strobe_setup->strobe_width_high_us, 1, tmp);
-
- tmp = div_u64(((u64)strobe_setup->strobe_width_high_us * (u64)ext_freq +
- 1000000 - 1), 1000000ULL);
- strobe_adjustment = (tmp + (1 << 16) - 1 - 1) / ((1 << 16) - 1);
- strobe_width_high_rs = (tmp + strobe_adjustment - 1) /
- strobe_adjustment;
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_MODE_RS,
- strobe_setup->mode);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT,
- strobe_adjustment);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
- strobe_width_high_rs);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(sensor, SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL,
- strobe_setup->strobe_delay);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(sensor, SMIAPP_REG_U16_FLASH_STROBE_START_POINT,
- strobe_setup->stobe_start_point);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_TRIGGER_RS,
- strobe_setup->trigger);
-
-out:
- sensor->hwcfg->strobe_setup->trigger = 0;
-
- return rval;
-}
-
-/* -----------------------------------------------------------------------------
- * Power management
- */
-
-static int smiapp_power_on(struct device *dev)
-{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- /*
- * The sub-device related to the I2C device is always the
- * source one, i.e. ssds[0].
- */
- struct smiapp_sensor *sensor =
- container_of(ssd, struct smiapp_sensor, ssds[0]);
- unsigned int sleep;
- int rval;
-
- rval = regulator_enable(sensor->vana);
- if (rval) {
- dev_err(&client->dev, "failed to enable vana regulator\n");
- return rval;
- }
- usleep_range(1000, 1000);
-
- rval = clk_prepare_enable(sensor->ext_clk);
- if (rval < 0) {
- dev_dbg(&client->dev, "failed to enable xclk\n");
- goto out_xclk_fail;
- }
- usleep_range(1000, 1000);
-
- gpiod_set_value(sensor->xshutdown, 1);
-
- sleep = SMIAPP_RESET_DELAY(sensor->hwcfg->ext_clk);
- usleep_range(sleep, sleep);
-
- /*
- * Failures to respond to the address change command have been noticed.
- * Those failures seem to be caused by the sensor requiring a longer
- * boot time than advertised. An additional 10ms delay seems to work
- * around the issue, but the SMIA++ I2C write retry hack makes the delay
- * unnecessary. The failures need to be investigated to find a proper
- * fix, and a delay will likely need to be added here if the I2C write
- * retry hack is reverted before the root cause of the boot time issue
- * is found.
- */
-
- if (sensor->hwcfg->i2c_addr_alt) {
- rval = smiapp_change_cci_addr(sensor);
- if (rval) {
- dev_err(&client->dev, "cci address change error\n");
- goto out_cci_addr_fail;
- }
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_SOFTWARE_RESET,
- SMIAPP_SOFTWARE_RESET);
- if (rval < 0) {
- dev_err(&client->dev, "software reset failed\n");
- goto out_cci_addr_fail;
- }
-
- if (sensor->hwcfg->i2c_addr_alt) {
- rval = smiapp_change_cci_addr(sensor);
- if (rval) {
- dev_err(&client->dev, "cci address change error\n");
- goto out_cci_addr_fail;
- }
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U16_COMPRESSION_MODE,
- SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR);
- if (rval) {
- dev_err(&client->dev, "compression mode set failed\n");
- goto out_cci_addr_fail;
- }
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ,
- sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
- if (rval) {
- dev_err(&client->dev, "extclk frequency set failed\n");
- goto out_cci_addr_fail;
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_LANE_MODE,
- sensor->hwcfg->lanes - 1);
- if (rval) {
- dev_err(&client->dev, "csi lane mode set failed\n");
- goto out_cci_addr_fail;
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FAST_STANDBY_CTRL,
- SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE);
- if (rval) {
- dev_err(&client->dev, "fast standby set failed\n");
- goto out_cci_addr_fail;
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_SIGNALLING_MODE,
- sensor->hwcfg->csi_signalling_mode);
- if (rval) {
- dev_err(&client->dev, "csi signalling mode set failed\n");
- goto out_cci_addr_fail;
- }
-
- /* DPHY control done by sensor based on requested link rate */
- rval = smiapp_write(sensor, SMIAPP_REG_U8_DPHY_CTRL,
- SMIAPP_DPHY_CTRL_UI);
- if (rval < 0)
- goto out_cci_addr_fail;
-
- rval = smiapp_call_quirk(sensor, post_poweron);
- if (rval) {
- dev_err(&client->dev, "post_poweron quirks failed\n");
- goto out_cci_addr_fail;
- }
-
- return 0;
-
-out_cci_addr_fail:
- gpiod_set_value(sensor->xshutdown, 0);
- clk_disable_unprepare(sensor->ext_clk);
-
-out_xclk_fail:
- regulator_disable(sensor->vana);
-
- return rval;
-}
-
-static int smiapp_power_off(struct device *dev)
-{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct smiapp_sensor *sensor =
- container_of(ssd, struct smiapp_sensor, ssds[0]);
-
- /*
- * Currently power/clock to lens are enable/disabled separately
- * but they are essentially the same signals. So if the sensor is
- * powered off while the lens is powered on the sensor does not
- * really see a power off and next time the cci address change
- * will fail. So do a soft reset explicitly here.
- */
- if (sensor->hwcfg->i2c_addr_alt)
- smiapp_write(sensor,
- SMIAPP_REG_U8_SOFTWARE_RESET,
- SMIAPP_SOFTWARE_RESET);
-
- gpiod_set_value(sensor->xshutdown, 0);
- clk_disable_unprepare(sensor->ext_clk);
- usleep_range(5000, 5000);
- regulator_disable(sensor->vana);
- sensor->streaming = false;
-
- return 0;
-}
-
-/* -----------------------------------------------------------------------------
- * Video stream management
- */
-
-static int smiapp_start_streaming(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- unsigned int binning_mode;
- int rval;
-
- mutex_lock(&sensor->mutex);
-
- rval = smiapp_write(sensor, SMIAPP_REG_U16_CSI_DATA_FORMAT,
- (sensor->csi_format->width << 8) |
- sensor->csi_format->compressed);
- if (rval)
- goto out;
-
- /* Binning configuration */
- if (sensor->binning_horizontal == 1 &&
- sensor->binning_vertical == 1) {
- binning_mode = 0;
- } else {
- u8 binning_type =
- (sensor->binning_horizontal << 4)
- | sensor->binning_vertical;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U8_BINNING_TYPE, binning_type);
- if (rval < 0)
- goto out;
-
- binning_mode = 1;
- }
- rval = smiapp_write(sensor, SMIAPP_REG_U8_BINNING_MODE, binning_mode);
- if (rval < 0)
- goto out;
-
- /* Set up PLL */
- rval = smiapp_pll_configure(sensor);
- if (rval)
- goto out;
-
- /* Analog crop start coordinates */
- rval = smiapp_write(sensor, SMIAPP_REG_U16_X_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_ADDR_START,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
- if (rval < 0)
- goto out;
-
- /* Analog crop end coordinates */
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_X_ADDR_END,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left
- + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - 1);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_Y_ADDR_END,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top
- + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - 1);
- if (rval < 0)
- goto out;
-
- /*
- * Output from pixel array, including blanking, is set using
- * controls below. No need to set here.
- */
-
- /* Digital crop */
- if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].left);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].top);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH,
- sensor->scaler->crop[SMIAPP_PAD_SINK].width);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT,
- sensor->scaler->crop[SMIAPP_PAD_SINK].height);
- if (rval < 0)
- goto out;
- }
-
- /* Scaling */
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE) {
- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE,
- sensor->scaling_mode);
- if (rval < 0)
- goto out;
-
- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALE_M,
- sensor->scale_m);
- if (rval < 0)
- goto out;
- }
-
- /* Output size from sensor */
- rval = smiapp_write(sensor, SMIAPP_REG_U16_X_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].width);
- if (rval < 0)
- goto out;
- rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_OUTPUT_SIZE,
- sensor->src->crop[SMIAPP_PAD_SRC].height);
- if (rval < 0)
- goto out;
-
- if ((SMIA_LIM(sensor, FLASH_MODE_CAPABILITY) &
- (SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
- SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE)) &&
- sensor->hwcfg->strobe_setup != NULL &&
- sensor->hwcfg->strobe_setup->trigger != 0) {
- rval = smiapp_setup_flash_strobe(sensor);
- if (rval)
- goto out;
- }
-
- rval = smiapp_call_quirk(sensor, pre_streamon);
- if (rval) {
- dev_err(&client->dev, "pre_streamon quirks failed\n");
- goto out;
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT,
- SMIAPP_MODE_SELECT_STREAMING);
-
-out:
- mutex_unlock(&sensor->mutex);
-
- return rval;
-}
-
-static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int rval;
-
- mutex_lock(&sensor->mutex);
- rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT,
- SMIAPP_MODE_SELECT_SOFTWARE_STANDBY);
- if (rval)
- goto out;
-
- rval = smiapp_call_quirk(sensor, post_streamoff);
- if (rval)
- dev_err(&client->dev, "post_streamoff quirks failed\n");
-
-out:
- mutex_unlock(&sensor->mutex);
- return rval;
-}
-
-/* -----------------------------------------------------------------------------
- * V4L2 subdev video operations
- */
-
-static int smiapp_pm_get_init(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int rval;
-
- rval = pm_runtime_get_sync(&client->dev);
- if (rval < 0) {
- if (rval != -EBUSY && rval != -EAGAIN)
- pm_runtime_set_active(&client->dev);
- pm_runtime_put_noidle(&client->dev);
-
- return rval;
- } else if (!rval) {
- rval = v4l2_ctrl_handler_setup(&sensor->pixel_array->
- ctrl_handler);
- if (rval)
- return rval;
-
- return v4l2_ctrl_handler_setup(&sensor->src->ctrl_handler);
- }
-
- return 0;
-}
-
-static int smiapp_set_stream(struct v4l2_subdev *subdev, int enable)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int rval;
-
- if (sensor->streaming == enable)
- return 0;
-
- if (!enable) {
- smiapp_stop_streaming(sensor);
- sensor->streaming = false;
- pm_runtime_mark_last_busy(&client->dev);
- pm_runtime_put_autosuspend(&client->dev);
-
- return 0;
- }
-
- rval = smiapp_pm_get_init(sensor);
- if (rval)
- return rval;
-
- sensor->streaming = true;
-
- rval = smiapp_start_streaming(sensor);
- if (rval < 0) {
- sensor->streaming = false;
- pm_runtime_mark_last_busy(&client->dev);
- pm_runtime_put_autosuspend(&client->dev);
- }
-
- return rval;
-}
-
-static int smiapp_enum_mbus_code(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_mbus_code_enum *code)
-{
- struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- unsigned int i;
- int idx = -1;
- int rval = -EINVAL;
-
- mutex_lock(&sensor->mutex);
-
- dev_err(&client->dev, "subdev %s, pad %d, index %d\n",
- subdev->name, code->pad, code->index);
-
- if (subdev != &sensor->src->sd || code->pad != SMIAPP_PAD_SRC) {
- if (code->index)
- goto out;
-
- code->code = sensor->internal_csi_format->code;
- rval = 0;
- goto out;
- }
-
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
- if (sensor->mbus_frame_fmts & (1 << i))
- idx++;
-
- if (idx == code->index) {
- code->code = smiapp_csi_data_formats[i].code;
- dev_err(&client->dev, "found index %d, i %d, code %x\n",
- code->index, i, code->code);
- rval = 0;
- break;
- }
- }
-
-out:
- mutex_unlock(&sensor->mutex);
-
- return rval;
-}
-
-static u32 __smiapp_get_mbus_code(struct v4l2_subdev *subdev,
- unsigned int pad)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
-
- if (subdev == &sensor->src->sd && pad == SMIAPP_PAD_SRC)
- return sensor->csi_format->code;
- else
- return sensor->internal_csi_format->code;
-}
-
-static int __smiapp_get_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
-{
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
-
- if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
- fmt->format = *v4l2_subdev_get_try_format(subdev, cfg,
- fmt->pad);
- } else {
- struct v4l2_rect *r;
-
- if (fmt->pad == ssd->source_pad)
- r = &ssd->crop[ssd->source_pad];
- else
- r = &ssd->sink_fmt;
-
- fmt->format.code = __smiapp_get_mbus_code(subdev, fmt->pad);
- fmt->format.width = r->width;
- fmt->format.height = r->height;
- fmt->format.field = V4L2_FIELD_NONE;
- }
-
- return 0;
-}
-
-static int smiapp_get_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- int rval;
-
- mutex_lock(&sensor->mutex);
- rval = __smiapp_get_format(subdev, cfg, fmt);
- mutex_unlock(&sensor->mutex);
-
- return rval;
-}
-
-static void smiapp_get_crop_compose(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_rect **crops,
- struct v4l2_rect **comps, int which)
-{
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- unsigned int i;
-
- if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
- if (crops)
- for (i = 0; i < subdev->entity.num_pads; i++)
- crops[i] = &ssd->crop[i];
- if (comps)
- *comps = &ssd->compose;
- } else {
- if (crops) {
- for (i = 0; i < subdev->entity.num_pads; i++) {
- crops[i] = v4l2_subdev_get_try_crop(subdev, cfg, i);
- BUG_ON(!crops[i]);
- }
- }
- if (comps) {
- *comps = v4l2_subdev_get_try_compose(subdev, cfg,
- SMIAPP_PAD_SINK);
- BUG_ON(!*comps);
- }
- }
-}
-
-/* Changes require propagation only on sink pad. */
-static void smiapp_propagate(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg, int which,
- int target)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
-
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, which);
-
- switch (target) {
- case V4L2_SEL_TGT_CROP:
- comp->width = crops[SMIAPP_PAD_SINK]->width;
- comp->height = crops[SMIAPP_PAD_SINK]->height;
- if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
- if (ssd == sensor->scaler) {
- sensor->scale_m =
- SMIA_LIM(sensor, SCALER_N_MIN);
- sensor->scaling_mode =
- SMIAPP_SCALING_MODE_NONE;
- } else if (ssd == sensor->binner) {
- sensor->binning_horizontal = 1;
- sensor->binning_vertical = 1;
- }
- }
- fallthrough;
- case V4L2_SEL_TGT_COMPOSE:
- *crops[SMIAPP_PAD_SRC] = *comp;
- break;
- default:
- BUG();
- }
-}
-
-static const struct smiapp_csi_data_format
-*smiapp_validate_csi_data_format(struct smiapp_sensor *sensor, u32 code)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(smiapp_csi_data_formats); i++) {
- if (sensor->mbus_frame_fmts & (1 << i)
- && smiapp_csi_data_formats[i].code == code)
- return &smiapp_csi_data_formats[i];
- }
-
- return sensor->csi_format;
-}
-
-static int smiapp_set_format_source(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- const struct smiapp_csi_data_format *csi_format,
- *old_csi_format = sensor->csi_format;
- unsigned long *valid_link_freqs;
- u32 code = fmt->format.code;
- unsigned int i;
- int rval;
-
- rval = __smiapp_get_format(subdev, cfg, fmt);
- if (rval)
- return rval;
-
- /*
- * Media bus code is changeable on src subdev's source pad. On
- * other source pads we just get format here.
- */
- if (subdev != &sensor->src->sd)
- return 0;
-
- csi_format = smiapp_validate_csi_data_format(sensor, code);
-
- fmt->format.code = csi_format->code;
-
- if (fmt->which != V4L2_SUBDEV_FORMAT_ACTIVE)
- return 0;
-
- sensor->csi_format = csi_format;
-
- if (csi_format->width != old_csi_format->width)
- for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++)
- __v4l2_ctrl_modify_range(
- sensor->test_data[i], 0,
- (1 << csi_format->width) - 1, 1, 0);
-
- if (csi_format->compressed == old_csi_format->compressed)
- return 0;
-
- valid_link_freqs =
- &sensor->valid_link_freqs[sensor->csi_format->compressed
- - sensor->compressed_min_bpp];
-
- __v4l2_ctrl_modify_range(
- sensor->link_freq, 0,
- __fls(*valid_link_freqs), ~*valid_link_freqs,
- __ffs(*valid_link_freqs));
-
- return smiapp_pll_update(sensor);
-}
-
-static int smiapp_set_format(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_format *fmt)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *crops[SMIAPP_PADS];
-
- mutex_lock(&sensor->mutex);
-
- if (fmt->pad == ssd->source_pad) {
- int rval;
-
- rval = smiapp_set_format_source(subdev, cfg, fmt);
-
- mutex_unlock(&sensor->mutex);
-
- return rval;
- }
-
- /* Sink pad. Width and height are changeable here. */
- fmt->format.code = __smiapp_get_mbus_code(subdev, fmt->pad);
- fmt->format.width &= ~1;
- fmt->format.height &= ~1;
- fmt->format.field = V4L2_FIELD_NONE;
-
- fmt->format.width =
- clamp(fmt->format.width,
- SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE),
- SMIA_LIM(sensor, MAX_X_OUTPUT_SIZE));
- fmt->format.height =
- clamp(fmt->format.height,
- SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE),
- SMIA_LIM(sensor, MAX_Y_OUTPUT_SIZE));
-
- smiapp_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
-
- crops[ssd->sink_pad]->left = 0;
- crops[ssd->sink_pad]->top = 0;
- crops[ssd->sink_pad]->width = fmt->format.width;
- crops[ssd->sink_pad]->height = fmt->format.height;
- if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
- ssd->sink_fmt = *crops[ssd->sink_pad];
- smiapp_propagate(subdev, cfg, fmt->which,
- V4L2_SEL_TGT_CROP);
-
- mutex_unlock(&sensor->mutex);
-
- return 0;
-}
-
-/*
- * Calculate goodness of scaled image size compared to expected image
- * size and flags provided.
- */
-#define SCALING_GOODNESS 100000
-#define SCALING_GOODNESS_EXTREME 100000000
-static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
- int h, int ask_h, u32 flags)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct i2c_client *client = v4l2_get_subdevdata(subdev);
- int val = 0;
-
- w &= ~1;
- ask_w &= ~1;
- h &= ~1;
- ask_h &= ~1;
-
- if (flags & V4L2_SEL_FLAG_GE) {
- if (w < ask_w)
- val -= SCALING_GOODNESS;
- if (h < ask_h)
- val -= SCALING_GOODNESS;
- }
-
- if (flags & V4L2_SEL_FLAG_LE) {
- if (w > ask_w)
- val -= SCALING_GOODNESS;
- if (h > ask_h)
- val -= SCALING_GOODNESS;
- }
-
- val -= abs(w - ask_w);
- val -= abs(h - ask_h);
-
- if (w < SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE))
- val -= SCALING_GOODNESS_EXTREME;
-
- dev_dbg(&client->dev, "w %d ask_w %d h %d ask_h %d goodness %d\n",
- w, ask_w, h, ask_h, val);
-
- return val;
-}
-
-static void smiapp_set_compose_binner(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel,
- struct v4l2_rect **crops,
- struct v4l2_rect *comp)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- unsigned int i;
- unsigned int binh = 1, binv = 1;
- int best = scaling_goodness(
- subdev,
- crops[SMIAPP_PAD_SINK]->width, sel->r.width,
- crops[SMIAPP_PAD_SINK]->height, sel->r.height, sel->flags);
-
- for (i = 0; i < sensor->nbinning_subtypes; i++) {
- int this = scaling_goodness(
- subdev,
- crops[SMIAPP_PAD_SINK]->width
- / sensor->binning_subtypes[i].horizontal,
- sel->r.width,
- crops[SMIAPP_PAD_SINK]->height
- / sensor->binning_subtypes[i].vertical,
- sel->r.height, sel->flags);
-
- if (this > best) {
- binh = sensor->binning_subtypes[i].horizontal;
- binv = sensor->binning_subtypes[i].vertical;
- best = this;
- }
- }
- if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
- sensor->binning_vertical = binv;
- sensor->binning_horizontal = binh;
- }
-
- sel->r.width = (crops[SMIAPP_PAD_SINK]->width / binh) & ~1;
- sel->r.height = (crops[SMIAPP_PAD_SINK]->height / binv) & ~1;
-}
-
-/*
- * Calculate best scaling ratio and mode for given output resolution.
- *
- * Try all of these: horizontal ratio, vertical ratio and smallest
- * size possible (horizontally).
- *
- * Also try whether horizontal scaler or full scaler gives a better
- * result.
- */
-static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel,
- struct v4l2_rect **crops,
- struct v4l2_rect *comp)
-{
- struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- u32 min, max, a, b, max_m;
- u32 scale_m = SMIA_LIM(sensor, SCALER_N_MIN);
- int mode = SMIAPP_SCALING_MODE_HORIZONTAL;
- u32 try[4];
- u32 ntry = 0;
- unsigned int i;
- int best = INT_MIN;
-
- sel->r.width = min_t(unsigned int, sel->r.width,
- crops[SMIAPP_PAD_SINK]->width);
- sel->r.height = min_t(unsigned int, sel->r.height,
- crops[SMIAPP_PAD_SINK]->height);
-
- a = crops[SMIAPP_PAD_SINK]->width
- * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.width;
- b = crops[SMIAPP_PAD_SINK]->height
- * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.height;
- max_m = crops[SMIAPP_PAD_SINK]->width
- * SMIA_LIM(sensor, SCALER_N_MIN)
- / SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE);
-
- a = clamp(a, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
- b = clamp(b, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
- max_m = clamp(max_m, SMIA_LIM(sensor, SCALER_M_MIN),
- SMIA_LIM(sensor, SCALER_M_MAX));
-
- dev_dbg(&client->dev, "scaling: a %d b %d max_m %d\n", a, b, max_m);
-
- min = min(max_m, min(a, b));
- max = min(max_m, max(a, b));
-
- try[ntry] = min;
- ntry++;
- if (min != max) {
- try[ntry] = max;
- ntry++;
- }
- if (max != max_m) {
- try[ntry] = min + 1;
- ntry++;
- if (min != max) {
- try[ntry] = max + 1;
- ntry++;
- }
- }
-
- for (i = 0; i < ntry; i++) {
- int this = scaling_goodness(
- subdev,
- crops[SMIAPP_PAD_SINK]->width
- / try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
- sel->r.width,
- crops[SMIAPP_PAD_SINK]->height,
- sel->r.height,
- sel->flags);
-
- dev_dbg(&client->dev, "trying factor %d (%d)\n", try[i], i);
-
- if (this > best) {
- scale_m = try[i];
- mode = SMIAPP_SCALING_MODE_HORIZONTAL;
- best = this;
- }
-
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- == SMIAPP_SCALING_CAPABILITY_HORIZONTAL)
- continue;
-
- this = scaling_goodness(
- subdev, crops[SMIAPP_PAD_SINK]->width
- / try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
- sel->r.width,
- crops[SMIAPP_PAD_SINK]->height
- / try[i]
- * SMIA_LIM(sensor, SCALER_N_MIN),
- sel->r.height,
- sel->flags);
-
- if (this > best) {
- scale_m = try[i];
- mode = SMIAPP_SCALING_MODE_BOTH;
- best = this;
- }
- }
-
- sel->r.width =
- (crops[SMIAPP_PAD_SINK]->width
- / scale_m
- * SMIA_LIM(sensor, SCALER_N_MIN)) & ~1;
- if (mode == SMIAPP_SCALING_MODE_BOTH)
- sel->r.height =
- (crops[SMIAPP_PAD_SINK]->height
- / scale_m
- * SMIA_LIM(sensor, SCALER_N_MIN))
- & ~1;
- else
- sel->r.height = crops[SMIAPP_PAD_SINK]->height;
-
- if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
- sensor->scale_m = scale_m;
- sensor->scaling_mode = mode;
- }
-}
-/* We're only called on source pads. This function sets scaling. */
-static int smiapp_set_compose(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
-
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
-
- sel->r.top = 0;
- sel->r.left = 0;
-
- if (ssd == sensor->binner)
- smiapp_set_compose_binner(subdev, cfg, sel, crops, comp);
- else
- smiapp_set_compose_scaler(subdev, cfg, sel, crops, comp);
-
- *comp = sel->r;
- smiapp_propagate(subdev, cfg, sel->which, V4L2_SEL_TGT_COMPOSE);
-
- if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE)
- return smiapp_pll_blanking_update(sensor);
-
- return 0;
-}
-
-static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
- struct v4l2_subdev_selection *sel)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
-
- /* We only implement crop in three places. */
- switch (sel->target) {
- case V4L2_SEL_TGT_CROP:
- case V4L2_SEL_TGT_CROP_BOUNDS:
- if (ssd == sensor->pixel_array
- && sel->pad == SMIAPP_PA_PAD_SRC)
- return 0;
- if (ssd == sensor->src
- && sel->pad == SMIAPP_PAD_SRC)
- return 0;
- if (ssd == sensor->scaler
- && sel->pad == SMIAPP_PAD_SINK
- && SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
- return 0;
- return -EINVAL;
- case V4L2_SEL_TGT_NATIVE_SIZE:
- if (ssd == sensor->pixel_array
- && sel->pad == SMIAPP_PA_PAD_SRC)
- return 0;
- return -EINVAL;
- case V4L2_SEL_TGT_COMPOSE:
- case V4L2_SEL_TGT_COMPOSE_BOUNDS:
- if (sel->pad == ssd->source_pad)
- return -EINVAL;
- if (ssd == sensor->binner)
- return 0;
- if (ssd == sensor->scaler
- && SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE)
- return 0;
- fallthrough;
- default:
- return -EINVAL;
- }
-}
-
-static int smiapp_set_crop(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *src_size, *crops[SMIAPP_PADS];
- struct v4l2_rect _r;
-
- smiapp_get_crop_compose(subdev, cfg, crops, NULL, sel->which);
-
- if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
- if (sel->pad == ssd->sink_pad)
- src_size = &ssd->sink_fmt;
- else
- src_size = &ssd->compose;
- } else {
- if (sel->pad == ssd->sink_pad) {
- _r.left = 0;
- _r.top = 0;
- _r.width = v4l2_subdev_get_try_format(subdev, cfg, sel->pad)
- ->width;
- _r.height = v4l2_subdev_get_try_format(subdev, cfg, sel->pad)
- ->height;
- src_size = &_r;
- } else {
- src_size = v4l2_subdev_get_try_compose(
- subdev, cfg, ssd->sink_pad);
- }
- }
-
- if (ssd == sensor->src && sel->pad == SMIAPP_PAD_SRC) {
- sel->r.left = 0;
- sel->r.top = 0;
- }
-
- sel->r.width = min(sel->r.width, src_size->width);
- sel->r.height = min(sel->r.height, src_size->height);
-
- sel->r.left = min_t(int, sel->r.left, src_size->width - sel->r.width);
- sel->r.top = min_t(int, sel->r.top, src_size->height - sel->r.height);
-
- *crops[sel->pad] = sel->r;
-
- if (ssd != sensor->pixel_array && sel->pad == SMIAPP_PAD_SINK)
- smiapp_propagate(subdev, cfg, sel->which,
- V4L2_SEL_TGT_CROP);
-
- return 0;
-}
-
-static void smiapp_get_native_size(struct smiapp_subdev *ssd,
- struct v4l2_rect *r)
-{
- r->top = 0;
- r->left = 0;
- r->width = SMIA_LIM(ssd->sensor, X_ADDR_MAX) + 1;
- r->height = SMIA_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
-}
-
-static int __smiapp_get_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct v4l2_rect *comp, *crops[SMIAPP_PADS];
- struct v4l2_rect sink_fmt;
- int ret;
-
- ret = __smiapp_sel_supported(subdev, sel);
- if (ret)
- return ret;
-
- smiapp_get_crop_compose(subdev, cfg, crops, &comp, sel->which);
-
- if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
- sink_fmt = ssd->sink_fmt;
- } else {
- struct v4l2_mbus_framefmt *fmt =
- v4l2_subdev_get_try_format(subdev, cfg, ssd->sink_pad);
-
- sink_fmt.left = 0;
- sink_fmt.top = 0;
- sink_fmt.width = fmt->width;
- sink_fmt.height = fmt->height;
- }
-
- switch (sel->target) {
- case V4L2_SEL_TGT_CROP_BOUNDS:
- case V4L2_SEL_TGT_NATIVE_SIZE:
- if (ssd == sensor->pixel_array)
- smiapp_get_native_size(ssd, &sel->r);
- else if (sel->pad == ssd->sink_pad)
- sel->r = sink_fmt;
- else
- sel->r = *comp;
- break;
- case V4L2_SEL_TGT_CROP:
- case V4L2_SEL_TGT_COMPOSE_BOUNDS:
- sel->r = *crops[sel->pad];
- break;
- case V4L2_SEL_TGT_COMPOSE:
- sel->r = *comp;
- break;
- }
-
- return 0;
-}
-
-static int smiapp_get_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- int rval;
-
- mutex_lock(&sensor->mutex);
- rval = __smiapp_get_selection(subdev, cfg, sel);
- mutex_unlock(&sensor->mutex);
-
- return rval;
-}
-static int smiapp_set_selection(struct v4l2_subdev *subdev,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_selection *sel)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- int ret;
-
- ret = __smiapp_sel_supported(subdev, sel);
- if (ret)
- return ret;
-
- mutex_lock(&sensor->mutex);
-
- sel->r.left = max(0, sel->r.left & ~1);
- sel->r.top = max(0, sel->r.top & ~1);
- sel->r.width = SMIAPP_ALIGN_DIM(sel->r.width, sel->flags);
- sel->r.height = SMIAPP_ALIGN_DIM(sel->r.height, sel->flags);
-
- sel->r.width = max_t(unsigned int,
- SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE),
- sel->r.width);
- sel->r.height = max_t(unsigned int,
- SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE),
- sel->r.height);
-
- switch (sel->target) {
- case V4L2_SEL_TGT_CROP:
- ret = smiapp_set_crop(subdev, cfg, sel);
- break;
- case V4L2_SEL_TGT_COMPOSE:
- ret = smiapp_set_compose(subdev, cfg, sel);
- break;
- default:
- ret = -EINVAL;
- }
-
- mutex_unlock(&sensor->mutex);
- return ret;
-}
-
-static int smiapp_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
-
- *frames = sensor->frame_skip;
- return 0;
-}
-
-static int smiapp_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
-
- *lines = sensor->image_start;
-
- return 0;
-}
-
-/* -----------------------------------------------------------------------------
- * sysfs attributes
- */
-
-static ssize_t
-smiapp_sysfs_nvm_read(struct device *dev, struct device_attribute *attr,
- char *buf)
-{
- struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
- struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- int rval;
-
- if (!sensor->dev_init_done)
- return -EBUSY;
-
- rval = smiapp_pm_get_init(sensor);
- if (rval < 0)
- return -ENODEV;
-
- rval = smiapp_read_nvm(sensor, buf, PAGE_SIZE);
- if (rval < 0) {
- pm_runtime_put(&client->dev);
- dev_err(&client->dev, "nvm read failed\n");
- return -ENODEV;
- }
-
- pm_runtime_mark_last_busy(&client->dev);
- pm_runtime_put_autosuspend(&client->dev);
-
- /*
- * NVM is still way below a PAGE_SIZE, so we can safely
- * assume this for now.
- */
- return rval;
-}
-static DEVICE_ATTR(nvm, S_IRUGO, smiapp_sysfs_nvm_read, NULL);
-
-static ssize_t
-smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
- char *buf)
-{
- struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_module_info *minfo = &sensor->minfo;
-
- return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
- minfo->manufacturer_id, minfo->model_id,
- minfo->revision_number_major) + 1;
-}
-
-static DEVICE_ATTR(ident, S_IRUGO, smiapp_sysfs_ident_read, NULL);
-
-/* -----------------------------------------------------------------------------
- * V4L2 subdev core operations
- */
-
-static int smiapp_identify_module(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_module_info *minfo = &sensor->minfo;
- unsigned int i;
- int rval = 0;
-
- minfo->name = SMIAPP_NAME;
-
- /* Module info */
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
- &minfo->manufacturer_id);
- if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID,
- &minfo->model_id);
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_REVISION_NUMBER_MAJOR,
- &minfo->revision_number_major);
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_REVISION_NUMBER_MINOR,
- &minfo->revision_number_minor);
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_MODULE_DATE_YEAR,
- &minfo->module_year);
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_MODULE_DATE_MONTH,
- &minfo->module_month);
- if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MODULE_DATE_DAY,
- &minfo->module_day);
-
- /* Sensor info */
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID,
- &minfo->sensor_manufacturer_id);
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U16_SENSOR_MODEL_ID,
- &minfo->sensor_model_id);
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_REVISION_NUMBER,
- &minfo->sensor_revision_number);
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION,
- &minfo->sensor_firmware_version);
-
- /* SMIA */
- if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
- &minfo->smia_version);
- if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
- &minfo->smiapp_version);
-
- if (rval) {
- dev_err(&client->dev, "sensor detection failed\n");
- return -ENODEV;
- }
-
- dev_dbg(&client->dev, "module 0x%2.2x-0x%4.4x\n",
- minfo->manufacturer_id, minfo->model_id);
-
- dev_dbg(&client->dev,
- "module revision 0x%2.2x-0x%2.2x date %2.2d-%2.2d-%2.2d\n",
- minfo->revision_number_major, minfo->revision_number_minor,
- minfo->module_year, minfo->module_month, minfo->module_day);
-
- dev_dbg(&client->dev, "sensor 0x%2.2x-0x%4.4x\n",
- minfo->sensor_manufacturer_id, minfo->sensor_model_id);
-
- dev_dbg(&client->dev,
- "sensor revision 0x%2.2x firmware version 0x%2.2x\n",
- minfo->sensor_revision_number, minfo->sensor_firmware_version);
-
- dev_dbg(&client->dev, "smia version %2.2d smiapp version %2.2d\n",
- minfo->smia_version, minfo->smiapp_version);
-
- /*
- * Some modules have bad data in the lvalues below. Hope the
- * rvalues have better stuff. The lvalues are module
- * parameters whereas the rvalues are sensor parameters.
- */
- if (!minfo->manufacturer_id && !minfo->model_id) {
- minfo->manufacturer_id = minfo->sensor_manufacturer_id;
- minfo->model_id = minfo->sensor_model_id;
- minfo->revision_number_major = minfo->sensor_revision_number;
- }
-
- for (i = 0; i < ARRAY_SIZE(smiapp_module_idents); i++) {
- if (smiapp_module_idents[i].manufacturer_id
- != minfo->manufacturer_id)
- continue;
- if (smiapp_module_idents[i].model_id != minfo->model_id)
- continue;
- if (smiapp_module_idents[i].flags
- & SMIAPP_MODULE_IDENT_FLAG_REV_LE) {
- if (smiapp_module_idents[i].revision_number_major
- < minfo->revision_number_major)
- continue;
- } else {
- if (smiapp_module_idents[i].revision_number_major
- != minfo->revision_number_major)
- continue;
- }
-
- minfo->name = smiapp_module_idents[i].name;
- minfo->quirk = smiapp_module_idents[i].quirk;
- break;
- }
-
- if (i >= ARRAY_SIZE(smiapp_module_idents))
- dev_warn(&client->dev,
- "no quirks for this module; let's hope it's fully compliant\n");
-
- dev_dbg(&client->dev, "the sensor is called %s, ident %2.2x%4.4x%2.2x\n",
- minfo->name, minfo->manufacturer_id, minfo->model_id,
- minfo->revision_number_major);
-
- return 0;
-}
-
-static const struct v4l2_subdev_ops smiapp_ops;
-static const struct v4l2_subdev_internal_ops smiapp_internal_ops;
-static const struct media_entity_operations smiapp_entity_ops;
-
-static int smiapp_register_subdev(struct smiapp_sensor *sensor,
- struct smiapp_subdev *ssd,
- struct smiapp_subdev *sink_ssd,
- u16 source_pad, u16 sink_pad, u32 link_flags)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- int rval;
-
- if (!sink_ssd)
- return 0;
-
- rval = media_entity_pads_init(&ssd->sd.entity,
- ssd->npads, ssd->pads);
- if (rval) {
- dev_err(&client->dev,
- "media_entity_pads_init failed\n");
- return rval;
- }
-
- rval = v4l2_device_register_subdev(sensor->src->sd.v4l2_dev,
- &ssd->sd);
- if (rval) {
- dev_err(&client->dev,
- "v4l2_device_register_subdev failed\n");
- return rval;
- }
-
- rval = media_create_pad_link(&ssd->sd.entity, source_pad,
- &sink_ssd->sd.entity, sink_pad,
- link_flags);
- if (rval) {
- dev_err(&client->dev,
- "media_create_pad_link failed\n");
- v4l2_device_unregister_subdev(&ssd->sd);
- return rval;
- }
-
- return 0;
-}
-
-static void smiapp_unregistered(struct v4l2_subdev *subdev)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- unsigned int i;
-
- for (i = 1; i < sensor->ssds_used; i++)
- v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
-}
-
-static int smiapp_registered(struct v4l2_subdev *subdev)
-{
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- int rval;
-
- if (sensor->scaler) {
- rval = smiapp_register_subdev(
- sensor, sensor->binner, sensor->scaler,
- SMIAPP_PAD_SRC, SMIAPP_PAD_SINK,
- MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
- if (rval < 0)
- return rval;
- }
-
- rval = smiapp_register_subdev(
- sensor, sensor->pixel_array, sensor->binner,
- SMIAPP_PA_PAD_SRC, SMIAPP_PAD_SINK,
- MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
- if (rval)
- goto out_err;
-
- return 0;
-
-out_err:
- smiapp_unregistered(subdev);
-
- return rval;
-}
-
-static void smiapp_cleanup(struct smiapp_sensor *sensor)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-
- device_remove_file(&client->dev, &dev_attr_nvm);
- device_remove_file(&client->dev, &dev_attr_ident);
-
- smiapp_free_controls(sensor);
-}
-
-static void smiapp_create_subdev(struct smiapp_sensor *sensor,
- struct smiapp_subdev *ssd, const char *name,
- unsigned short num_pads)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-
- if (!ssd)
- return;
-
- if (ssd != sensor->src)
- v4l2_subdev_init(&ssd->sd, &smiapp_ops);
-
- ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
- ssd->sensor = sensor;
-
- ssd->npads = num_pads;
- ssd->source_pad = num_pads - 1;
-
- v4l2_i2c_subdev_set_name(&ssd->sd, client, sensor->minfo.name, name);
-
- smiapp_get_native_size(ssd, &ssd->sink_fmt);
-
- ssd->compose.width = ssd->sink_fmt.width;
- ssd->compose.height = ssd->sink_fmt.height;
- ssd->crop[ssd->source_pad] = ssd->compose;
- ssd->pads[ssd->source_pad].flags = MEDIA_PAD_FL_SOURCE;
- if (ssd != sensor->pixel_array) {
- ssd->crop[ssd->sink_pad] = ssd->compose;
- ssd->pads[ssd->sink_pad].flags = MEDIA_PAD_FL_SINK;
- }
-
- ssd->sd.entity.ops = &smiapp_entity_ops;
-
- if (ssd == sensor->src)
- return;
-
- ssd->sd.internal_ops = &smiapp_internal_ops;
- ssd->sd.owner = THIS_MODULE;
- ssd->sd.dev = &client->dev;
- v4l2_set_subdevdata(&ssd->sd, client);
-}
-
-static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
-{
- struct smiapp_subdev *ssd = to_smiapp_subdev(sd);
- struct smiapp_sensor *sensor = ssd->sensor;
- unsigned int i;
-
- mutex_lock(&sensor->mutex);
-
- for (i = 0; i < ssd->npads; i++) {
- struct v4l2_mbus_framefmt *try_fmt =
- v4l2_subdev_get_try_format(sd, fh->pad, i);
- struct v4l2_rect *try_crop =
- v4l2_subdev_get_try_crop(sd, fh->pad, i);
- struct v4l2_rect *try_comp;
-
- smiapp_get_native_size(ssd, try_crop);
-
- try_fmt->width = try_crop->width;
- try_fmt->height = try_crop->height;
- try_fmt->code = sensor->internal_csi_format->code;
- try_fmt->field = V4L2_FIELD_NONE;
-
- if (ssd != sensor->pixel_array)
- continue;
-
- try_comp = v4l2_subdev_get_try_compose(sd, fh->pad, i);
- *try_comp = *try_crop;
- }
-
- mutex_unlock(&sensor->mutex);
-
- return 0;
-}
-
-static const struct v4l2_subdev_video_ops smiapp_video_ops = {
- .s_stream = smiapp_set_stream,
-};
-
-static const struct v4l2_subdev_pad_ops smiapp_pad_ops = {
- .enum_mbus_code = smiapp_enum_mbus_code,
- .get_fmt = smiapp_get_format,
- .set_fmt = smiapp_set_format,
- .get_selection = smiapp_get_selection,
- .set_selection = smiapp_set_selection,
-};
-
-static const struct v4l2_subdev_sensor_ops smiapp_sensor_ops = {
- .g_skip_frames = smiapp_get_skip_frames,
- .g_skip_top_lines = smiapp_get_skip_top_lines,
-};
-
-static const struct v4l2_subdev_ops smiapp_ops = {
- .video = &smiapp_video_ops,
- .pad = &smiapp_pad_ops,
- .sensor = &smiapp_sensor_ops,
-};
-
-static const struct media_entity_operations smiapp_entity_ops = {
- .link_validate = v4l2_subdev_link_validate,
-};
-
-static const struct v4l2_subdev_internal_ops smiapp_internal_src_ops = {
- .registered = smiapp_registered,
- .unregistered = smiapp_unregistered,
- .open = smiapp_open,
-};
-
-static const struct v4l2_subdev_internal_ops smiapp_internal_ops = {
- .open = smiapp_open,
-};
-
-/* -----------------------------------------------------------------------------
- * I2C Driver
- */
-
-static int __maybe_unused smiapp_suspend(struct device *dev)
-{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- bool streaming = sensor->streaming;
- int rval;
-
- rval = pm_runtime_get_sync(dev);
- if (rval < 0) {
- if (rval != -EBUSY && rval != -EAGAIN)
- pm_runtime_set_active(&client->dev);
- pm_runtime_put(dev);
- return -EAGAIN;
- }
-
- if (sensor->streaming)
- smiapp_stop_streaming(sensor);
-
- /* save state for resume */
- sensor->streaming = streaming;
-
- return 0;
-}
-
-static int __maybe_unused smiapp_resume(struct device *dev)
-{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- int rval = 0;
-
- pm_runtime_put(dev);
-
- if (sensor->streaming)
- rval = smiapp_start_streaming(sensor);
-
- return rval;
-}
-
-static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
-{
- struct smiapp_hwconfig *hwcfg;
- struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
- struct fwnode_handle *ep;
- struct fwnode_handle *fwnode = dev_fwnode(dev);
- u32 rotation;
- int i;
- int rval;
-
- if (!fwnode)
- return dev->platform_data;
-
- ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
- if (!ep)
- return NULL;
-
- bus_cfg.bus_type = V4L2_MBUS_CSI2_DPHY;
- rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
- if (rval == -ENXIO) {
- bus_cfg = (struct v4l2_fwnode_endpoint)
- { .bus_type = V4L2_MBUS_CCP2 };
- rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
- }
- if (rval)
- goto out_err;
-
- hwcfg = devm_kzalloc(dev, sizeof(*hwcfg), GFP_KERNEL);
- if (!hwcfg)
- goto out_err;
-
- switch (bus_cfg.bus_type) {
- case V4L2_MBUS_CSI2_DPHY:
- hwcfg->csi_signalling_mode = SMIAPP_CSI_SIGNALLING_MODE_CSI2;
- hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
- break;
- case V4L2_MBUS_CCP2:
- hwcfg->csi_signalling_mode = (bus_cfg.bus.mipi_csi1.strobe) ?
- SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE :
- SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK;
- hwcfg->lanes = 1;
- break;
- default:
- dev_err(dev, "unsupported bus %u\n", bus_cfg.bus_type);
- goto out_err;
- }
-
- dev_dbg(dev, "lanes %u\n", hwcfg->lanes);
-
- rval = fwnode_property_read_u32(fwnode, "rotation", &rotation);
- if (!rval) {
- switch (rotation) {
- case 180:
- hwcfg->module_board_orient =
- SMIAPP_MODULE_BOARD_ORIENT_180;
- fallthrough;
- case 0:
- break;
- default:
- dev_err(dev, "invalid rotation %u\n", rotation);
- goto out_err;
- }
- }
-
- rval = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
- &hwcfg->ext_clk);
- if (rval)
- dev_info(dev, "can't get clock-frequency\n");
-
- dev_dbg(dev, "clk %d, mode %d\n", hwcfg->ext_clk,
- hwcfg->csi_signalling_mode);
-
- if (!bus_cfg.nr_of_link_frequencies) {
- dev_warn(dev, "no link frequencies defined\n");
- goto out_err;
- }
-
- hwcfg->op_sys_clock = devm_kcalloc(
- dev, bus_cfg.nr_of_link_frequencies + 1 /* guardian */,
- sizeof(*hwcfg->op_sys_clock), GFP_KERNEL);
- if (!hwcfg->op_sys_clock)
- goto out_err;
-
- for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
- hwcfg->op_sys_clock[i] = bus_cfg.link_frequencies[i];
- dev_dbg(dev, "freq %d: %lld\n", i, hwcfg->op_sys_clock[i]);
- }
-
- v4l2_fwnode_endpoint_free(&bus_cfg);
- fwnode_handle_put(ep);
- return hwcfg;
-
-out_err:
- v4l2_fwnode_endpoint_free(&bus_cfg);
- fwnode_handle_put(ep);
- return NULL;
-}
-
-static int smiapp_probe(struct i2c_client *client)
-{
- struct smiapp_sensor *sensor;
- struct smiapp_hwconfig *hwcfg = smiapp_get_hwconfig(&client->dev);
- unsigned int i;
- int rval;
-
- if (hwcfg == NULL)
- return -ENODEV;
-
- sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
- if (sensor == NULL)
- return -ENOMEM;
-
- sensor->hwcfg = hwcfg;
- sensor->src = &sensor->ssds[sensor->ssds_used];
-
- v4l2_i2c_subdev_init(&sensor->src->sd, client, &smiapp_ops);
- sensor->src->sd.internal_ops = &smiapp_internal_src_ops;
-
- sensor->vana = devm_regulator_get(&client->dev, "vana");
- if (IS_ERR(sensor->vana)) {
- dev_err(&client->dev, "could not get regulator for vana\n");
- return PTR_ERR(sensor->vana);
- }
-
- sensor->ext_clk = devm_clk_get(&client->dev, NULL);
- if (PTR_ERR(sensor->ext_clk) == -ENOENT) {
- dev_info(&client->dev, "no clock defined, continuing...\n");
- sensor->ext_clk = NULL;
- } else if (IS_ERR(sensor->ext_clk)) {
- dev_err(&client->dev, "could not get clock (%ld)\n",
- PTR_ERR(sensor->ext_clk));
- return -EPROBE_DEFER;
- }
-
- if (sensor->ext_clk) {
- if (sensor->hwcfg->ext_clk) {
- unsigned long rate;
-
- rval = clk_set_rate(sensor->ext_clk,
- sensor->hwcfg->ext_clk);
- if (rval < 0) {
- dev_err(&client->dev,
- "unable to set clock freq to %u\n",
- sensor->hwcfg->ext_clk);
- return rval;
- }
-
- rate = clk_get_rate(sensor->ext_clk);
- if (rate != sensor->hwcfg->ext_clk) {
- dev_err(&client->dev,
- "can't set clock freq, asked for %u but got %lu\n",
- sensor->hwcfg->ext_clk, rate);
- return rval;
- }
- } else {
- sensor->hwcfg->ext_clk = clk_get_rate(sensor->ext_clk);
- dev_dbg(&client->dev, "obtained clock freq %u\n",
- sensor->hwcfg->ext_clk);
- }
- } else if (sensor->hwcfg->ext_clk) {
- dev_dbg(&client->dev, "assuming clock freq %u\n",
- sensor->hwcfg->ext_clk);
- } else {
- dev_err(&client->dev, "unable to obtain clock freq\n");
- return -EINVAL;
- }
-
- sensor->xshutdown = devm_gpiod_get_optional(&client->dev, "xshutdown",
- GPIOD_OUT_LOW);
- if (IS_ERR(sensor->xshutdown))
- return PTR_ERR(sensor->xshutdown);
-
- rval = smiapp_power_on(&client->dev);
- if (rval < 0)
- return rval;
-
- mutex_init(&sensor->mutex);
-
- rval = smiapp_identify_module(sensor);
- if (rval) {
- rval = -ENODEV;
- goto out_power_off;
- }
-
- rval = smiapp_read_all_smia_limits(sensor);
- if (rval) {
- rval = -ENODEV;
- goto out_power_off;
- }
-
- rval = smiapp_read_frame_fmt(sensor);
- if (rval) {
- rval = -ENODEV;
- goto out_power_off;
- }
-
- /*
- * Handle Sensor Module orientation on the board.
- *
- * The application of H-FLIP and V-FLIP on the sensor is modified by
- * the sensor orientation on the board.
- *
- * For SMIAPP_BOARD_SENSOR_ORIENT_180 the default behaviour is to set
- * both H-FLIP and V-FLIP for normal operation which also implies
- * that a set/unset operation for user space HFLIP and VFLIP v4l2
- * controls will need to be internally inverted.
- *
- * Rotation also changes the bayer pattern.
- */
- if (sensor->hwcfg->module_board_orient ==
- SMIAPP_MODULE_BOARD_ORIENT_180)
- sensor->hvflip_inv_mask = SMIAPP_IMAGE_ORIENTATION_HFLIP |
- SMIAPP_IMAGE_ORIENTATION_VFLIP;
-
- rval = smiapp_call_quirk(sensor, limits);
- if (rval) {
- dev_err(&client->dev, "limits quirks failed\n");
- goto out_power_off;
- }
-
- if (SMIA_LIM(sensor, BINNING_CAPABILITY)) {
- u32 val;
-
- rval = smiapp_read(sensor,
- SMIAPP_REG_U8_BINNING_SUBTYPES, &val);
- if (rval < 0) {
- rval = -ENODEV;
- goto out_power_off;
- }
- sensor->nbinning_subtypes = min_t(u8, val,
- SMIAPP_BINNING_SUBTYPES);
-
- for (i = 0; i < sensor->nbinning_subtypes; i++) {
- rval = smiapp_read(
- sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val);
- if (rval < 0) {
- rval = -ENODEV;
- goto out_power_off;
- }
- sensor->binning_subtypes[i] =
- *(struct smiapp_binning_subtype *)&val;
-
- dev_dbg(&client->dev, "binning %xx%x\n",
- sensor->binning_subtypes[i].horizontal,
- sensor->binning_subtypes[i].vertical);
- }
- }
- sensor->binning_horizontal = 1;
- sensor->binning_vertical = 1;
-
- if (device_create_file(&client->dev, &dev_attr_ident) != 0) {
- dev_err(&client->dev, "sysfs ident entry creation failed\n");
- rval = -ENOENT;
- goto out_power_off;
- }
-
- if (sensor->minfo.smiapp_version &&
- SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
- SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
- if (device_create_file(&client->dev, &dev_attr_nvm) != 0) {
- dev_err(&client->dev, "sysfs nvm entry failed\n");
- rval = -EBUSY;
- goto out_cleanup;
- }
- }
-
- /* We consider this as profile 0 sensor if any of these are zero. */
- if (!SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
- !SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
- !SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
- !SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_0;
- } else if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- != SMIAPP_SCALING_CAPABILITY_NONE) {
- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
- == SMIAPP_SCALING_CAPABILITY_HORIZONTAL)
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_1;
- else
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_2;
- sensor->scaler = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
- } else if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
- sensor->scaler = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
- }
- sensor->binner = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
- sensor->pixel_array = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
-
- sensor->scale_m = SMIA_LIM(sensor, SCALER_N_MIN);
-
- /* prepare PLL configuration input values */
- sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2;
- sensor->pll.csi2.lanes = sensor->hwcfg->lanes;
- sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
- sensor->pll.scale_n = SMIA_LIM(sensor, SCALER_N_MIN);
- /* Profile 0 sensors have no separate OP clock branch. */
- if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
- sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
-
- smiapp_create_subdev(sensor, sensor->scaler, " scaler", 2);
- smiapp_create_subdev(sensor, sensor->binner, " binner", 2);
- smiapp_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1);
-
- dev_dbg(&client->dev, "profile %d\n", sensor->minfo.smiapp_profile);
-
- sensor->pixel_array->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
-
- rval = smiapp_init_controls(sensor);
- if (rval < 0)
- goto out_cleanup;
-
- rval = smiapp_call_quirk(sensor, init);
- if (rval)
- goto out_cleanup;
-
- rval = smiapp_get_mbus_formats(sensor);
- if (rval) {
- rval = -ENODEV;
- goto out_cleanup;
- }
-
- rval = smiapp_init_late_controls(sensor);
- if (rval) {
- rval = -ENODEV;
- goto out_cleanup;
- }
-
- mutex_lock(&sensor->mutex);
- rval = smiapp_pll_blanking_update(sensor);
- mutex_unlock(&sensor->mutex);
- if (rval) {
- dev_err(&client->dev, "update mode failed\n");
- goto out_cleanup;
- }
-
- sensor->streaming = false;
- sensor->dev_init_done = true;
-
- rval = media_entity_pads_init(&sensor->src->sd.entity, 2,
- sensor->src->pads);
- if (rval < 0)
- goto out_media_entity_cleanup;
-
- pm_runtime_set_active(&client->dev);
- pm_runtime_get_noresume(&client->dev);
- pm_runtime_enable(&client->dev);
-
- rval = v4l2_async_register_subdev_sensor_common(&sensor->src->sd);
- if (rval < 0)
- goto out_disable_runtime_pm;
-
- pm_runtime_set_autosuspend_delay(&client->dev, 1000);
- pm_runtime_use_autosuspend(&client->dev);
- pm_runtime_put_autosuspend(&client->dev);
-
- return 0;
-
-out_disable_runtime_pm:
- pm_runtime_put_noidle(&client->dev);
- pm_runtime_disable(&client->dev);
-
-out_media_entity_cleanup:
- media_entity_cleanup(&sensor->src->sd.entity);
-
-out_cleanup:
- smiapp_cleanup(sensor);
-
-out_power_off:
- smiapp_power_off(&client->dev);
- mutex_destroy(&sensor->mutex);
-
- return rval;
-}
-
-static int smiapp_remove(struct i2c_client *client)
-{
- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- unsigned int i;
-
- v4l2_async_unregister_subdev(subdev);
-
- pm_runtime_disable(&client->dev);
- if (!pm_runtime_status_suspended(&client->dev))
- smiapp_power_off(&client->dev);
- pm_runtime_set_suspended(&client->dev);
-
- for (i = 0; i < sensor->ssds_used; i++) {
- v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
- media_entity_cleanup(&sensor->ssds[i].sd.entity);
- }
- smiapp_cleanup(sensor);
- mutex_destroy(&sensor->mutex);
-
- return 0;
-}
-
-static const struct of_device_id smiapp_of_table[] = {
- { .compatible = "nokia,smia" },
- { },
-};
-MODULE_DEVICE_TABLE(of, smiapp_of_table);
-
-static const struct i2c_device_id smiapp_id_table[] = {
- { SMIAPP_NAME, 0 },
- { },
-};
-MODULE_DEVICE_TABLE(i2c, smiapp_id_table);
-
-static const struct dev_pm_ops smiapp_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(smiapp_suspend, smiapp_resume)
- SET_RUNTIME_PM_OPS(smiapp_power_off, smiapp_power_on, NULL)
-};
-
-static struct i2c_driver smiapp_i2c_driver = {
- .driver = {
- .of_match_table = smiapp_of_table,
- .name = SMIAPP_NAME,
- .pm = &smiapp_pm_ops,
- },
- .probe_new = smiapp_probe,
- .remove = smiapp_remove,
- .id_table = smiapp_id_table,
-};
-
-module_i2c_driver(smiapp_i2c_driver);
-
-MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
-MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/smiapp/smiapp-limits.c b/drivers/media/i2c/smiapp/smiapp-limits.c
deleted file mode 100644
index de5ee5296713..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-limits.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * drivers/media/i2c/smiapp/smiapp-limits.c
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#include "smiapp.h"
-
-struct smiapp_reg_limits smiapp_reg_limits[] = {
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY, "analogue_gain_capability" }, /* 0 */
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN, "analogue_gain_code_min" },
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX, "analogue_gain_code_max" },
- { SMIAPP_REG_U8_THS_ZERO_MIN, "ths_zero_min" },
- { SMIAPP_REG_U8_TCLK_TRAIL_MIN, "tclk_trail_min" },
- { SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY, "integration_time_capability" }, /* 5 */
- { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN, "coarse_integration_time_min" },
- { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN, "coarse_integration_time_max_margin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN, "fine_integration_time_min" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN, "fine_integration_time_max_margin" },
- { SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY, "digital_gain_capability" }, /* 10 */
- { SMIAPP_REG_U16_DIGITAL_GAIN_MIN, "digital_gain_min" },
- { SMIAPP_REG_U16_DIGITAL_GAIN_MAX, "digital_gain_max" },
- { SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ, "min_ext_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ, "max_ext_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV, "min_pre_pll_clk_div" }, /* 15 */
- { SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV, "max_pre_pll_clk_div" },
- { SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ, "min_pll_ip_freq_hz" },
- { SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ, "max_pll_ip_freq_hz" },
- { SMIAPP_REG_U16_MIN_PLL_MULTIPLIER, "min_pll_multiplier" },
- { SMIAPP_REG_U16_MAX_PLL_MULTIPLIER, "max_pll_multiplier" }, /* 20 */
- { SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ, "min_pll_op_freq_hz" },
- { SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ, "max_pll_op_freq_hz" },
- { SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV, "min_vt_sys_clk_div" },
- { SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV, "max_vt_sys_clk_div" },
- { SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ, "min_vt_sys_clk_freq_hz" }, /* 25 */
- { SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ, "max_vt_sys_clk_freq_hz" },
- { SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ, "min_vt_pix_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ, "max_vt_pix_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV, "min_vt_pix_clk_div" },
- { SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV, "max_vt_pix_clk_div" }, /* 30 */
- { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES, "min_frame_length_lines" },
- { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES, "max_frame_length_lines" },
- { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK, "min_line_length_pck" },
- { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK, "max_line_length_pck" },
- { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK, "min_line_blanking_pck" }, /* 35 */
- { SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES, "min_frame_blanking_lines" },
- { SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE, "min_line_length_pck_step_size" },
- { SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV, "min_op_sys_clk_div" },
- { SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV, "max_op_sys_clk_div" },
- { SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ, "min_op_sys_clk_freq_hz" }, /* 40 */
- { SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ, "max_op_sys_clk_freq_hz" },
- { SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV, "min_op_pix_clk_div" },
- { SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV, "max_op_pix_clk_div" },
- { SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ, "min_op_pix_clk_freq_hz" },
- { SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ, "max_op_pix_clk_freq_hz" }, /* 45 */
- { SMIAPP_REG_U16_X_ADDR_MIN, "x_addr_min" },
- { SMIAPP_REG_U16_Y_ADDR_MIN, "y_addr_min" },
- { SMIAPP_REG_U16_X_ADDR_MAX, "x_addr_max" },
- { SMIAPP_REG_U16_Y_ADDR_MAX, "y_addr_max" },
- { SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE, "min_x_output_size" }, /* 50 */
- { SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE, "min_y_output_size" },
- { SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE, "max_x_output_size" },
- { SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE, "max_y_output_size" },
- { SMIAPP_REG_U16_MIN_EVEN_INC, "min_even_inc" },
- { SMIAPP_REG_U16_MAX_EVEN_INC, "max_even_inc" }, /* 55 */
- { SMIAPP_REG_U16_MIN_ODD_INC, "min_odd_inc" },
- { SMIAPP_REG_U16_MAX_ODD_INC, "max_odd_inc" },
- { SMIAPP_REG_U16_SCALING_CAPABILITY, "scaling_capability" },
- { SMIAPP_REG_U16_SCALER_M_MIN, "scaler_m_min" },
- { SMIAPP_REG_U16_SCALER_M_MAX, "scaler_m_max" }, /* 60 */
- { SMIAPP_REG_U16_SCALER_N_MIN, "scaler_n_min" },
- { SMIAPP_REG_U16_SCALER_N_MAX, "scaler_n_max" },
- { SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY, "spatial_sampling_capability" },
- { SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY, "digital_crop_capability" },
- { SMIAPP_REG_U16_COMPRESSION_CAPABILITY, "compression_capability" }, /* 65 */
- { SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY, "fifo_support_capability" },
- { SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY, "dphy_ctrl_capability" },
- { SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY, "csi_lane_mode_capability" },
- { SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY, "csi_signalling_mode_capability" },
- { SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY, "fast_standby_capability" }, /* 70 */
- { SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY, "cci_address_control_capability" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS, "max_per_lane_bitrate_1_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS, "max_per_lane_bitrate_2_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS, "max_per_lane_bitrate_3_lane_mode_mbps" },
- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS, "max_per_lane_bitrate_4_lane_mode_mbps" }, /* 75 */
- { SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY, "temp_sensor_capability" },
- { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN, "min_frame_length_lines_bin" },
- { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN, "max_frame_length_lines_bin" },
- { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN, "min_line_length_pck_bin" },
- { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN, "max_line_length_pck_bin" }, /* 80 */
- { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN, "min_line_blanking_pck_bin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN, "fine_integration_time_min_bin" },
- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, "fine_integration_time_max_margin_bin" },
- { SMIAPP_REG_U8_BINNING_CAPABILITY, "binning_capability" },
- { SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY, "binning_weighting_capability" }, /* 85 */
- { SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY, "data_transfer_if_capability" },
- { SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY, "shading_correction_capability" },
- { SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY, "green_imbalance_capability" },
- { SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY, "black_level_capability" },
- { SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY, "module_specific_correction_capability" }, /* 90 */
- { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY, "defect_correction_capability" },
- { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2, "defect_correction_capability_2" },
- { SMIAPP_REG_U8_EDOF_CAPABILITY, "edof_capability" },
- { SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY, "colour_feedback_capability" },
- { SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY, "estimation_mode_capability" }, /* 95 */
- { SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY, "estimation_zone_capability" },
- { SMIAPP_REG_U16_CAPABILITY_TRDY_MIN, "capability_trdy_min" },
- { SMIAPP_REG_U8_FLASH_MODE_CAPABILITY, "flash_mode_capability" },
- { SMIAPP_REG_U8_ACTUATOR_CAPABILITY, "actuator_capability" },
- { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1, "bracketing_lut_capability_1" }, /* 100 */
- { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2, "bracketing_lut_capability_2" },
- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP, "analogue_gain_code_step" },
- { 0, NULL },
-};
diff --git a/drivers/media/i2c/smiapp/smiapp-limits.h b/drivers/media/i2c/smiapp/smiapp-limits.h
deleted file mode 100644
index dbac0b4975f9..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-limits.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * drivers/media/i2c/smiapp/smiapp-limits.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CAPABILITY 0
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN 1
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX 2
-#define SMIAPP_LIMIT_THS_ZERO_MIN 3
-#define SMIAPP_LIMIT_TCLK_TRAIL_MIN 4
-#define SMIAPP_LIMIT_INTEGRATION_TIME_CAPABILITY 5
-#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MIN 6
-#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MAX_MARGIN 7
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN 8
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN 9
-#define SMIAPP_LIMIT_DIGITAL_GAIN_CAPABILITY 10
-#define SMIAPP_LIMIT_DIGITAL_GAIN_MIN 11
-#define SMIAPP_LIMIT_DIGITAL_GAIN_MAX 12
-#define SMIAPP_LIMIT_MIN_EXT_CLK_FREQ_HZ 13
-#define SMIAPP_LIMIT_MAX_EXT_CLK_FREQ_HZ 14
-#define SMIAPP_LIMIT_MIN_PRE_PLL_CLK_DIV 15
-#define SMIAPP_LIMIT_MAX_PRE_PLL_CLK_DIV 16
-#define SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ 17
-#define SMIAPP_LIMIT_MAX_PLL_IP_FREQ_HZ 18
-#define SMIAPP_LIMIT_MIN_PLL_MULTIPLIER 19
-#define SMIAPP_LIMIT_MAX_PLL_MULTIPLIER 20
-#define SMIAPP_LIMIT_MIN_PLL_OP_FREQ_HZ 21
-#define SMIAPP_LIMIT_MAX_PLL_OP_FREQ_HZ 22
-#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_DIV 23
-#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_DIV 24
-#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_FREQ_HZ 25
-#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_FREQ_HZ 26
-#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_FREQ_HZ 27
-#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_FREQ_HZ 28
-#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_DIV 29
-#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_DIV 30
-#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES 31
-#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES 32
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK 33
-#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK 34
-#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK 35
-#define SMIAPP_LIMIT_MIN_FRAME_BLANKING_LINES 36
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_STEP_SIZE 37
-#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_DIV 38
-#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_DIV 39
-#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_FREQ_HZ 40
-#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_FREQ_HZ 41
-#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_DIV 42
-#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_DIV 43
-#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_FREQ_HZ 44
-#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_FREQ_HZ 45
-#define SMIAPP_LIMIT_X_ADDR_MIN 46
-#define SMIAPP_LIMIT_Y_ADDR_MIN 47
-#define SMIAPP_LIMIT_X_ADDR_MAX 48
-#define SMIAPP_LIMIT_Y_ADDR_MAX 49
-#define SMIAPP_LIMIT_MIN_X_OUTPUT_SIZE 50
-#define SMIAPP_LIMIT_MIN_Y_OUTPUT_SIZE 51
-#define SMIAPP_LIMIT_MAX_X_OUTPUT_SIZE 52
-#define SMIAPP_LIMIT_MAX_Y_OUTPUT_SIZE 53
-#define SMIAPP_LIMIT_MIN_EVEN_INC 54
-#define SMIAPP_LIMIT_MAX_EVEN_INC 55
-#define SMIAPP_LIMIT_MIN_ODD_INC 56
-#define SMIAPP_LIMIT_MAX_ODD_INC 57
-#define SMIAPP_LIMIT_SCALING_CAPABILITY 58
-#define SMIAPP_LIMIT_SCALER_M_MIN 59
-#define SMIAPP_LIMIT_SCALER_M_MAX 60
-#define SMIAPP_LIMIT_SCALER_N_MIN 61
-#define SMIAPP_LIMIT_SCALER_N_MAX 62
-#define SMIAPP_LIMIT_SPATIAL_SAMPLING_CAPABILITY 63
-#define SMIAPP_LIMIT_DIGITAL_CROP_CAPABILITY 64
-#define SMIAPP_LIMIT_COMPRESSION_CAPABILITY 65
-#define SMIAPP_LIMIT_FIFO_SUPPORT_CAPABILITY 66
-#define SMIAPP_LIMIT_DPHY_CTRL_CAPABILITY 67
-#define SMIAPP_LIMIT_CSI_LANE_MODE_CAPABILITY 68
-#define SMIAPP_LIMIT_CSI_SIGNALLING_MODE_CAPABILITY 69
-#define SMIAPP_LIMIT_FAST_STANDBY_CAPABILITY 70
-#define SMIAPP_LIMIT_CCI_ADDRESS_CONTROL_CAPABILITY 71
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS 72
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS 73
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS 74
-#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS 75
-#define SMIAPP_LIMIT_TEMP_SENSOR_CAPABILITY 76
-#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES_BIN 77
-#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES_BIN 78
-#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_BIN 79
-#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK_BIN 80
-#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN 81
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN_BIN 82
-#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 83
-#define SMIAPP_LIMIT_BINNING_CAPABILITY 84
-#define SMIAPP_LIMIT_BINNING_WEIGHTING_CAPABILITY 85
-#define SMIAPP_LIMIT_DATA_TRANSFER_IF_CAPABILITY 86
-#define SMIAPP_LIMIT_SHADING_CORRECTION_CAPABILITY 87
-#define SMIAPP_LIMIT_GREEN_IMBALANCE_CAPABILITY 88
-#define SMIAPP_LIMIT_BLACK_LEVEL_CAPABILITY 89
-#define SMIAPP_LIMIT_MODULE_SPECIFIC_CORRECTION_CAPABILITY 90
-#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY 91
-#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY_2 92
-#define SMIAPP_LIMIT_EDOF_CAPABILITY 93
-#define SMIAPP_LIMIT_COLOUR_FEEDBACK_CAPABILITY 94
-#define SMIAPP_LIMIT_ESTIMATION_MODE_CAPABILITY 95
-#define SMIAPP_LIMIT_ESTIMATION_ZONE_CAPABILITY 96
-#define SMIAPP_LIMIT_CAPABILITY_TRDY_MIN 97
-#define SMIAPP_LIMIT_FLASH_MODE_CAPABILITY 98
-#define SMIAPP_LIMIT_ACTUATOR_CAPABILITY 99
-#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_1 100
-#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_2 101
-#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_STEP 102
-#define SMIAPP_LIMIT_LAST 103
diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
deleted file mode 100644
index 865488befc09..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * drivers/media/i2c/smiapp/smiapp-reg-defs.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-#define SMIAPP_REG_MK_U8(r) ((SMIAPP_REG_8BIT << 16) | (r))
-#define SMIAPP_REG_MK_U16(r) ((SMIAPP_REG_16BIT << 16) | (r))
-#define SMIAPP_REG_MK_U32(r) ((SMIAPP_REG_32BIT << 16) | (r))
-
-#define SMIAPP_REG_MK_F32(r) (SMIAPP_REG_FLAG_FLOAT | (SMIAPP_REG_32BIT << 16) | (r))
-
-#define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000)
-#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002)
-#define SMIAPP_REG_U8_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0003)
-#define SMIAPP_REG_U8_SMIA_VERSION SMIAPP_REG_MK_U8(0x0004)
-#define SMIAPP_REG_U8_FRAME_COUNT SMIAPP_REG_MK_U8(0x0005)
-#define SMIAPP_REG_U8_PIXEL_ORDER SMIAPP_REG_MK_U8(0x0006)
-#define SMIAPP_REG_U16_DATA_PEDESTAL SMIAPP_REG_MK_U16(0x0008)
-#define SMIAPP_REG_U8_PIXEL_DEPTH SMIAPP_REG_MK_U8(0x000c)
-#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR SMIAPP_REG_MK_U8(0x0010)
-#define SMIAPP_REG_U8_SMIAPP_VERSION SMIAPP_REG_MK_U8(0x0011)
-#define SMIAPP_REG_U8_MODULE_DATE_YEAR SMIAPP_REG_MK_U8(0x0012)
-#define SMIAPP_REG_U8_MODULE_DATE_MONTH SMIAPP_REG_MK_U8(0x0013)
-#define SMIAPP_REG_U8_MODULE_DATE_DAY SMIAPP_REG_MK_U8(0x0014)
-#define SMIAPP_REG_U8_MODULE_DATE_PHASE SMIAPP_REG_MK_U8(0x0015)
-#define SMIAPP_REG_U16_SENSOR_MODEL_ID SMIAPP_REG_MK_U16(0x0016)
-#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER SMIAPP_REG_MK_U8(0x0018)
-#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID SMIAPP_REG_MK_U8(0x0019)
-#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION SMIAPP_REG_MK_U8(0x001a)
-#define SMIAPP_REG_U32_SERIAL_NUMBER SMIAPP_REG_MK_U32(0x001c)
-#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE SMIAPP_REG_MK_U8(0x0040)
-#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE SMIAPP_REG_MK_U8(0x0041)
-#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) SMIAPP_REG_MK_U16(0x0042 + ((n) << 1)) /* 0 <= n <= 14 */
-#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) SMIAPP_REG_MK_U32(0x0060 + ((n) << 2)) /* 0 <= n <= 7 */
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY SMIAPP_REG_MK_U16(0x0080)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN SMIAPP_REG_MK_U16(0x0084)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX SMIAPP_REG_MK_U16(0x0086)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP SMIAPP_REG_MK_U16(0x0088)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE SMIAPP_REG_MK_U16(0x008a)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 SMIAPP_REG_MK_U16(0x008c)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 SMIAPP_REG_MK_U16(0x008e)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 SMIAPP_REG_MK_U16(0x0090)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 SMIAPP_REG_MK_U16(0x0092)
-#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE SMIAPP_REG_MK_U8(0x00c0)
-#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE SMIAPP_REG_MK_U8(0x00c1)
-#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) SMIAPP_REG_MK_U16(0x00c2 + ((n) << 1))
-#define SMIAPP_REG_U8_MODE_SELECT SMIAPP_REG_MK_U8(0x0100)
-#define SMIAPP_REG_U8_IMAGE_ORIENTATION SMIAPP_REG_MK_U8(0x0101)
-#define SMIAPP_REG_U8_SOFTWARE_RESET SMIAPP_REG_MK_U8(0x0103)
-#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD SMIAPP_REG_MK_U8(0x0104)
-#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES SMIAPP_REG_MK_U8(0x0105)
-#define SMIAPP_REG_U8_FAST_STANDBY_CTRL SMIAPP_REG_MK_U8(0x0106)
-#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL SMIAPP_REG_MK_U8(0x0107)
-#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL SMIAPP_REG_MK_U8(0x0108)
-#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL SMIAPP_REG_MK_U8(0x0109)
-#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER SMIAPP_REG_MK_U8(0x0110)
-#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE SMIAPP_REG_MK_U8(0x0111)
-#define SMIAPP_REG_U16_CSI_DATA_FORMAT SMIAPP_REG_MK_U16(0x0112)
-#define SMIAPP_REG_U8_CSI_LANE_MODE SMIAPP_REG_MK_U8(0x0114)
-#define SMIAPP_REG_U8_CSI2_10_TO_8_DT SMIAPP_REG_MK_U8(0x0115)
-#define SMIAPP_REG_U8_CSI2_10_TO_7_DT SMIAPP_REG_MK_U8(0x0116)
-#define SMIAPP_REG_U8_CSI2_10_TO_6_DT SMIAPP_REG_MK_U8(0x0117)
-#define SMIAPP_REG_U8_CSI2_12_TO_8_DT SMIAPP_REG_MK_U8(0x0118)
-#define SMIAPP_REG_U8_CSI2_12_TO_7_DT SMIAPP_REG_MK_U8(0x0119)
-#define SMIAPP_REG_U8_CSI2_12_TO_6_DT SMIAPP_REG_MK_U8(0x011a)
-#define SMIAPP_REG_U8_CSI2_14_TO_10_DT SMIAPP_REG_MK_U8(0x011b)
-#define SMIAPP_REG_U8_CSI2_14_TO_8_DT SMIAPP_REG_MK_U8(0x011c)
-#define SMIAPP_REG_U8_CSI2_16_TO_10_DT SMIAPP_REG_MK_U8(0x011d)
-#define SMIAPP_REG_U8_CSI2_16_TO_8_DT SMIAPP_REG_MK_U8(0x011e)
-#define SMIAPP_REG_U8_GAIN_MODE SMIAPP_REG_MK_U8(0x0120)
-#define SMIAPP_REG_U16_VANA_VOLTAGE SMIAPP_REG_MK_U16(0x0130)
-#define SMIAPP_REG_U16_VDIG_VOLTAGE SMIAPP_REG_MK_U16(0x0132)
-#define SMIAPP_REG_U16_VIO_VOLTAGE SMIAPP_REG_MK_U16(0x0134)
-#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ SMIAPP_REG_MK_U16(0x0136)
-#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL SMIAPP_REG_MK_U8(0x0138)
-#define SMIAPP_REG_U8_TEMP_SENSOR_MODE SMIAPP_REG_MK_U8(0x0139)
-#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT SMIAPP_REG_MK_U8(0x013a)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME SMIAPP_REG_MK_U16(0x0200)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME SMIAPP_REG_MK_U16(0x0202)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL SMIAPP_REG_MK_U16(0x0204)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR SMIAPP_REG_MK_U16(0x0206)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED SMIAPP_REG_MK_U16(0x0208)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE SMIAPP_REG_MK_U16(0x020a)
-#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB SMIAPP_REG_MK_U16(0x020c)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR SMIAPP_REG_MK_U16(0x020e)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_RED SMIAPP_REG_MK_U16(0x0210)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE SMIAPP_REG_MK_U16(0x0212)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB SMIAPP_REG_MK_U16(0x0214)
-#define SMIAPP_REG_U16_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x0300)
-#define SMIAPP_REG_U16_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x0302)
-#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x0304)
-#define SMIAPP_REG_U16_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x0306)
-#define SMIAPP_REG_U16_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x0308)
-#define SMIAPP_REG_U16_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x030a)
-#define SMIAPP_REG_U16_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x0340)
-#define SMIAPP_REG_U16_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x0342)
-#define SMIAPP_REG_U16_X_ADDR_START SMIAPP_REG_MK_U16(0x0344)
-#define SMIAPP_REG_U16_Y_ADDR_START SMIAPP_REG_MK_U16(0x0346)
-#define SMIAPP_REG_U16_X_ADDR_END SMIAPP_REG_MK_U16(0x0348)
-#define SMIAPP_REG_U16_Y_ADDR_END SMIAPP_REG_MK_U16(0x034a)
-#define SMIAPP_REG_U16_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x034c)
-#define SMIAPP_REG_U16_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x034e)
-#define SMIAPP_REG_U16_X_EVEN_INC SMIAPP_REG_MK_U16(0x0380)
-#define SMIAPP_REG_U16_X_ODD_INC SMIAPP_REG_MK_U16(0x0382)
-#define SMIAPP_REG_U16_Y_EVEN_INC SMIAPP_REG_MK_U16(0x0384)
-#define SMIAPP_REG_U16_Y_ODD_INC SMIAPP_REG_MK_U16(0x0386)
-#define SMIAPP_REG_U16_SCALING_MODE SMIAPP_REG_MK_U16(0x0400)
-#define SMIAPP_REG_U16_SPATIAL_SAMPLING SMIAPP_REG_MK_U16(0x0402)
-#define SMIAPP_REG_U16_SCALE_M SMIAPP_REG_MK_U16(0x0404)
-#define SMIAPP_REG_U16_SCALE_N SMIAPP_REG_MK_U16(0x0406)
-#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET SMIAPP_REG_MK_U16(0x0408)
-#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET SMIAPP_REG_MK_U16(0x040a)
-#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH SMIAPP_REG_MK_U16(0x040c)
-#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT SMIAPP_REG_MK_U16(0x040e)
-#define SMIAPP_REG_U16_COMPRESSION_MODE SMIAPP_REG_MK_U16(0x0500)
-#define SMIAPP_REG_U16_TEST_PATTERN_MODE SMIAPP_REG_MK_U16(0x0600)
-#define SMIAPP_REG_U16_TEST_DATA_RED SMIAPP_REG_MK_U16(0x0602)
-#define SMIAPP_REG_U16_TEST_DATA_GREENR SMIAPP_REG_MK_U16(0x0604)
-#define SMIAPP_REG_U16_TEST_DATA_BLUE SMIAPP_REG_MK_U16(0x0606)
-#define SMIAPP_REG_U16_TEST_DATA_GREENB SMIAPP_REG_MK_U16(0x0608)
-#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH SMIAPP_REG_MK_U16(0x060a)
-#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION SMIAPP_REG_MK_U16(0x060c)
-#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH SMIAPP_REG_MK_U16(0x060e)
-#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION SMIAPP_REG_MK_U16(0x0610)
-#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS SMIAPP_REG_MK_U16(0x0700)
-#define SMIAPP_REG_U8_TCLK_POST SMIAPP_REG_MK_U8(0x0800)
-#define SMIAPP_REG_U8_THS_PREPARE SMIAPP_REG_MK_U8(0x0801)
-#define SMIAPP_REG_U8_THS_ZERO_MIN SMIAPP_REG_MK_U8(0x0802)
-#define SMIAPP_REG_U8_THS_TRAIL SMIAPP_REG_MK_U8(0x0803)
-#define SMIAPP_REG_U8_TCLK_TRAIL_MIN SMIAPP_REG_MK_U8(0x0804)
-#define SMIAPP_REG_U8_TCLK_PREPARE SMIAPP_REG_MK_U8(0x0805)
-#define SMIAPP_REG_U8_TCLK_ZERO SMIAPP_REG_MK_U8(0x0806)
-#define SMIAPP_REG_U8_TLPX SMIAPP_REG_MK_U8(0x0807)
-#define SMIAPP_REG_U8_DPHY_CTRL SMIAPP_REG_MK_U8(0x0808)
-#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS SMIAPP_REG_MK_U32(0x0820)
-#define SMIAPP_REG_U8_BINNING_MODE SMIAPP_REG_MK_U8(0x0900)
-#define SMIAPP_REG_U8_BINNING_TYPE SMIAPP_REG_MK_U8(0x0901)
-#define SMIAPP_REG_U8_BINNING_WEIGHTING SMIAPP_REG_MK_U8(0x0902)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL SMIAPP_REG_MK_U8(0x0a00)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS SMIAPP_REG_MK_U8(0x0a01)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT SMIAPP_REG_MK_U8(0x0a02)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 SMIAPP_REG_MK_U8(0x0a04)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 SMIAPP_REG_MK_U8(0x0a05)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 SMIAPP_REG_MK_U8(0x0a06)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 SMIAPP_REG_MK_U8(0x0a07)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 SMIAPP_REG_MK_U8(0x0a08)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 SMIAPP_REG_MK_U8(0x0a09)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 SMIAPP_REG_MK_U8(0x0a10)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 SMIAPP_REG_MK_U8(0x0a11)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 SMIAPP_REG_MK_U8(0x0a12)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 SMIAPP_REG_MK_U8(0x0a13)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 SMIAPP_REG_MK_U8(0x0a14)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 SMIAPP_REG_MK_U8(0x0a15)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 SMIAPP_REG_MK_U8(0x0a16)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 SMIAPP_REG_MK_U8(0x0a17)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 SMIAPP_REG_MK_U8(0x0a18)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 SMIAPP_REG_MK_U8(0x0a19)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 SMIAPP_REG_MK_U8(0x0a1a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 SMIAPP_REG_MK_U8(0x0a1b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 SMIAPP_REG_MK_U8(0x0a1c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 SMIAPP_REG_MK_U8(0x0a1d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 SMIAPP_REG_MK_U8(0x0a1e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 SMIAPP_REG_MK_U8(0x0a1f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 SMIAPP_REG_MK_U8(0x0a20)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 SMIAPP_REG_MK_U8(0x0a21)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 SMIAPP_REG_MK_U8(0x0a22)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 SMIAPP_REG_MK_U8(0x0a23)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 SMIAPP_REG_MK_U8(0x0a24)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 SMIAPP_REG_MK_U8(0x0a25)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 SMIAPP_REG_MK_U8(0x0a26)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 SMIAPP_REG_MK_U8(0x0a27)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 SMIAPP_REG_MK_U8(0x0a28)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 SMIAPP_REG_MK_U8(0x0a29)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 SMIAPP_REG_MK_U8(0x0a2a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 SMIAPP_REG_MK_U8(0x0a2b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 SMIAPP_REG_MK_U8(0x0a2c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 SMIAPP_REG_MK_U8(0x0a2d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 SMIAPP_REG_MK_U8(0x0a2e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 SMIAPP_REG_MK_U8(0x0a2f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 SMIAPP_REG_MK_U8(0x0a30)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 SMIAPP_REG_MK_U8(0x0a31)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 SMIAPP_REG_MK_U8(0x0a32)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 SMIAPP_REG_MK_U8(0x0a33)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 SMIAPP_REG_MK_U8(0x0a34)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 SMIAPP_REG_MK_U8(0x0a35)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 SMIAPP_REG_MK_U8(0x0a36)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 SMIAPP_REG_MK_U8(0x0a37)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 SMIAPP_REG_MK_U8(0x0a38)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 SMIAPP_REG_MK_U8(0x0a39)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 SMIAPP_REG_MK_U8(0x0a3a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 SMIAPP_REG_MK_U8(0x0a3b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 SMIAPP_REG_MK_U8(0x0a3c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 SMIAPP_REG_MK_U8(0x0a3d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 SMIAPP_REG_MK_U8(0x0a3e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 SMIAPP_REG_MK_U8(0x0a3f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 SMIAPP_REG_MK_U8(0x0a40)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 SMIAPP_REG_MK_U8(0x0a41)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 SMIAPP_REG_MK_U8(0x0a42)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 SMIAPP_REG_MK_U8(0x0a43)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL SMIAPP_REG_MK_U8(0x0a44)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS SMIAPP_REG_MK_U8(0x0a45)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT SMIAPP_REG_MK_U8(0x0a46)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 SMIAPP_REG_MK_U8(0x0a48)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 SMIAPP_REG_MK_U8(0x0a49)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 SMIAPP_REG_MK_U8(0x0a4a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 SMIAPP_REG_MK_U8(0x0a4b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 SMIAPP_REG_MK_U8(0x0a4c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 SMIAPP_REG_MK_U8(0x0a4d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 SMIAPP_REG_MK_U8(0x0a4e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 SMIAPP_REG_MK_U8(0x0a4f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 SMIAPP_REG_MK_U8(0x0a50)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 SMIAPP_REG_MK_U8(0x0a51)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 SMIAPP_REG_MK_U8(0x0a52)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 SMIAPP_REG_MK_U8(0x0a53)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 SMIAPP_REG_MK_U8(0x0a54)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 SMIAPP_REG_MK_U8(0x0a55)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 SMIAPP_REG_MK_U8(0x0a56)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 SMIAPP_REG_MK_U8(0x0a57)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 SMIAPP_REG_MK_U8(0x0a58)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 SMIAPP_REG_MK_U8(0x0a59)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 SMIAPP_REG_MK_U8(0x0a5a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 SMIAPP_REG_MK_U8(0x0a5b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 SMIAPP_REG_MK_U8(0x0a5c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 SMIAPP_REG_MK_U8(0x0a5d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 SMIAPP_REG_MK_U8(0x0a5e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 SMIAPP_REG_MK_U8(0x0a5f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 SMIAPP_REG_MK_U8(0x0a60)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 SMIAPP_REG_MK_U8(0x0a61)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 SMIAPP_REG_MK_U8(0x0a62)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 SMIAPP_REG_MK_U8(0x0a63)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 SMIAPP_REG_MK_U8(0x0a64)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 SMIAPP_REG_MK_U8(0x0a65)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 SMIAPP_REG_MK_U8(0x0a66)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 SMIAPP_REG_MK_U8(0x0a67)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 SMIAPP_REG_MK_U8(0x0a68)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 SMIAPP_REG_MK_U8(0x0a69)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 SMIAPP_REG_MK_U8(0x0a6a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 SMIAPP_REG_MK_U8(0x0a6b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 SMIAPP_REG_MK_U8(0x0a6c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 SMIAPP_REG_MK_U8(0x0a6d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 SMIAPP_REG_MK_U8(0x0a6e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 SMIAPP_REG_MK_U8(0x0a6f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 SMIAPP_REG_MK_U8(0x0a70)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 SMIAPP_REG_MK_U8(0x0a71)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 SMIAPP_REG_MK_U8(0x0a72)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 SMIAPP_REG_MK_U8(0x0a73)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 SMIAPP_REG_MK_U8(0x0a74)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 SMIAPP_REG_MK_U8(0x0a75)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 SMIAPP_REG_MK_U8(0x0a76)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 SMIAPP_REG_MK_U8(0x0a77)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 SMIAPP_REG_MK_U8(0x0a78)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 SMIAPP_REG_MK_U8(0x0a79)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 SMIAPP_REG_MK_U8(0x0a7a)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 SMIAPP_REG_MK_U8(0x0a7b)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 SMIAPP_REG_MK_U8(0x0a7c)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 SMIAPP_REG_MK_U8(0x0a7d)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 SMIAPP_REG_MK_U8(0x0a7e)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 SMIAPP_REG_MK_U8(0x0a7f)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 SMIAPP_REG_MK_U8(0x0a80)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 SMIAPP_REG_MK_U8(0x0a81)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 SMIAPP_REG_MK_U8(0x0a82)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 SMIAPP_REG_MK_U8(0x0a83)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 SMIAPP_REG_MK_U8(0x0a84)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 SMIAPP_REG_MK_U8(0x0a85)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 SMIAPP_REG_MK_U8(0x0a86)
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 SMIAPP_REG_MK_U8(0x0a87)
-#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b00)
-#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL SMIAPP_REG_MK_U8(0x0b01)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE SMIAPP_REG_MK_U8(0x0b02)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT SMIAPP_REG_MK_U8(0x0b03)
-#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b04)
-#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b05)
-#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b06)
-#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b07)
-#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b08)
-#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b09)
-#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b0a)
-#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT SMIAPP_REG_MK_U8(0x0b0b)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE SMIAPP_REG_MK_U8(0x0b0c)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT SMIAPP_REG_MK_U8(0x0b0d)
-#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b0e)
-#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b0f)
-#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b10)
-#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b11)
-#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b12)
-#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b13)
-#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b14)
-#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE SMIAPP_REG_MK_U8(0x0b15)
-#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST SMIAPP_REG_MK_U8(0x0b16)
-#define SMIAPP_REG_U8_EDOF_MODE SMIAPP_REG_MK_U8(0x0b80)
-#define SMIAPP_REG_U8_SHARPNESS SMIAPP_REG_MK_U8(0x0b83)
-#define SMIAPP_REG_U8_DENOISING SMIAPP_REG_MK_U8(0x0b84)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC SMIAPP_REG_MK_U8(0x0b85)
-#define SMIAPP_REG_U16_DEPTH_OF_FIELD SMIAPP_REG_MK_U16(0x0b86)
-#define SMIAPP_REG_U16_FOCUS_DISTANCE SMIAPP_REG_MK_U16(0x0b88)
-#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL SMIAPP_REG_MK_U8(0x0b8a)
-#define SMIAPP_REG_U16_COLOUR_TEMPERATURE SMIAPP_REG_MK_U16(0x0b8c)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR SMIAPP_REG_MK_U16(0x0b8e)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED SMIAPP_REG_MK_U16(0x0b90)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE SMIAPP_REG_MK_U16(0x0b92)
-#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB SMIAPP_REG_MK_U16(0x0b94)
-#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE SMIAPP_REG_MK_U8(0x0bc0)
-#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING SMIAPP_REG_MK_U16(0x0bc2)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START SMIAPP_REG_MK_U16(0x0bc4)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START SMIAPP_REG_MK_U16(0x0bc6)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH SMIAPP_REG_MK_U16(0x0bc8)
-#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT SMIAPP_REG_MK_U16(0x0bca)
-#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 SMIAPP_REG_MK_U8(0x0c00)
-#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 SMIAPP_REG_MK_U8(0x0c01)
-#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 SMIAPP_REG_MK_U8(0x0c02)
-#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 SMIAPP_REG_MK_U8(0x0c03)
-#define SMIAPP_REG_U16_TRDY_CTRL SMIAPP_REG_MK_U16(0x0c04)
-#define SMIAPP_REG_U16_TRDOUT_CTRL SMIAPP_REG_MK_U16(0x0c06)
-#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c08)
-#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL SMIAPP_REG_MK_U16(0x0c0a)
-#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c0c)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL SMIAPP_REG_MK_U16(0x0c0e)
-#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL SMIAPP_REG_MK_U16(0x0c10)
-#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT SMIAPP_REG_MK_U8(0x0c12)
-#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT SMIAPP_REG_MK_U16(0x0c14)
-#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL SMIAPP_REG_MK_U16(0x0c16)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL SMIAPP_REG_MK_U16(0x0c18)
-#define SMIAPP_REG_U8_FLASH_MODE_RS SMIAPP_REG_MK_U8(0x0c1a)
-#define SMIAPP_REG_U8_FLASH_TRIGGER_RS SMIAPP_REG_MK_U8(0x0c1b)
-#define SMIAPP_REG_U8_FLASH_STATUS SMIAPP_REG_MK_U8(0x0c1c)
-#define SMIAPP_REG_U8_SA_STROBE_MODE SMIAPP_REG_MK_U8(0x0c1d)
-#define SMIAPP_REG_U16_SA_STROBE_START_POINT SMIAPP_REG_MK_U16(0x0c1e)
-#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL SMIAPP_REG_MK_U16(0x0c20)
-#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL SMIAPP_REG_MK_U16(0x0c22)
-#define SMIAPP_REG_U8_SA_STROBE_TRIGGER SMIAPP_REG_MK_U8(0x0c24)
-#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS SMIAPP_REG_MK_U8(0x0c25)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL SMIAPP_REG_MK_U16(0x0c26)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL SMIAPP_REG_MK_U16(0x0c28)
-#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL SMIAPP_REG_MK_U8(0x0c2a)
-#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL SMIAPP_REG_MK_U8(0x0c2b)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL SMIAPP_REG_MK_U16(0x0c2c)
-#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL SMIAPP_REG_MK_U16(0x0c2e)
-#define SMIAPP_REG_U8_LOW_LEVEL_CTRL SMIAPP_REG_MK_U8(0x0c80)
-#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT SMIAPP_REG_MK_U16(0x0c82)
-#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c84)
-#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c86)
-#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c88)
-#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c8a)
-#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 SMIAPP_REG_MK_U16(0x0c8c)
-#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT SMIAPP_REG_MK_U8(0x0c8e)
-#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL SMIAPP_REG_MK_U8(0x0d00)
-#define SMIAPP_REG_U8_OPERATION_MODE SMIAPP_REG_MK_U8(0x0d01)
-#define SMIAPP_REG_U8_ACT_STATE1 SMIAPP_REG_MK_U8(0x0d02)
-#define SMIAPP_REG_U8_ACT_STATE2 SMIAPP_REG_MK_U8(0x0d03)
-#define SMIAPP_REG_U16_FOCUS_CHANGE SMIAPP_REG_MK_U16(0x0d80)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL SMIAPP_REG_MK_U16(0x0d82)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 SMIAPP_REG_MK_U16(0x0d84)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 SMIAPP_REG_MK_U16(0x0d86)
-#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 SMIAPP_REG_MK_U8(0x0d88)
-#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 SMIAPP_REG_MK_U8(0x0d89)
-#define SMIAPP_REG_U8_POSITION SMIAPP_REG_MK_U8(0x0d8a)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL SMIAPP_REG_MK_U8(0x0e00)
-#define SMIAPP_REG_U8_BRACKETING_LUT_MODE SMIAPP_REG_MK_U8(0x0e01)
-#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL SMIAPP_REG_MK_U8(0x0e02)
-#define SMIAPP_REG_U8_LUT_PARAMETERS_START SMIAPP_REG_MK_U8(0x0e10)
-#define SMIAPP_REG_U8_LUT_PARAMETERS_END SMIAPP_REG_MK_U8(0x0eff)
-#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY SMIAPP_REG_MK_U16(0x1000)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN SMIAPP_REG_MK_U16(0x1004)
-#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN SMIAPP_REG_MK_U16(0x1006)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN SMIAPP_REG_MK_U16(0x1008)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN SMIAPP_REG_MK_U16(0x100a)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY SMIAPP_REG_MK_U16(0x1080)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN SMIAPP_REG_MK_U16(0x1084)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX SMIAPP_REG_MK_U16(0x1086)
-#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE SMIAPP_REG_MK_U16(0x1088)
-#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1100)
-#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1104)
-#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x1108)
-#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV SMIAPP_REG_MK_U16(0x110a)
-#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ SMIAPP_REG_MK_F32(0x110c)
-#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ SMIAPP_REG_MK_F32(0x1110)
-#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x1114)
-#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER SMIAPP_REG_MK_U16(0x1116)
-#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ SMIAPP_REG_MK_F32(0x1118)
-#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ SMIAPP_REG_MK_F32(0x111c)
-#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1120)
-#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1122)
-#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1124)
-#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1128)
-#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x112c)
-#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1130)
-#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x1134)
-#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x1136)
-#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x1140)
-#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES SMIAPP_REG_MK_U16(0x1142)
-#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x1144)
-#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK SMIAPP_REG_MK_U16(0x1146)
-#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK SMIAPP_REG_MK_U16(0x1148)
-#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES SMIAPP_REG_MK_U16(0x114a)
-#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE SMIAPP_REG_MK_U8(0x114c)
-#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1160)
-#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV SMIAPP_REG_MK_U16(0x1162)
-#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1164)
-#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1168)
-#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x116c)
-#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV SMIAPP_REG_MK_U16(0x116e)
-#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1170)
-#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ SMIAPP_REG_MK_F32(0x1174)
-#define SMIAPP_REG_U16_X_ADDR_MIN SMIAPP_REG_MK_U16(0x1180)
-#define SMIAPP_REG_U16_Y_ADDR_MIN SMIAPP_REG_MK_U16(0x1182)
-#define SMIAPP_REG_U16_X_ADDR_MAX SMIAPP_REG_MK_U16(0x1184)
-#define SMIAPP_REG_U16_Y_ADDR_MAX SMIAPP_REG_MK_U16(0x1186)
-#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x1188)
-#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118a)
-#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118c)
-#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE SMIAPP_REG_MK_U16(0x118e)
-#define SMIAPP_REG_U16_MIN_EVEN_INC SMIAPP_REG_MK_U16(0x11c0)
-#define SMIAPP_REG_U16_MAX_EVEN_INC SMIAPP_REG_MK_U16(0x11c2)
-#define SMIAPP_REG_U16_MIN_ODD_INC SMIAPP_REG_MK_U16(0x11c4)
-#define SMIAPP_REG_U16_MAX_ODD_INC SMIAPP_REG_MK_U16(0x11c6)
-#define SMIAPP_REG_U16_SCALING_CAPABILITY SMIAPP_REG_MK_U16(0x1200)
-#define SMIAPP_REG_U16_SCALER_M_MIN SMIAPP_REG_MK_U16(0x1204)
-#define SMIAPP_REG_U16_SCALER_M_MAX SMIAPP_REG_MK_U16(0x1206)
-#define SMIAPP_REG_U16_SCALER_N_MIN SMIAPP_REG_MK_U16(0x1208)
-#define SMIAPP_REG_U16_SCALER_N_MAX SMIAPP_REG_MK_U16(0x120a)
-#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY SMIAPP_REG_MK_U16(0x120c)
-#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY SMIAPP_REG_MK_U8(0x120e)
-#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY SMIAPP_REG_MK_U16(0x1300)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED SMIAPP_REG_MK_U16(0x1400)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED SMIAPP_REG_MK_U16(0x1402)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED SMIAPP_REG_MK_U16(0x1404)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN SMIAPP_REG_MK_U16(0x1406)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN SMIAPP_REG_MK_U16(0x1408)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN SMIAPP_REG_MK_U16(0x140a)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE SMIAPP_REG_MK_U16(0x140c)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE SMIAPP_REG_MK_U16(0x140e)
-#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE SMIAPP_REG_MK_U16(0x1410)
-#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS SMIAPP_REG_MK_U16(0x1500)
-#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY SMIAPP_REG_MK_U8(0x1502)
-#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY SMIAPP_REG_MK_U8(0x1600)
-#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1601)
-#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1602)
-#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY SMIAPP_REG_MK_U8(0x1603)
-#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY SMIAPP_REG_MK_U8(0x1604)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1608)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x160c)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1610)
-#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS SMIAPP_REG_MK_U32(0x1614)
-#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY SMIAPP_REG_MK_U8(0x1618)
-#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN SMIAPP_REG_MK_U16(0x1700)
-#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN SMIAPP_REG_MK_U16(0x1702)
-#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN SMIAPP_REG_MK_U16(0x1704)
-#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN SMIAPP_REG_MK_U16(0x1706)
-#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN SMIAPP_REG_MK_U16(0x1708)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN SMIAPP_REG_MK_U16(0x170a)
-#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN SMIAPP_REG_MK_U16(0x170c)
-#define SMIAPP_REG_U8_BINNING_CAPABILITY SMIAPP_REG_MK_U8(0x1710)
-#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY SMIAPP_REG_MK_U8(0x1711)
-#define SMIAPP_REG_U8_BINNING_SUBTYPES SMIAPP_REG_MK_U8(0x1712)
-#define SMIAPP_REG_U8_BINNING_TYPE_n(n) SMIAPP_REG_MK_U8(0x1713 + (n)) /* 1 <= n <= 237 */
-#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY SMIAPP_REG_MK_U8(0x1800)
-#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY SMIAPP_REG_MK_U8(0x1900)
-#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY SMIAPP_REG_MK_U8(0x1901)
-#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY SMIAPP_REG_MK_U8(0x1902)
-#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY SMIAPP_REG_MK_U8(0x1903)
-#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY SMIAPP_REG_MK_U16(0x1904)
-#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 SMIAPP_REG_MK_U16(0x1906)
-#define SMIAPP_REG_U8_EDOF_CAPABILITY SMIAPP_REG_MK_U8(0x1980)
-#define SMIAPP_REG_U8_ESTIMATION_FRAMES SMIAPP_REG_MK_U8(0x1981)
-#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ SMIAPP_REG_MK_U8(0x1982)
-#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ SMIAPP_REG_MK_U8(0x1983)
-#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ SMIAPP_REG_MK_U8(0x1984)
-#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ SMIAPP_REG_MK_U8(0x1985)
-#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ SMIAPP_REG_MK_U8(0x1986)
-#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY SMIAPP_REG_MK_U8(0x1987)
-#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM SMIAPP_REG_MK_U8(0x1988)
-#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x19c0)
-#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY SMIAPP_REG_MK_U8(0x19c1)
-#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD SMIAPP_REG_MK_U16(0x19c2)
-#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE SMIAPP_REG_MK_U16(0x19c4)
-#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN SMIAPP_REG_MK_U16(0x1a00)
-#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY SMIAPP_REG_MK_U8(0x1a02)
-#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR SMIAPP_REG_MK_U16(0x1b02)
-#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY SMIAPP_REG_MK_U8(0x1b04)
-#define SMIAPP_REG_U16_ACTUATOR_TYPE SMIAPP_REG_MK_U16(0x1b40)
-#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS SMIAPP_REG_MK_U8(0x1b42)
-#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS SMIAPP_REG_MK_U16(0x1b44)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 SMIAPP_REG_MK_U8(0x1c00)
-#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 SMIAPP_REG_MK_U8(0x1c01)
-#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE SMIAPP_REG_MK_U8(0x1c02)
diff --git a/drivers/media/i2c/smiapp/smiapp-reg.h b/drivers/media/i2c/smiapp/smiapp-reg.h
deleted file mode 100644
index e6f96309786f..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-reg.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * drivers/media/i2c/smiapp/smiapp-reg.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#ifndef __SMIAPP_REG_H_
-#define __SMIAPP_REG_H_
-
-#include <linux/bits.h>
-
-#include "smiapp-reg-defs.h"
-
-/* Bits for above register */
-#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0)
-#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1)
-
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1)
-#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2)
-#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3)
-
-#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
-#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2)
-
-#define SMIAPP_SOFTWARE_RESET BIT(0)
-
-#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
-#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1)
-
-#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0
-#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1
-#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2
-
-#define SMIAPP_DPHY_CTRL_AUTOMATIC 0
-/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */
-#define SMIAPP_DPHY_CTRL_UI 1
-#define SMIAPP_DPHY_CTRL_REGISTER 2
-
-#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1
-#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2
-
-#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0
-#define SMIAPP_MODE_SELECT_STREAMING 1
-
-#define SMIAPP_SCALING_MODE_NONE 0
-#define SMIAPP_SCALING_MODE_HORIZONTAL 1
-#define SMIAPP_SCALING_MODE_BOTH 2
-
-#define SMIAPP_SCALING_CAPABILITY_NONE 0
-#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1
-#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */
-
-/* digital crop right before scaler */
-#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0
-#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1
-
-#define SMIAPP_BINNING_CAPABILITY_NO 0
-#define SMIAPP_BINNING_CAPABILITY_YES 1
-
-/* Maximum number of binning subtypes */
-#define SMIAPP_BINNING_SUBTYPES 253
-
-#define SMIAPP_PIXEL_ORDER_GRBG 0
-#define SMIAPP_PIXEL_ORDER_RGGB 1
-#define SMIAPP_PIXEL_ORDER_BGGR 2
-#define SMIAPP_PIXEL_ORDER_GBRG 3
-
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8
-#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16
-
-#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01
-#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0
-#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4
-
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12
-#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff
-
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28
-#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff
-
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4
-#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5
-
-#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0
-#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1
-
-/* Scaling N factor */
-#define SMIAPP_SCALE_N 16
-
-/* Image statistics registers */
-/* Registers 0x2000 to 0x2fff are reserved for future
- * use for statistics features.
- */
-
-/* Manufacturer Specific Registers: 0x3000 to 0x3fff
- * The manufacturer specifies these as a black box.
- */
-
-#endif /* __SMIAPP_REG_H_ */
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/smiapp-regs.c
deleted file mode 100644
index 1b58b7c6c839..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-regs.c
+++ /dev/null
@@ -1,261 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * drivers/media/i2c/smiapp/smiapp-regs.c
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#include <asm/unaligned.h>
-
-#include <linux/delay.h>
-#include <linux/i2c.h>
-
-#include "smiapp.h"
-#include "smiapp-regs.h"
-
-static uint32_t float_to_u32_mul_1000000(struct i2c_client *client,
- uint32_t phloat)
-{
- int32_t exp;
- uint64_t man;
-
- if (phloat >= 0x80000000) {
- dev_err(&client->dev, "this is a negative number\n");
- return 0;
- }
-
- if (phloat == 0x7f800000)
- return ~0; /* Inf. */
-
- if ((phloat & 0x7f800000) == 0x7f800000) {
- dev_err(&client->dev, "NaN or other special number\n");
- return 0;
- }
-
- /* Valid cases begin here */
- if (phloat == 0)
- return 0; /* Valid zero */
-
- if (phloat > 0x4f800000)
- return ~0; /* larger than 4294967295 */
-
- /*
- * Unbias exponent (note how phloat is now guaranteed to
- * have 0 in the high bit)
- */
- exp = ((int32_t)phloat >> 23) - 127;
-
- /* Extract mantissa, add missing '1' bit and it's in MHz */
- man = ((phloat & 0x7fffff) | 0x800000) * 1000000ULL;
-
- if (exp < 0)
- man >>= -exp;
- else
- man <<= exp;
-
- man >>= 23; /* Remove mantissa bias */
-
- return man & 0xffffffff;
-}
-
-
-/*
- * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
- * Returns zero if successful, or non-zero otherwise.
- */
-static int ____smiapp_read(struct smiapp_sensor *sensor, u16 reg,
- u16 len, u32 *val)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct i2c_msg msg;
- unsigned char data_buf[sizeof(u32)] = { 0 };
- unsigned char offset_buf[sizeof(u16)];
- int r;
-
- if (len > sizeof(data_buf))
- return -EINVAL;
-
- msg.addr = client->addr;
- msg.flags = 0;
- msg.len = sizeof(offset_buf);
- msg.buf = offset_buf;
- put_unaligned_be16(reg, offset_buf);
-
- r = i2c_transfer(client->adapter, &msg, 1);
- if (r != 1) {
- if (r >= 0)
- r = -EBUSY;
- goto err;
- }
-
- msg.len = len;
- msg.flags = I2C_M_RD;
- msg.buf = &data_buf[sizeof(data_buf) - len];
-
- r = i2c_transfer(client->adapter, &msg, 1);
- if (r != 1) {
- if (r >= 0)
- r = -EBUSY;
- goto err;
- }
-
- *val = get_unaligned_be32(data_buf);
-
- return 0;
-
-err:
- dev_err(&client->dev, "read from offset 0x%x error %d\n", reg, r);
-
- return r;
-}
-
-/* Read a register using 8-bit access only. */
-static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg,
- u16 len, u32 *val)
-{
- unsigned int i;
- int rval;
-
- *val = 0;
-
- for (i = 0; i < len; i++) {
- u32 val8;
-
- rval = ____smiapp_read(sensor, reg + i, 1, &val8);
- if (rval < 0)
- return rval;
- *val |= val8 << ((len - i - 1) << 3);
- }
-
- return 0;
-}
-
-/*
- * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
- * Returns zero if successful, or non-zero otherwise.
- */
-static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
- bool only8)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- u8 len = SMIAPP_REG_WIDTH(reg);
- int rval;
-
- if (len != SMIAPP_REG_8BIT && len != SMIAPP_REG_16BIT
- && len != SMIAPP_REG_32BIT)
- return -EINVAL;
-
- if (!only8)
- rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val);
- else
- rval = ____smiapp_read_8only(sensor, SMIAPP_REG_ADDR(reg), len,
- val);
- if (rval < 0)
- return rval;
-
- if (reg & SMIAPP_REG_FLAG_FLOAT)
- *val = float_to_u32_mul_1000000(client, *val);
-
- return 0;
-}
-
-int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val)
-{
- return __smiapp_read(
- sensor, reg, val,
- smiapp_needs_quirk(sensor,
- SMIAPP_QUIRK_FLAG_8BIT_READ_ONLY));
-}
-
-static int smiapp_read_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val,
- bool force8)
-{
- int rval;
-
- *val = 0;
- rval = smiapp_call_quirk(sensor, reg_access, false, &reg, val);
- if (rval == -ENOIOCTLCMD)
- return 0;
- if (rval < 0)
- return rval;
-
- if (force8)
- return __smiapp_read(sensor, reg, val, true);
-
- return smiapp_read_no_quirk(sensor, reg, val);
-}
-
-int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val)
-{
- return smiapp_read_quirk(sensor, reg, val, false);
-}
-
-int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val)
-{
- return smiapp_read_quirk(sensor, reg, val, true);
-}
-
-int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
-{
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct i2c_msg msg;
- unsigned char data[6];
- unsigned int retries;
- u8 len = SMIAPP_REG_WIDTH(reg);
- int r;
-
- if (len > sizeof(data) - 2)
- return -EINVAL;
-
- msg.addr = client->addr;
- msg.flags = 0; /* Write */
- msg.len = 2 + len;
- msg.buf = data;
-
- put_unaligned_be16(SMIAPP_REG_ADDR(reg), data);
- put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
-
- for (retries = 0; retries < 5; retries++) {
- /*
- * Due to unknown reason sensor stops responding. This
- * loop is a temporaty solution until the root cause
- * is found.
- */
- r = i2c_transfer(client->adapter, &msg, 1);
- if (r == 1) {
- if (retries)
- dev_err(&client->dev,
- "sensor i2c stall encountered. retries: %d\n",
- retries);
- return 0;
- }
-
- usleep_range(2000, 2000);
- }
-
- dev_err(&client->dev,
- "wrote 0x%x to offset 0x%x error %d\n", val,
- SMIAPP_REG_ADDR(reg), r);
-
- return r;
-}
-
-/*
- * Write to a 8/16-bit register.
- * Returns zero if successful, or non-zero otherwise.
- */
-int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val)
-{
- int rval;
-
- rval = smiapp_call_quirk(sensor, reg_access, true, &reg, &val);
- if (rval == -ENOIOCTLCMD)
- return 0;
- if (rval < 0)
- return rval;
-
- return smiapp_write_no_quirk(sensor, reg, val);
-}
diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
deleted file mode 100644
index 8fda6ed5668c..000000000000
--- a/drivers/media/i2c/smiapp/smiapp-regs.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * include/media/smiapp/smiapp-regs.h
- *
- * Generic driver for SMIA/SMIA++ compliant camera modules
- *
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
-
-#ifndef SMIAPP_REGS_H
-#define SMIAPP_REGS_H
-
-#include <linux/i2c.h>
-#include <linux/types.h>
-
-#define SMIAPP_REG_ADDR(reg) ((u16)reg)
-#define SMIAPP_REG_WIDTH(reg) ((u8)(reg >> 16))
-#define SMIAPP_REG_FLAGS(reg) ((u8)(reg >> 24))
-
-/* Use upper 8 bits of the type field for flags */
-#define SMIAPP_REG_FLAG_FLOAT (1 << 24)
-
-#define SMIAPP_REG_8BIT 1
-#define SMIAPP_REG_16BIT 2
-#define SMIAPP_REG_32BIT 4
-
-struct smiapp_sensor;
-
-int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
-int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
-int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
-
-#endif
diff --git a/drivers/media/i2c/tvp5150.c b/drivers/media/i2c/tvp5150.c
index 7d9401219a3a..e26e3f544054 100644
--- a/drivers/media/i2c/tvp5150.c
+++ b/drivers/media/i2c/tvp5150.c
@@ -1413,8 +1413,7 @@ static const struct media_entity_operations tvp5150_sd_media_ops = {
****************************************************************************/
static int __maybe_unused tvp5150_runtime_suspend(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct tvp5150 *decoder = to_tvp5150(sd);
if (decoder->irq)
@@ -1427,8 +1426,7 @@ static int __maybe_unused tvp5150_runtime_suspend(struct device *dev)
static int __maybe_unused tvp5150_runtime_resume(struct device *dev)
{
- struct i2c_client *client = to_i2c_client(dev);
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct tvp5150 *decoder = to_tvp5150(sd);
if (decoder->irq)
@@ -2082,6 +2080,7 @@ static int tvp5150_parse_dt(struct tvp5150 *decoder, struct device_node *np)
ep_np = of_graph_get_endpoint_by_regs(np, TVP5150_PAD_VID_OUT, 0);
if (!ep_np) {
+ ret = -EINVAL;
dev_err(dev, "Error no output endpoint available\n");
goto err_free;
}
diff --git a/drivers/media/pci/b2c2/flexcop-dma.c b/drivers/media/pci/b2c2/flexcop-dma.c
index ba45b378d739..ff8058568240 100644
--- a/drivers/media/pci/b2c2/flexcop-dma.c
+++ b/drivers/media/pci/b2c2/flexcop-dma.c
@@ -17,7 +17,7 @@ int flexcop_dma_allocate(struct pci_dev *pdev,
return -EINVAL;
}
- tcpu = pci_alloc_consistent(pdev, size, &tdma);
+ tcpu = dma_alloc_coherent(&pdev->dev, size, &tdma, GFP_KERNEL);
if (tcpu != NULL) {
dma->pdev = pdev;
dma->cpu_addr0 = tcpu;
@@ -33,8 +33,8 @@ EXPORT_SYMBOL(flexcop_dma_allocate);
void flexcop_dma_free(struct flexcop_dma *dma)
{
- pci_free_consistent(dma->pdev, dma->size*2,
- dma->cpu_addr0, dma->dma_addr0);
+ dma_free_coherent(&dma->pdev->dev, dma->size * 2, dma->cpu_addr0,
+ dma->dma_addr0);
memset(dma, 0, sizeof(struct flexcop_dma));
}
EXPORT_SYMBOL(flexcop_dma_free);
diff --git a/drivers/media/pci/bt8xx/bt878.c b/drivers/media/pci/bt8xx/bt878.c
index 79ba15a9385a..78dd35c9b65d 100644
--- a/drivers/media/pci/bt8xx/bt878.c
+++ b/drivers/media/pci/bt8xx/bt878.c
@@ -67,14 +67,14 @@ EXPORT_SYMBOL(bt878);
static void bt878_mem_free(struct bt878 *bt)
{
if (bt->buf_cpu) {
- pci_free_consistent(bt->dev, bt->buf_size, bt->buf_cpu,
- bt->buf_dma);
+ dma_free_coherent(&bt->dev->dev, bt->buf_size, bt->buf_cpu,
+ bt->buf_dma);
bt->buf_cpu = NULL;
}
if (bt->risc_cpu) {
- pci_free_consistent(bt->dev, bt->risc_size, bt->risc_cpu,
- bt->risc_dma);
+ dma_free_coherent(&bt->dev->dev, bt->risc_size, bt->risc_cpu,
+ bt->risc_dma);
bt->risc_cpu = NULL;
}
}
@@ -84,16 +84,16 @@ static int bt878_mem_alloc(struct bt878 *bt)
if (!bt->buf_cpu) {
bt->buf_size = 128 * 1024;
- bt->buf_cpu = pci_zalloc_consistent(bt->dev, bt->buf_size,
- &bt->buf_dma);
+ bt->buf_cpu = dma_alloc_coherent(&bt->dev->dev, bt->buf_size,
+ &bt->buf_dma, GFP_KERNEL);
if (!bt->buf_cpu)
return -ENOMEM;
}
if (!bt->risc_cpu) {
bt->risc_size = PAGE_SIZE;
- bt->risc_cpu = pci_zalloc_consistent(bt->dev, bt->risc_size,
- &bt->risc_dma);
+ bt->risc_cpu = dma_alloc_coherent(&bt->dev->dev, bt->risc_size,
+ &bt->risc_dma, GFP_KERNEL);
if (!bt->risc_cpu) {
bt878_mem_free(bt);
return -ENOMEM;
diff --git a/drivers/media/pci/bt8xx/btcx-risc.c b/drivers/media/pci/bt8xx/btcx-risc.c
index 51257980f539..b3179038b900 100644
--- a/drivers/media/pci/bt8xx/btcx-risc.c
+++ b/drivers/media/pci/bt8xx/btcx-risc.c
@@ -48,7 +48,7 @@ void btcx_riscmem_free(struct pci_dev *pci,
dprintk("btcx: riscmem free [%d] dma=%lx\n",
memcnt, (unsigned long)risc->dma);
- pci_free_consistent(pci, risc->size, risc->cpu, risc->dma);
+ dma_free_coherent(&pci->dev, risc->size, risc->cpu, risc->dma);
memset(risc,0,sizeof(*risc));
}
@@ -62,7 +62,7 @@ int btcx_riscmem_alloc(struct pci_dev *pci,
if (NULL != risc->cpu && risc->size < size)
btcx_riscmem_free(pci,risc);
if (NULL == risc->cpu) {
- cpu = pci_alloc_consistent(pci, size, &dma);
+ cpu = dma_alloc_coherent(&pci->dev, size, &dma, GFP_KERNEL);
if (NULL == cpu)
return -ENOMEM;
risc->cpu = cpu;
@@ -73,7 +73,6 @@ int btcx_riscmem_alloc(struct pci_dev *pci,
dprintk("btcx: riscmem alloc [%d] dma=%lx cpu=%p size=%d\n",
memcnt, (unsigned long)dma, cpu, size);
}
- memset(risc->cpu,0,risc->size);
return 0;
}
diff --git a/drivers/media/pci/bt8xx/bttv-cards.c b/drivers/media/pci/bt8xx/bttv-cards.c
index 16148802dabb..ca20b806e82d 100644
--- a/drivers/media/pci/bt8xx/bttv-cards.c
+++ b/drivers/media/pci/bt8xx/bttv-cards.c
@@ -3934,8 +3934,10 @@ static void osprey_eeprom(struct bttv *btv, const u8 ee[256])
if (checksum != ee[21])
return;
cardid = BTTV_BOARD_OSPREY1x0_848;
- for (i = 12; i < 21; i++)
- serial *= 10, serial += ee[i] - '0';
+ for (i = 12; i < 21; i++) {
+ serial *= 10;
+ serial += ee[i] - '0';
+ }
}
} else {
unsigned short type;
diff --git a/drivers/media/pci/bt8xx/bttv-driver.c b/drivers/media/pci/bt8xx/bttv-driver.c
index 8824dd0fb331..1f62a9d8ea1d 100644
--- a/drivers/media/pci/bt8xx/bttv-driver.c
+++ b/drivers/media/pci/bt8xx/bttv-driver.c
@@ -2058,7 +2058,6 @@ verify_window_lock(struct bttv_fh *fh, struct v4l2_window *win,
{
enum v4l2_field field;
unsigned int width_mask;
- int rc;
if (win->w.width < 48)
win->w.width = 48;
@@ -2111,13 +2110,10 @@ verify_window_lock(struct bttv_fh *fh, struct v4l2_window *win,
win->w.width -= win->w.left & ~width_mask;
win->w.left = (win->w.left - width_mask - 1) & width_mask;
- rc = limit_scaled_size_lock(fh, &win->w.width, &win->w.height,
- field, width_mask,
- /* width_bias: round down */ 0,
- adjust_size, adjust_crop);
- if (0 != rc)
- return rc;
- return 0;
+ return limit_scaled_size_lock(fh, &win->w.width, &win->w.height,
+ field, width_mask,
+ /* width_bias: round down */ 0,
+ adjust_size, adjust_crop);
}
static int setup_window_lock(struct bttv_fh *fh, struct bttv *btv,
@@ -2143,12 +2139,8 @@ static int setup_window_lock(struct bttv_fh *fh, struct bttv *btv,
clips = kmalloc(size,GFP_KERNEL);
if (NULL == clips)
return -ENOMEM;
- if (n > 0) {
- if (copy_from_user(clips,win->clips,sizeof(struct v4l2_clip)*n)) {
- kfree(clips);
- return -EFAULT;
- }
- }
+ if (n > 0)
+ memcpy(clips, win->clips, sizeof(struct v4l2_clip) * n);
/* clip against screen */
if (NULL != btv->fbuf.base)
@@ -4016,7 +4008,7 @@ static int bttv_probe(struct pci_dev *dev, const struct pci_device_id *pci_id)
result = -EIO;
goto free_mem;
}
- if (pci_set_dma_mask(dev, DMA_BIT_MASK(32))) {
+ if (dma_set_mask(&dev->dev, DMA_BIT_MASK(32))) {
pr_warn("%d: No suitable DMA available\n", btv->c.nr);
result = -EIO;
goto free_mem;
@@ -4270,15 +4262,14 @@ static void bttv_remove(struct pci_dev *pci_dev)
return;
}
-#ifdef CONFIG_PM
-static int bttv_suspend(struct pci_dev *pci_dev, pm_message_t state)
+static int __maybe_unused bttv_suspend(struct device *dev)
{
- struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
+ struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
struct bttv *btv = to_bttv(v4l2_dev);
struct bttv_buffer_set idle;
unsigned long flags;
- dprintk("%d: suspend %d\n", btv->c.nr, state.event);
+ dprintk("%d: suspend\n", btv->c.nr);
/* stop dma + irqs */
spin_lock_irqsave(&btv->s_lock,flags);
@@ -4298,42 +4289,19 @@ static int bttv_suspend(struct pci_dev *pci_dev, pm_message_t state)
btv->state.gpio_enable = btread(BT848_GPIO_OUT_EN);
btv->state.gpio_data = gpio_read();
- /* save pci state */
- pci_save_state(pci_dev);
- if (0 != pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state))) {
- pci_disable_device(pci_dev);
- btv->state.disabled = 1;
- }
+ btv->state.disabled = 1;
return 0;
}
-static int bttv_resume(struct pci_dev *pci_dev)
+static int __maybe_unused bttv_resume(struct device *dev)
{
- struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
+ struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
struct bttv *btv = to_bttv(v4l2_dev);
unsigned long flags;
- int err;
dprintk("%d: resume\n", btv->c.nr);
- /* restore pci state */
- if (btv->state.disabled) {
- err=pci_enable_device(pci_dev);
- if (err) {
- pr_warn("%d: Can't enable device\n", btv->c.nr);
- return err;
- }
- btv->state.disabled = 0;
- }
- err=pci_set_power_state(pci_dev, PCI_D0);
- if (err) {
- pci_disable_device(pci_dev);
- pr_warn("%d: Can't enable device\n", btv->c.nr);
- btv->state.disabled = 1;
- return err;
- }
-
- pci_restore_state(pci_dev);
+ btv->state.disabled = 0;
/* restore bt878 state */
bttv_reinit_bt848(btv);
@@ -4351,7 +4319,6 @@ static int bttv_resume(struct pci_dev *pci_dev)
spin_unlock_irqrestore(&btv->s_lock,flags);
return 0;
}
-#endif
static const struct pci_device_id bttv_pci_tbl[] = {
{PCI_VDEVICE(BROOKTREE, PCI_DEVICE_ID_BT848), 0},
@@ -4364,15 +4331,16 @@ static const struct pci_device_id bttv_pci_tbl[] = {
MODULE_DEVICE_TABLE(pci, bttv_pci_tbl);
+static SIMPLE_DEV_PM_OPS(bttv_pm_ops,
+ bttv_suspend,
+ bttv_resume);
+
static struct pci_driver bttv_pci_driver = {
- .name = "bttv",
- .id_table = bttv_pci_tbl,
- .probe = bttv_probe,
- .remove = bttv_remove,
-#ifdef CONFIG_PM
- .suspend = bttv_suspend,
- .resume = bttv_resume,
-#endif
+ .name = "bttv",
+ .id_table = bttv_pci_tbl,
+ .probe = bttv_probe,
+ .remove = bttv_remove,
+ .driver.pm = &bttv_pm_ops,
};
static int __init bttv_init_module(void)
diff --git a/drivers/media/pci/bt8xx/bttv-risc.c b/drivers/media/pci/bt8xx/bttv-risc.c
index 4af72826b006..32fa4a7fe76f 100644
--- a/drivers/media/pci/bt8xx/bttv-risc.c
+++ b/drivers/media/pci/bt8xx/bttv-risc.c
@@ -572,7 +572,6 @@ bttv_dma_free(struct videobuf_queue *q,struct bttv *btv, struct bttv_buffer *buf
{
struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb);
- BUG_ON(in_interrupt());
videobuf_waiton(q, &buf->vb, 0, 0);
videobuf_dma_unmap(q->dev, dma);
videobuf_dma_free(dma);
diff --git a/drivers/media/pci/cx23885/cx23885-core.c b/drivers/media/pci/cx23885/cx23885-core.c
index 4b0c53f61fb7..22f55a7840a6 100644
--- a/drivers/media/pci/cx23885/cx23885-core.c
+++ b/drivers/media/pci/cx23885/cx23885-core.c
@@ -1322,7 +1322,6 @@ void cx23885_free_buffer(struct cx23885_dev *dev, struct cx23885_buffer *buf)
{
struct cx23885_riscmem *risc = &buf->risc;
- BUG_ON(in_interrupt());
pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
}
@@ -2074,6 +2073,10 @@ static struct {
* 0x1451 is PCI ID for the IOMMU found on Ryzen
*/
{ PCI_VENDOR_ID_AMD, 0x1451 },
+ /* According to sudo lspci -nn,
+ * 0x1423 is the PCI ID for the IOMMU found on Kaveri
+ */
+ { PCI_VENDOR_ID_AMD, 0x1423 },
};
static bool cx23885_does_need_dma_reset(void)
diff --git a/drivers/media/pci/cx25821/cx25821-core.c b/drivers/media/pci/cx25821/cx25821-core.c
index 55018d9e439f..6f8ffab8840f 100644
--- a/drivers/media/pci/cx25821/cx25821-core.c
+++ b/drivers/media/pci/cx25821/cx25821-core.c
@@ -1198,7 +1198,6 @@ EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
void cx25821_free_buffer(struct cx25821_dev *dev, struct cx25821_buffer *buf)
{
- BUG_ON(in_interrupt());
if (WARN_ON(buf->risc.size == 0))
return;
pci_free_consistent(dev->pci,
diff --git a/drivers/media/pci/cx88/cx88-mpeg.c b/drivers/media/pci/cx88/cx88-mpeg.c
index a57c991b165b..a3edb548afde 100644
--- a/drivers/media/pci/cx88/cx88-mpeg.c
+++ b/drivers/media/pci/cx88/cx88-mpeg.c
@@ -524,8 +524,7 @@ static int cx8802_request_acquire(struct cx8802_driver *drv)
core->last_analog_input = core->input;
core->input = 0;
for (i = 0;
- i < (sizeof(core->board.input) /
- sizeof(struct cx88_input));
+ i < ARRAY_SIZE(core->board.input);
i++) {
if (core->board.input[i].type == CX88_VMUX_DVB) {
core->input = i;
diff --git a/drivers/media/pci/dm1105/dm1105.c b/drivers/media/pci/dm1105/dm1105.c
index 9dce31d2b525..4ac645a56c14 100644
--- a/drivers/media/pci/dm1105/dm1105.c
+++ b/drivers/media/pci/dm1105/dm1105.c
@@ -604,19 +604,17 @@ static void dm1105_set_dma_addr(struct dm1105_dev *dev)
static int dm1105_dma_map(struct dm1105_dev *dev)
{
- dev->ts_buf = pci_alloc_consistent(dev->pdev,
- 6 * DM1105_DMA_BYTES,
- &dev->dma_addr);
+ dev->ts_buf = dma_alloc_coherent(&dev->pdev->dev,
+ 6 * DM1105_DMA_BYTES, &dev->dma_addr,
+ GFP_KERNEL);
return !dev->ts_buf;
}
static void dm1105_dma_unmap(struct dm1105_dev *dev)
{
- pci_free_consistent(dev->pdev,
- 6 * DM1105_DMA_BYTES,
- dev->ts_buf,
- dev->dma_addr);
+ dma_free_coherent(&dev->pdev->dev, 6 * DM1105_DMA_BYTES, dev->ts_buf,
+ dev->dma_addr);
}
static void dm1105_enable_irqs(struct dm1105_dev *dev)
@@ -1010,7 +1008,7 @@ static int dm1105_probe(struct pci_dev *pdev,
if (ret < 0)
goto err_kfree;
- ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret < 0)
goto err_pci_disable_device;
diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.c b/drivers/media/pci/intel/ipu3/ipu3-cio2.c
index 4e598e937dfe..36e354ecf71e 100644
--- a/drivers/media/pci/intel/ipu3/ipu3-cio2.c
+++ b/drivers/media/pci/intel/ipu3/ipu3-cio2.c
@@ -14,6 +14,7 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/iopoll.h>
+#include <linux/mm.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/pfn.h>
@@ -33,6 +34,7 @@ struct ipu3_cio2_fmt {
u32 mbus_code;
u32 fourcc;
u8 mipicode;
+ u8 bpp;
};
/*
@@ -46,18 +48,22 @@ static const struct ipu3_cio2_fmt formats[] = {
.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
.fourcc = V4L2_PIX_FMT_IPU3_SGRBG10,
.mipicode = 0x2b,
+ .bpp = 10,
}, {
.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
.fourcc = V4L2_PIX_FMT_IPU3_SGBRG10,
.mipicode = 0x2b,
+ .bpp = 10,
}, {
.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
.fourcc = V4L2_PIX_FMT_IPU3_SBGGR10,
.mipicode = 0x2b,
+ .bpp = 10,
}, {
.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
.fourcc = V4L2_PIX_FMT_IPU3_SRGGB10,
.mipicode = 0x2b,
+ .bpp = 10,
},
};
@@ -189,9 +195,8 @@ static void cio2_fbpt_entry_init_buf(struct cio2_device *cio2,
* 4095 (PAGE_SIZE - 1) means every single byte in the last page
* is available for DMA transfer.
*/
- entry[1].second_entry.last_page_available_bytes =
- (remaining & ~PAGE_MASK) ?
- (remaining & ~PAGE_MASK) - 1 : PAGE_SIZE - 1;
+ remaining = offset_in_page(remaining) ?: PAGE_SIZE;
+ entry[1].second_entry.last_page_available_bytes = remaining - 1;
/* Fill FBPT */
remaining = length;
i = 0;
@@ -286,37 +291,22 @@ static s32 cio2_rx_timing(s32 a, s32 b, s64 freq, int def)
return r;
};
-/* Calculate the the delay value for termination enable of clock lane HS Rx */
+/* Calculate the delay value for termination enable of clock lane HS Rx */
static int cio2_csi2_calc_timing(struct cio2_device *cio2, struct cio2_queue *q,
- struct cio2_csi2_timing *timing)
+ struct cio2_csi2_timing *timing,
+ unsigned int bpp, unsigned int lanes)
{
struct device *dev = &cio2->pci_dev->dev;
- struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ };
- struct v4l2_ctrl *link_freq;
s64 freq;
- int r;
if (!q->sensor)
return -ENODEV;
- link_freq = v4l2_ctrl_find(q->sensor->ctrl_handler, V4L2_CID_LINK_FREQ);
- if (!link_freq) {
- dev_err(dev, "failed to find LINK_FREQ\n");
- return -EPIPE;
- }
-
- qm.index = v4l2_ctrl_g_ctrl(link_freq);
- r = v4l2_querymenu(q->sensor->ctrl_handler, &qm);
- if (r) {
- dev_err(dev, "failed to get menu item\n");
- return r;
- }
-
- if (!qm.value) {
- dev_err(dev, "error invalid link_freq\n");
- return -EINVAL;
+ freq = v4l2_get_link_rate(q->sensor->ctrl_handler, bpp, lanes);
+ if (freq < 0) {
+ dev_err(dev, "error %lld, invalid link_freq\n", freq);
+ return freq;
}
- freq = qm.value;
timing->clk_termen = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A,
CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_B,
@@ -364,7 +354,7 @@ static int cio2_hw_init(struct cio2_device *cio2, struct cio2_queue *q)
lanes = q->csi2.lanes;
- r = cio2_csi2_calc_timing(cio2, q, &timing);
+ r = cio2_csi2_calc_timing(cio2, q, &timing, fmt->bpp, lanes);
if (r)
return r;
@@ -561,7 +551,9 @@ static void cio2_buffer_done(struct cio2_device *cio2, unsigned int dma_chan)
b = q->bufs[q->bufs_first];
if (b) {
- unsigned int bytes = entry[1].second_entry.num_of_bytes;
+ unsigned int received = entry[1].second_entry.num_of_bytes;
+ unsigned long payload =
+ vb2_get_plane_payload(&b->vbb.vb2_buf, 0);
q->bufs[q->bufs_first] = NULL;
atomic_dec(&q->bufs_queued);
@@ -571,10 +563,10 @@ static void cio2_buffer_done(struct cio2_device *cio2, unsigned int dma_chan)
b->vbb.vb2_buf.timestamp = ns;
b->vbb.field = V4L2_FIELD_NONE;
b->vbb.sequence = atomic_read(&q->frame_sequence);
- if (b->vbb.vb2_buf.planes[0].length != bytes)
- dev_warn(dev, "buffer length is %d received %d\n",
- b->vbb.vb2_buf.planes[0].length,
- bytes);
+ if (payload != received)
+ dev_warn(dev,
+ "payload length is %lu, received %u\n",
+ payload, received);
vb2_buffer_done(&b->vbb.vb2_buf, VB2_BUF_STATE_DONE);
}
atomic_inc(&q->frame_sequence);
@@ -791,6 +783,7 @@ static void cio2_vb2_return_all_buffers(struct cio2_queue *q,
atomic_dec(&q->bufs_queued);
vb2_buffer_done(&q->bufs[i]->vbb.vb2_buf,
state);
+ q->bufs[i] = NULL;
}
}
}
@@ -1094,8 +1087,8 @@ static int cio2_v4l2_try_fmt(struct file *file, void *fh, struct v4l2_format *f)
/* Only supports up to 4224x3136 */
if (mpix->width > CIO2_IMAGE_MAX_WIDTH)
mpix->width = CIO2_IMAGE_MAX_WIDTH;
- if (mpix->height > CIO2_IMAGE_MAX_LENGTH)
- mpix->height = CIO2_IMAGE_MAX_LENGTH;
+ if (mpix->height > CIO2_IMAGE_MAX_HEIGHT)
+ mpix->height = CIO2_IMAGE_MAX_HEIGHT;
mpix->num_planes = 1;
mpix->pixelformat = fmt->fourcc;
@@ -1232,29 +1225,15 @@ static int cio2_subdev_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_format *fmt)
{
struct cio2_queue *q = container_of(sd, struct cio2_queue, subdev);
- struct v4l2_subdev_format format;
- int ret;
- if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
- fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
- return 0;
- }
-
- if (fmt->pad == CIO2_PAD_SINK) {
- format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
- ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
- &format);
+ mutex_lock(&q->subdev_lock);
- if (ret)
- return ret;
- /* update colorspace etc */
- q->subdev_fmt.colorspace = format.format.colorspace;
- q->subdev_fmt.ycbcr_enc = format.format.ycbcr_enc;
- q->subdev_fmt.quantization = format.format.quantization;
- q->subdev_fmt.xfer_func = format.format.xfer_func;
- }
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
+ fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
+ else
+ fmt->format = q->subdev_fmt;
- fmt->format = q->subdev_fmt;
+ mutex_unlock(&q->subdev_lock);
return 0;
}
@@ -1271,6 +1250,9 @@ static int cio2_subdev_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_format *fmt)
{
struct cio2_queue *q = container_of(sd, struct cio2_queue, subdev);
+ struct v4l2_mbus_framefmt *mbus;
+ u32 mbus_code = fmt->format.code;
+ unsigned int i;
/*
* Only allow setting sink pad format;
@@ -1279,16 +1261,28 @@ static int cio2_subdev_set_fmt(struct v4l2_subdev *sd,
if (fmt->pad == CIO2_PAD_SOURCE)
return cio2_subdev_get_fmt(sd, cfg, fmt);
- if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
- *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
- } else {
- /* It's the sink, allow changing frame size */
- q->subdev_fmt.width = fmt->format.width;
- q->subdev_fmt.height = fmt->format.height;
- q->subdev_fmt.code = fmt->format.code;
- fmt->format = q->subdev_fmt;
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
+ mbus = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
+ else
+ mbus = &q->subdev_fmt;
+
+ fmt->format.code = formats[0].mbus_code;
+
+ for (i = 0; i < ARRAY_SIZE(formats); i++) {
+ if (formats[i].mbus_code == fmt->format.code) {
+ fmt->format.code = mbus_code;
+ break;
+ }
}
+ fmt->format.width = min(fmt->format.width, CIO2_IMAGE_MAX_WIDTH);
+ fmt->format.height = min(fmt->format.height, CIO2_IMAGE_MAX_HEIGHT);
+ fmt->format.field = V4L2_FIELD_NONE;
+
+ mutex_lock(&q->subdev_lock);
+ *mbus = fmt->format;
+ mutex_unlock(&q->subdev_lock);
+
return 0;
}
@@ -1547,6 +1541,7 @@ static int cio2_queue_init(struct cio2_device *cio2, struct cio2_queue *q)
/* Initialize miscellaneous variables */
mutex_init(&q->lock);
+ mutex_init(&q->subdev_lock);
/* Initialize formats to default values */
fmt = &q->subdev_fmt;
@@ -1663,6 +1658,7 @@ fail_vdev_media_entity:
fail_subdev_media_entity:
cio2_fbpt_exit(q, &cio2->pci_dev->dev);
fail_fbpt:
+ mutex_destroy(&q->subdev_lock);
mutex_destroy(&q->lock);
return r;
@@ -1675,6 +1671,7 @@ static void cio2_queue_exit(struct cio2_device *cio2, struct cio2_queue *q)
v4l2_device_unregister_subdev(&q->subdev);
media_entity_cleanup(&q->subdev.entity);
cio2_fbpt_exit(q, &cio2->pci_dev->dev);
+ mutex_destroy(&q->subdev_lock);
mutex_destroy(&q->lock);
}
diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.h b/drivers/media/pci/intel/ipu3/ipu3-cio2.h
index 549b08f88f0c..ccf0b85ae36f 100644
--- a/drivers/media/pci/intel/ipu3/ipu3-cio2.h
+++ b/drivers/media/pci/intel/ipu3/ipu3-cio2.h
@@ -13,20 +13,20 @@
#define CIO2_PCI_BAR 0
#define CIO2_DMA_MASK DMA_BIT_MASK(39)
-#define CIO2_IMAGE_MAX_WIDTH 4224
-#define CIO2_IMAGE_MAX_LENGTH 3136
+#define CIO2_IMAGE_MAX_WIDTH 4224U
+#define CIO2_IMAGE_MAX_HEIGHT 3136U
/* 32MB = 8xFBPT_entry */
#define CIO2_MAX_LOPS 8
#define CIO2_MAX_BUFFERS (PAGE_SIZE / 16 / CIO2_MAX_LOPS)
#define CIO2_LOP_ENTRIES (PAGE_SIZE / sizeof(u32))
-#define CIO2_PAD_SINK 0
-#define CIO2_PAD_SOURCE 1
-#define CIO2_PADS 2
+#define CIO2_PAD_SINK 0U
+#define CIO2_PAD_SOURCE 1U
+#define CIO2_PADS 2U
-#define CIO2_NUM_DMA_CHAN 20
-#define CIO2_NUM_PORTS 4 /* DPHYs */
+#define CIO2_NUM_DMA_CHAN 20U
+#define CIO2_NUM_PORTS 4U /* DPHYs */
/* 1 for each sensor */
#define CIO2_QUEUES CIO2_NUM_PORTS
@@ -66,12 +66,12 @@
#define CIO2_REG_MIPIBE_FORCE_RAW8 (CIO2_REG_MIPIBE_BASE + 0x20)
#define CIO2_REG_MIPIBE_FORCE_RAW8_ENABLE BIT(0)
#define CIO2_REG_MIPIBE_FORCE_RAW8_USE_TYPEID BIT(1)
-#define CIO2_REG_MIPIBE_FORCE_RAW8_TYPEID_SHIFT 2
+#define CIO2_REG_MIPIBE_FORCE_RAW8_TYPEID_SHIFT 2U
#define CIO2_REG_MIPIBE_IRQ_STATUS (CIO2_REG_MIPIBE_BASE + 0x24)
#define CIO2_REG_MIPIBE_IRQ_CLEAR (CIO2_REG_MIPIBE_BASE + 0x28)
#define CIO2_REG_MIPIBE_GLOBAL_LUT_DISREGARD (CIO2_REG_MIPIBE_BASE + 0x68)
-#define CIO2_MIPIBE_GLOBAL_LUT_DISREGARD 1
+#define CIO2_MIPIBE_GLOBAL_LUT_DISREGARD 1U
#define CIO2_REG_MIPIBE_PKT_STALL_STATUS (CIO2_REG_MIPIBE_BASE + 0x6c)
#define CIO2_REG_MIPIBE_PARSE_GSP_THROUGH_LP_LUT_REG_IDX \
(CIO2_REG_MIPIBE_BASE + 0x70)
@@ -79,10 +79,10 @@
(CIO2_REG_MIPIBE_BASE + 0x74 + 4 * (vc))
#define CIO2_REG_MIPIBE_LP_LUT_ENTRY(m) /* m = 0..15 */ \
(CIO2_REG_MIPIBE_BASE + 0x84 + 4 * (m))
-#define CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD 1
-#define CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT 1
-#define CIO2_MIPIBE_LP_LUT_ENTRY_VC_SHIFT 5
-#define CIO2_MIPIBE_LP_LUT_ENTRY_FORMAT_TYPE_SHIFT 7
+#define CIO2_MIPIBE_LP_LUT_ENTRY_DISREGARD 1U
+#define CIO2_MIPIBE_LP_LUT_ENTRY_SID_SHIFT 1U
+#define CIO2_MIPIBE_LP_LUT_ENTRY_VC_SHIFT 5U
+#define CIO2_MIPIBE_LP_LUT_ENTRY_FORMAT_TYPE_SHIFT 7U
/* base register: CIO2_REG_PIPE_BASE(pipe) * CIO2_REG_IRQCTRL_BASE */
/* IRQ registers are 18-bit wide, see cio2_irq_error for bit definitions */
@@ -113,31 +113,31 @@
#define CIO2_CGC_ROSC_DCGE BIT(12)
#define CIO2_CGC_XOSC_DCGE BIT(13)
#define CIO2_CGC_FLIS_DCGE BIT(14)
-#define CIO2_CGC_CLKGATE_HOLDOFF_SHIFT 20
-#define CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT 24
+#define CIO2_CGC_CLKGATE_HOLDOFF_SHIFT 20U
+#define CIO2_CGC_CSI_CLKGATE_HOLDOFF_SHIFT 24U
#define CIO2_REG_D0I3C 0x1408
#define CIO2_D0I3C_I3 BIT(2) /* Set D0I3 */
#define CIO2_D0I3C_RR BIT(3) /* Restore? */
#define CIO2_REG_SWRESET 0x140c
-#define CIO2_SWRESET_SWRESET 1
+#define CIO2_SWRESET_SWRESET 1U
#define CIO2_REG_SENSOR_ACTIVE 0x1410
#define CIO2_REG_INT_STS 0x1414
#define CIO2_REG_INT_STS_EXT_OE 0x1418
-#define CIO2_INT_EXT_OE_DMAOE_SHIFT 0
+#define CIO2_INT_EXT_OE_DMAOE_SHIFT 0U
#define CIO2_INT_EXT_OE_DMAOE_MASK 0x7ffff
-#define CIO2_INT_EXT_OE_OES_SHIFT 24
+#define CIO2_INT_EXT_OE_OES_SHIFT 24U
#define CIO2_INT_EXT_OE_OES_MASK (0xf << CIO2_INT_EXT_OE_OES_SHIFT)
#define CIO2_REG_INT_EN 0x1420
#define CIO2_REG_INT_EN_IRQ (1 << 24)
-#define CIO2_REG_INT_EN_IOS(dma) (1 << (((dma) >> 1) + 12))
+#define CIO2_REG_INT_EN_IOS(dma) (1U << (((dma) >> 1U) + 12U))
/*
* Interrupt on completion bit, Eg. DMA 0-3 maps to bit 0-3,
* DMA4 & DMA5 map to bit 4 ... DMA18 & DMA19 map to bit 11 Et cetera
*/
-#define CIO2_INT_IOC(dma) (1 << ((dma) < 4 ? (dma) : ((dma) >> 1) + 2))
+#define CIO2_INT_IOC(dma) (1U << ((dma) < 4U ? (dma) : ((dma) >> 1U) + 2U))
#define CIO2_INT_IOC_SHIFT 0
#define CIO2_INT_IOC_MASK (0x7ff << CIO2_INT_IOC_SHIFT)
-#define CIO2_INT_IOS_IOLN(dma) (1 << (((dma) >> 1) + 12))
+#define CIO2_INT_IOS_IOLN(dma) (1U << (((dma) >> 1U) + 12U))
#define CIO2_INT_IOS_IOLN_SHIFT 12
#define CIO2_INT_IOS_IOLN_MASK (0x3ff << CIO2_INT_IOS_IOLN_SHIFT)
#define CIO2_INT_IOIE BIT(22)
@@ -145,32 +145,32 @@
#define CIO2_INT_IOIRQ BIT(24)
#define CIO2_REG_INT_EN_EXT_OE 0x1424
#define CIO2_REG_DMA_DBG 0x1448
-#define CIO2_REG_DMA_DBG_DMA_INDEX_SHIFT 0
+#define CIO2_REG_DMA_DBG_DMA_INDEX_SHIFT 0U
#define CIO2_REG_PBM_ARB_CTRL 0x1460
-#define CIO2_PBM_ARB_CTRL_LANES_DIV 0 /* 4-4-2-2 lanes */
-#define CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT 0
+#define CIO2_PBM_ARB_CTRL_LANES_DIV 0U /* 4-4-2-2 lanes */
+#define CIO2_PBM_ARB_CTRL_LANES_DIV_SHIFT 0U
#define CIO2_PBM_ARB_CTRL_LE_EN BIT(7)
-#define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN 2
-#define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT 8
-#define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP 480
-#define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP_SHIFT 16
+#define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN 2U
+#define CIO2_PBM_ARB_CTRL_PLL_POST_SHTDN_SHIFT 8U
+#define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP 480U
+#define CIO2_PBM_ARB_CTRL_PLL_AHD_WK_UP_SHIFT 16U
#define CIO2_REG_PBM_WMCTRL1 0x1464
-#define CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT 0
-#define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT 8
-#define CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT 16
+#define CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT 0U
+#define CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT 8U
+#define CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT 16U
#define CIO2_PBM_WMCTRL1_TS_COUNT_DISABLE BIT(31)
#define CIO2_PBM_WMCTRL1_MIN_2CK (4 << CIO2_PBM_WMCTRL1_MIN_2CK_SHIFT)
#define CIO2_PBM_WMCTRL1_MID1_2CK (16 << CIO2_PBM_WMCTRL1_MID1_2CK_SHIFT)
#define CIO2_PBM_WMCTRL1_MID2_2CK (21 << CIO2_PBM_WMCTRL1_MID2_2CK_SHIFT)
#define CIO2_REG_PBM_WMCTRL2 0x1468
-#define CIO2_PBM_WMCTRL2_HWM_2CK 40
-#define CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT 0
-#define CIO2_PBM_WMCTRL2_LWM_2CK 22
-#define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT 8
-#define CIO2_PBM_WMCTRL2_OBFFWM_2CK 2
-#define CIO2_PBM_WMCTRL2_OBFFWM_2CK_SHIFT 16
-#define CIO2_PBM_WMCTRL2_TRANSDYN 1
-#define CIO2_PBM_WMCTRL2_TRANSDYN_SHIFT 24
+#define CIO2_PBM_WMCTRL2_HWM_2CK 40U
+#define CIO2_PBM_WMCTRL2_HWM_2CK_SHIFT 0U
+#define CIO2_PBM_WMCTRL2_LWM_2CK 22U
+#define CIO2_PBM_WMCTRL2_LWM_2CK_SHIFT 8U
+#define CIO2_PBM_WMCTRL2_OBFFWM_2CK 2U
+#define CIO2_PBM_WMCTRL2_OBFFWM_2CK_SHIFT 16U
+#define CIO2_PBM_WMCTRL2_TRANSDYN 1U
+#define CIO2_PBM_WMCTRL2_TRANSDYN_SHIFT 24U
#define CIO2_PBM_WMCTRL2_DYNWMEN BIT(28)
#define CIO2_PBM_WMCTRL2_OBFF_MEM_EN BIT(29)
#define CIO2_PBM_WMCTRL2_OBFF_CPU_EN BIT(30)
@@ -178,12 +178,12 @@
#define CIO2_REG_PBM_TS_COUNT 0x146c
#define CIO2_REG_PBM_FOPN_ABORT 0x1474
/* below n = 0..3 */
-#define CIO2_PBM_FOPN_ABORT(n) (0x1 << 8 * (n))
-#define CIO2_PBM_FOPN_FORCE_ABORT(n) (0x2 << 8 * (n))
-#define CIO2_PBM_FOPN_FRAMEOPEN(n) (0x8 << 8 * (n))
+#define CIO2_PBM_FOPN_ABORT(n) (0x1 << 8U * (n))
+#define CIO2_PBM_FOPN_FORCE_ABORT(n) (0x2 << 8U * (n))
+#define CIO2_PBM_FOPN_FRAMEOPEN(n) (0x8 << 8U * (n))
#define CIO2_REG_LTRCTRL 0x1480
#define CIO2_LTRCTRL_LTRDYNEN BIT(16)
-#define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT 8
+#define CIO2_LTRCTRL_LTRSTABLETIME_SHIFT 8U
#define CIO2_LTRCTRL_LTRSTABLETIME_MASK 0xff
#define CIO2_LTRCTRL_LTRSEL1S3 BIT(7)
#define CIO2_LTRCTRL_LTRSEL1S2 BIT(6)
@@ -195,28 +195,28 @@
#define CIO2_LTRCTRL_LTRSEL2S0 BIT(0)
#define CIO2_REG_LTRVAL23 0x1484
#define CIO2_REG_LTRVAL01 0x1488
-#define CIO2_LTRVAL02_VAL_SHIFT 0
-#define CIO2_LTRVAL02_SCALE_SHIFT 10
-#define CIO2_LTRVAL13_VAL_SHIFT 16
-#define CIO2_LTRVAL13_SCALE_SHIFT 26
+#define CIO2_LTRVAL02_VAL_SHIFT 0U
+#define CIO2_LTRVAL02_SCALE_SHIFT 10U
+#define CIO2_LTRVAL13_VAL_SHIFT 16U
+#define CIO2_LTRVAL13_SCALE_SHIFT 26U
-#define CIO2_LTRVAL0_VAL 175
+#define CIO2_LTRVAL0_VAL 175U
/* Value times 1024 ns */
-#define CIO2_LTRVAL0_SCALE 2
-#define CIO2_LTRVAL1_VAL 90
-#define CIO2_LTRVAL1_SCALE 2
-#define CIO2_LTRVAL2_VAL 90
-#define CIO2_LTRVAL2_SCALE 2
-#define CIO2_LTRVAL3_VAL 90
-#define CIO2_LTRVAL3_SCALE 2
+#define CIO2_LTRVAL0_SCALE 2U
+#define CIO2_LTRVAL1_VAL 90U
+#define CIO2_LTRVAL1_SCALE 2U
+#define CIO2_LTRVAL2_VAL 90U
+#define CIO2_LTRVAL2_SCALE 2U
+#define CIO2_LTRVAL3_VAL 90U
+#define CIO2_LTRVAL3_SCALE 2U
#define CIO2_REG_CDMABA(n) (0x1500 + 0x10 * (n)) /* n = 0..19 */
#define CIO2_REG_CDMARI(n) (0x1504 + 0x10 * (n))
-#define CIO2_CDMARI_FBPT_RP_SHIFT 0
+#define CIO2_CDMARI_FBPT_RP_SHIFT 0U
#define CIO2_CDMARI_FBPT_RP_MASK 0xff
#define CIO2_REG_CDMAC0(n) (0x1508 + 0x10 * (n))
-#define CIO2_CDMAC0_FBPT_LEN_SHIFT 0
-#define CIO2_CDMAC0_FBPT_WIDTH_SHIFT 8
+#define CIO2_CDMAC0_FBPT_LEN_SHIFT 0U
+#define CIO2_CDMAC0_FBPT_WIDTH_SHIFT 8U
#define CIO2_CDMAC0_FBPT_NS BIT(25)
#define CIO2_CDMAC0_DMA_INTR_ON_FS BIT(26)
#define CIO2_CDMAC0_DMA_INTR_ON_FE BIT(27)
@@ -225,12 +225,12 @@
#define CIO2_CDMAC0_DMA_EN BIT(30)
#define CIO2_CDMAC0_DMA_HALTED BIT(31)
#define CIO2_REG_CDMAC1(n) (0x150c + 0x10 * (n))
-#define CIO2_CDMAC1_LINENUMINT_SHIFT 0
-#define CIO2_CDMAC1_LINENUMUPDATE_SHIFT 16
+#define CIO2_CDMAC1_LINENUMINT_SHIFT 0U
+#define CIO2_CDMAC1_LINENUMUPDATE_SHIFT 16U
/* n = 0..3 */
#define CIO2_REG_PXM_PXF_FMT_CFG0(n) (0x1700 + 0x30 * (n))
-#define CIO2_PXM_PXF_FMT_CFG_SID0_SHIFT 0
-#define CIO2_PXM_PXF_FMT_CFG_SID1_SHIFT 16
+#define CIO2_PXM_PXF_FMT_CFG_SID0_SHIFT 0U
+#define CIO2_PXM_PXF_FMT_CFG_SID1_SHIFT 16U
#define CIO2_PXM_PXF_FMT_CFG_PCK_64B (0 << 0)
#define CIO2_PXM_PXF_FMT_CFG_PCK_32B (1 << 0)
#define CIO2_PXM_PXF_FMT_CFG_BPP_08 (0 << 2)
@@ -249,27 +249,27 @@
#define CIO2_PXM_PXF_FMT_CFG_PSWAP4_2ND_BD (1 << 10)
#define CIO2_REG_INT_STS_EXT_IE 0x17e4
#define CIO2_REG_INT_EN_EXT_IE 0x17e8
-#define CIO2_INT_EXT_IE_ECC_RE(n) (0x01 << (8 * (n)))
-#define CIO2_INT_EXT_IE_DPHY_NR(n) (0x02 << (8 * (n)))
-#define CIO2_INT_EXT_IE_ECC_NR(n) (0x04 << (8 * (n)))
-#define CIO2_INT_EXT_IE_CRCERR(n) (0x08 << (8 * (n)))
-#define CIO2_INT_EXT_IE_INTERFRAMEDATA(n) (0x10 << (8 * (n)))
-#define CIO2_INT_EXT_IE_PKT2SHORT(n) (0x20 << (8 * (n)))
-#define CIO2_INT_EXT_IE_PKT2LONG(n) (0x40 << (8 * (n)))
-#define CIO2_INT_EXT_IE_IRQ(n) (0x80 << (8 * (n)))
+#define CIO2_INT_EXT_IE_ECC_RE(n) (0x01 << (8U * (n)))
+#define CIO2_INT_EXT_IE_DPHY_NR(n) (0x02 << (8U * (n)))
+#define CIO2_INT_EXT_IE_ECC_NR(n) (0x04 << (8U * (n)))
+#define CIO2_INT_EXT_IE_CRCERR(n) (0x08 << (8U * (n)))
+#define CIO2_INT_EXT_IE_INTERFRAMEDATA(n) (0x10 << (8U * (n)))
+#define CIO2_INT_EXT_IE_PKT2SHORT(n) (0x20 << (8U * (n)))
+#define CIO2_INT_EXT_IE_PKT2LONG(n) (0x40 << (8U * (n)))
+#define CIO2_INT_EXT_IE_IRQ(n) (0x80 << (8U * (n)))
#define CIO2_REG_PXM_FRF_CFG(n) (0x1720 + 0x30 * (n))
#define CIO2_PXM_FRF_CFG_FNSEL BIT(0)
#define CIO2_PXM_FRF_CFG_FN_RST BIT(1)
#define CIO2_PXM_FRF_CFG_ABORT BIT(2)
-#define CIO2_PXM_FRF_CFG_CRC_TH_SHIFT 3
+#define CIO2_PXM_FRF_CFG_CRC_TH_SHIFT 3U
#define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NR BIT(8)
#define CIO2_PXM_FRF_CFG_MSK_ECC_RE BIT(9)
#define CIO2_PXM_FRF_CFG_MSK_ECC_DPHY_NE BIT(10)
-#define CIO2_PXM_FRF_CFG_EVEN_ODD_MODE_SHIFT 11
+#define CIO2_PXM_FRF_CFG_EVEN_ODD_MODE_SHIFT 11U
#define CIO2_PXM_FRF_CFG_MASK_CRC_THRES BIT(13)
#define CIO2_PXM_FRF_CFG_MASK_CSI_ACCEPT BIT(14)
#define CIO2_PXM_FRF_CFG_CIOHC_FS_MODE BIT(15)
-#define CIO2_PXM_FRF_CFG_CIOHC_FRST_FRM_SHIFT 16
+#define CIO2_PXM_FRF_CFG_CIOHC_FRST_FRM_SHIFT 16U
#define CIO2_REG_PXM_SID2BID0(n) (0x1724 + 0x30 * (n))
#define CIO2_FB_HPLL_FREQ 0x2
#define CIO2_ISCLK_RATIO 0xc
@@ -278,14 +278,14 @@
#define CIO2_INT_EN_EXT_OE_MASK 0x8f0fffff
-#define CIO2_CGC_CLKGATE_HOLDOFF 3
-#define CIO2_CGC_CSI_CLKGATE_HOLDOFF 5
+#define CIO2_CGC_CLKGATE_HOLDOFF 3U
+#define CIO2_CGC_CSI_CLKGATE_HOLDOFF 5U
#define CIO2_PXM_FRF_CFG_CRC_TH 16
#define CIO2_INT_EN_EXT_IE_MASK 0xffffffff
-#define CIO2_DMA_CHAN 0
+#define CIO2_DMA_CHAN 0U
#define CIO2_CSIRX_DLY_CNT_CLANE_IDX -1
@@ -302,8 +302,8 @@
#define CIO2_CSIRX_DLY_CNT_TERMEN_DEFAULT 0x4
#define CIO2_CSIRX_DLY_CNT_SETTLE_DEFAULT 0x570
-#define CIO2_PMCSR_OFFSET 4
-#define CIO2_PMCSR_D0D3_SHIFT 2
+#define CIO2_PMCSR_OFFSET 4U
+#define CIO2_PMCSR_D0D3_SHIFT 2U
#define CIO2_PMCSR_D3 0x3
struct cio2_csi2_timing {
@@ -335,6 +335,7 @@ struct cio2_queue {
/* Subdev, /dev/v4l-subdevX */
struct v4l2_subdev subdev;
+ struct mutex subdev_lock; /* Serialise acces to subdev_fmt field */
struct media_pad subdev_pads[CIO2_PADS];
struct v4l2_mbus_framefmt subdev_fmt;
atomic_t frame_sequence;
diff --git a/drivers/media/pci/mantis/hopper_vp3028.c b/drivers/media/pci/mantis/hopper_vp3028.c
index 37bd386f3ed8..ce1e8737b14b 100644
--- a/drivers/media/pci/mantis/hopper_vp3028.c
+++ b/drivers/media/pci/mantis/hopper_vp3028.c
@@ -33,7 +33,7 @@ static int vp3028_frontend_init(struct mantis_pci *mantis, struct dvb_frontend *
{
struct i2c_adapter *adapter = &mantis->adapter;
struct mantis_hwconfig *config = mantis->hwconfig;
- int err = 0;
+ int err;
mantis_gpio_set_bits(mantis, config->reset, 0);
msleep(100);
diff --git a/drivers/media/pci/saa7134/saa7134-video.c b/drivers/media/pci/saa7134/saa7134-video.c
index 9a6a6b68f8e3..0f9d6b9edb90 100644
--- a/drivers/media/pci/saa7134/saa7134-video.c
+++ b/drivers/media/pci/saa7134/saa7134-video.c
@@ -868,8 +868,11 @@ static int buffer_activate(struct saa7134_dev *dev,
lines_uv = dev->height >> dev->fmt->vshift;
base2 = base + bpl * dev->height;
base3 = base2 + bpl_uv * lines_uv;
- if (dev->fmt->uvswap)
- tmp = base2, base2 = base3, base3 = tmp;
+ if (dev->fmt->uvswap) {
+ tmp = base2;
+ base2 = base3;
+ base3 = tmp;
+ }
video_dbg("uv: bpl=%ld lines=%ld base2/3=%ld/%ld\n",
bpl_uv,lines_uv,base2,base3);
if (V4L2_FIELD_HAS_BOTH(dev->field)) {
@@ -1265,9 +1268,7 @@ static int saa7134_g_fmt_vid_overlay(struct file *file, void *priv,
struct v4l2_format *f)
{
struct saa7134_dev *dev = video_drvdata(file);
- struct v4l2_clip __user *clips = f->fmt.win.clips;
u32 clipcount = f->fmt.win.clipcount;
- int err = 0;
int i;
if (saa7134_no_overlay > 0) {
@@ -1275,20 +1276,20 @@ static int saa7134_g_fmt_vid_overlay(struct file *file, void *priv,
return -EINVAL;
}
f->fmt.win = dev->win;
- f->fmt.win.clips = clips;
- if (clips == NULL)
- clipcount = 0;
+ if (!f->fmt.win.clips) {
+ f->fmt.win.clipcount = 0;
+ return 0;
+ }
if (dev->nclips < clipcount)
clipcount = dev->nclips;
f->fmt.win.clipcount = clipcount;
- for (i = 0; !err && i < clipcount; i++) {
- if (copy_to_user(&f->fmt.win.clips[i].c, &dev->clips[i].c,
- sizeof(struct v4l2_rect)))
- err = -EFAULT;
+ for (i = 0; i < clipcount; i++) {
+ memcpy(&f->fmt.win.clips[i].c, &dev->clips[i].c,
+ sizeof(struct v4l2_rect));
}
- return err;
+ return 0;
}
static int saa7134_try_fmt_vid_cap(struct file *file, void *priv,
@@ -1396,9 +1397,8 @@ static int saa7134_s_fmt_vid_overlay(struct file *file, void *priv,
dev->win = f->fmt.win;
dev->nclips = f->fmt.win.clipcount;
- if (copy_from_user(dev->clips, f->fmt.win.clips,
- sizeof(struct v4l2_clip) * dev->nclips))
- return -EFAULT;
+ memcpy(dev->clips, f->fmt.win.clips,
+ sizeof(struct v4l2_clip) * dev->nclips);
if (priv == dev->overlay_owner) {
spin_lock_irqsave(&dev->slock, flags);
diff --git a/drivers/media/pci/saa7146/mxb.c b/drivers/media/pci/saa7146/mxb.c
index 129a1f8ebe1a..73fc901ecf3d 100644
--- a/drivers/media/pci/saa7146/mxb.c
+++ b/drivers/media/pci/saa7146/mxb.c
@@ -641,16 +641,17 @@ static int vidioc_s_audio(struct file *file, void *fh, const struct v4l2_audio *
struct mxb *mxb = (struct mxb *)dev->ext_priv;
DEB_D("VIDIOC_S_AUDIO %d\n", a->index);
- if (mxb_inputs[mxb->cur_input].audioset & (1 << a->index)) {
- if (mxb->cur_audinput != a->index) {
- mxb->cur_audinput = a->index;
- tea6420_route(mxb, a->index);
- if (mxb->cur_audinput == 0)
- mxb_update_audmode(mxb);
- }
- return 0;
+ if (a->index >= 32 ||
+ !(mxb_inputs[mxb->cur_input].audioset & (1 << a->index)))
+ return -EINVAL;
+
+ if (mxb->cur_audinput != a->index) {
+ mxb->cur_audinput = a->index;
+ tea6420_route(mxb, a->index);
+ if (mxb->cur_audinput == 0)
+ mxb_update_audmode(mxb);
}
- return -EINVAL;
+ return 0;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
diff --git a/drivers/media/pci/saa7164/saa7164-core.c b/drivers/media/pci/saa7164/saa7164-core.c
index 6c08b77bfd47..f3a4e575a782 100644
--- a/drivers/media/pci/saa7164/saa7164-core.c
+++ b/drivers/media/pci/saa7164/saa7164-core.c
@@ -1139,32 +1139,21 @@ static int saa7164_seq_show(struct seq_file *m, void *v)
return 0;
}
-static const struct seq_operations saa7164_seq_ops = {
+static const struct seq_operations saa7164_sops = {
.start = saa7164_seq_start,
.next = saa7164_seq_next,
.stop = saa7164_seq_stop,
.show = saa7164_seq_show,
};
-static int saa7164_open(struct inode *inode, struct file *file)
-{
- return seq_open(file, &saa7164_seq_ops);
-}
-
-static const struct file_operations saa7164_operations = {
- .owner = THIS_MODULE,
- .open = saa7164_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release,
-};
+DEFINE_SEQ_ATTRIBUTE(saa7164);
static struct dentry *saa7614_dentry;
static void __init saa7164_debugfs_create(void)
{
saa7614_dentry = debugfs_create_file("saa7164", 0444, NULL, NULL,
- &saa7164_operations);
+ &saa7164_fops);
}
static void __exit saa7164_debugfs_remove(void)
diff --git a/drivers/media/pci/solo6x10/solo6x10-g723.c b/drivers/media/pci/solo6x10/solo6x10-g723.c
index 906ce86437ae..6cebad665565 100644
--- a/drivers/media/pci/solo6x10/solo6x10-g723.c
+++ b/drivers/media/pci/solo6x10/solo6x10-g723.c
@@ -124,9 +124,10 @@ static int snd_solo_pcm_open(struct snd_pcm_substream *ss)
if (solo_pcm == NULL)
goto oom;
- solo_pcm->g723_buf = pci_alloc_consistent(solo_dev->pdev,
- G723_PERIOD_BYTES,
- &solo_pcm->g723_dma);
+ solo_pcm->g723_buf = dma_alloc_coherent(&solo_dev->pdev->dev,
+ G723_PERIOD_BYTES,
+ &solo_pcm->g723_dma,
+ GFP_KERNEL);
if (solo_pcm->g723_buf == NULL)
goto oom;
@@ -148,8 +149,8 @@ static int snd_solo_pcm_close(struct snd_pcm_substream *ss)
struct solo_snd_pcm *solo_pcm = snd_pcm_substream_chip(ss);
snd_pcm_substream_chip(ss) = solo_pcm->solo_dev;
- pci_free_consistent(solo_pcm->solo_dev->pdev, G723_PERIOD_BYTES,
- solo_pcm->g723_buf, solo_pcm->g723_dma);
+ dma_free_coherent(&solo_pcm->solo_dev->pdev->dev, G723_PERIOD_BYTES,
+ solo_pcm->g723_buf, solo_pcm->g723_dma);
kfree(solo_pcm);
return 0;
@@ -385,7 +386,7 @@ int solo_g723_init(struct solo_dev *solo_dev)
ret = snd_ctl_add(card, snd_ctl_new1(&kctl, solo_dev));
if (ret < 0)
- return ret;
+ goto snd_error;
ret = solo_snd_pcm_init(solo_dev);
if (ret < 0)
diff --git a/drivers/media/pci/solo6x10/solo6x10-p2m.c b/drivers/media/pci/solo6x10/solo6x10-p2m.c
index db2afc6a5fcb..ca70a864a3ef 100644
--- a/drivers/media/pci/solo6x10/solo6x10-p2m.c
+++ b/drivers/media/pci/solo6x10/solo6x10-p2m.c
@@ -37,16 +37,16 @@ int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
if (WARN_ON_ONCE(!size))
return -EINVAL;
- dma_addr = pci_map_single(solo_dev->pdev, sys_addr, size,
- wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
- if (pci_dma_mapping_error(solo_dev->pdev, dma_addr))
+ dma_addr = dma_map_single(&solo_dev->pdev->dev, sys_addr, size,
+ wr ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+ if (dma_mapping_error(&solo_dev->pdev->dev, dma_addr))
return -ENOMEM;
ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
repeat, ext_size);
- pci_unmap_single(solo_dev->pdev, dma_addr, size,
- wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
+ dma_unmap_single(&solo_dev->pdev->dev, dma_addr, size,
+ wr ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
return ret;
}
diff --git a/drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c b/drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c
index 3cf7bd6186aa..0abcad4e84fa 100644
--- a/drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c
+++ b/drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c
@@ -1286,10 +1286,11 @@ static struct solo_enc_dev *solo_enc_alloc(struct solo_dev *solo_dev,
memcpy(solo_enc->jpeg_header, jpeg_header, solo_enc->jpeg_len);
solo_enc->desc_nelts = 32;
- solo_enc->desc_items = pci_alloc_consistent(solo_dev->pdev,
- sizeof(struct solo_p2m_desc) *
- solo_enc->desc_nelts,
- &solo_enc->desc_dma);
+ solo_enc->desc_items = dma_alloc_coherent(&solo_dev->pdev->dev,
+ sizeof(struct solo_p2m_desc) *
+ solo_enc->desc_nelts,
+ &solo_enc->desc_dma,
+ GFP_KERNEL);
ret = -ENOMEM;
if (solo_enc->desc_items == NULL)
goto hdl_free;
@@ -1317,9 +1318,9 @@ static struct solo_enc_dev *solo_enc_alloc(struct solo_dev *solo_dev,
vdev_release:
video_device_release(solo_enc->vfd);
pci_free:
- pci_free_consistent(solo_enc->solo_dev->pdev,
- sizeof(struct solo_p2m_desc) * solo_enc->desc_nelts,
- solo_enc->desc_items, solo_enc->desc_dma);
+ dma_free_coherent(&solo_enc->solo_dev->pdev->dev,
+ sizeof(struct solo_p2m_desc) * solo_enc->desc_nelts,
+ solo_enc->desc_items, solo_enc->desc_dma);
hdl_free:
v4l2_ctrl_handler_free(hdl);
kfree(solo_enc);
@@ -1331,9 +1332,9 @@ static void solo_enc_free(struct solo_enc_dev *solo_enc)
if (solo_enc == NULL)
return;
- pci_free_consistent(solo_enc->solo_dev->pdev,
- sizeof(struct solo_p2m_desc) * solo_enc->desc_nelts,
- solo_enc->desc_items, solo_enc->desc_dma);
+ dma_free_coherent(&solo_enc->solo_dev->pdev->dev,
+ sizeof(struct solo_p2m_desc) * solo_enc->desc_nelts,
+ solo_enc->desc_items, solo_enc->desc_dma);
video_unregister_device(solo_enc->vfd);
v4l2_ctrl_handler_free(&solo_enc->hdl);
kfree(solo_enc);
@@ -1346,9 +1347,9 @@ int solo_enc_v4l2_init(struct solo_dev *solo_dev, unsigned nr)
init_waitqueue_head(&solo_dev->ring_thread_wait);
solo_dev->vh_size = sizeof(vop_header);
- solo_dev->vh_buf = pci_alloc_consistent(solo_dev->pdev,
- solo_dev->vh_size,
- &solo_dev->vh_dma);
+ solo_dev->vh_buf = dma_alloc_coherent(&solo_dev->pdev->dev,
+ solo_dev->vh_size,
+ &solo_dev->vh_dma, GFP_KERNEL);
if (solo_dev->vh_buf == NULL)
return -ENOMEM;
@@ -1363,8 +1364,8 @@ int solo_enc_v4l2_init(struct solo_dev *solo_dev, unsigned nr)
while (i--)
solo_enc_free(solo_dev->v4l2_enc[i]);
- pci_free_consistent(solo_dev->pdev, solo_dev->vh_size,
- solo_dev->vh_buf, solo_dev->vh_dma);
+ dma_free_coherent(&solo_dev->pdev->dev, solo_dev->vh_size,
+ solo_dev->vh_buf, solo_dev->vh_dma);
solo_dev->vh_buf = NULL;
return ret;
}
@@ -1391,6 +1392,6 @@ void solo_enc_v4l2_exit(struct solo_dev *solo_dev)
solo_enc_free(solo_dev->v4l2_enc[i]);
if (solo_dev->vh_buf)
- pci_free_consistent(solo_dev->pdev, solo_dev->vh_size,
- solo_dev->vh_buf, solo_dev->vh_dma);
+ dma_free_coherent(&solo_dev->pdev->dev, solo_dev->vh_size,
+ solo_dev->vh_buf, solo_dev->vh_dma);
}
diff --git a/drivers/media/pci/ttpci/av7110.c b/drivers/media/pci/ttpci/av7110.c
index 2f7069e19b78..d74ee0ecfb36 100644
--- a/drivers/media/pci/ttpci/av7110.c
+++ b/drivers/media/pci/ttpci/av7110.c
@@ -1250,7 +1250,8 @@ static void vpeirq(struct tasklet_struct *t)
return;
/* Ensure streamed PCI data is synced to CPU */
- pci_dma_sync_sg_for_cpu(budget->dev->pci, budget->pt.slist, budget->pt.nents, PCI_DMA_FROMDEVICE);
+ dma_sync_sg_for_cpu(&budget->dev->pci->dev, budget->pt.slist,
+ budget->pt.nents, DMA_FROM_DEVICE);
#if 0
/* track rps1 activity */
@@ -2637,7 +2638,8 @@ static int av7110_attach(struct saa7146_dev* dev,
av7110->arm_thread = NULL;
/* allocate and init buffers */
- av7110->debi_virt = pci_alloc_consistent(pdev, 8192, &av7110->debi_bus);
+ av7110->debi_virt = dma_alloc_coherent(&pdev->dev, 8192,
+ &av7110->debi_bus, GFP_KERNEL);
if (!av7110->debi_virt)
goto err_saa71466_vfree_4;
@@ -2726,7 +2728,8 @@ err_av7110_av_exit_7:
err_iobuf_vfree_6:
vfree(av7110->iobuf);
err_pci_free_5:
- pci_free_consistent(pdev, 8192, av7110->debi_virt, av7110->debi_bus);
+ dma_free_coherent(&pdev->dev, 8192, av7110->debi_virt,
+ av7110->debi_bus);
err_saa71466_vfree_4:
if (av7110->grabbing)
saa7146_vfree_destroy_pgtable(pdev, av7110->grabbing, &av7110->pt);
@@ -2779,8 +2782,8 @@ static int av7110_detach(struct saa7146_dev* saa)
av7110_av_exit(av7110);
vfree(av7110->iobuf);
- pci_free_consistent(saa->pci, 8192, av7110->debi_virt,
- av7110->debi_bus);
+ dma_free_coherent(&saa->pci->dev, 8192, av7110->debi_virt,
+ av7110->debi_bus);
i2c_del_adapter(&av7110->i2c_adap);
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 7e152bbb4fa6..35a18d388f3f 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -147,6 +147,24 @@ config VIDEO_RENESAS_CEU
help
This is a v4l2 driver for the Renesas CEU Interface
+config VIDEO_ROCKCHIP_ISP1
+ tristate "Rockchip Image Signal Processing v1 Unit driver"
+ depends on VIDEO_V4L2 && OF
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select VIDEOBUF2_DMA_CONTIG
+ select VIDEOBUF2_VMALLOC
+ select V4L2_FWNODE
+ select GENERIC_PHY_MIPI_DPHY
+ default n
+ help
+ Enable this to support the Image Signal Processing (ISP) module
+ present in RK3399 SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called rockchip-isp1.
+
source "drivers/media/platform/exynos4-is/Kconfig"
source "drivers/media/platform/am437x/Kconfig"
source "drivers/media/platform/xilinx/Kconfig"
@@ -183,7 +201,7 @@ if V4L_MEM2MEM_DRIVERS
config VIDEO_CODA
tristate "Chips&Media Coda multi-standard codec IP"
- depends on VIDEO_DEV && VIDEO_V4L2 && (ARCH_MXC || COMPILE_TEST)
+ depends on VIDEO_DEV && VIDEO_V4L2 && OF && (ARCH_MXC || COMPILE_TEST)
select SRAM
select VIDEOBUF2_DMA_CONTIG
select VIDEOBUF2_VMALLOC
@@ -288,6 +306,19 @@ config VIDEO_MEM2MEM_DEINTERLACE
help
Generic deinterlacing V4L2 driver.
+config VIDEO_MESON_GE2D
+ tristate "Amlogic 2D Graphic Acceleration Unit"
+ depends on VIDEO_DEV && VIDEO_V4L2
+ depends on ARCH_MESON || COMPILE_TEST
+ select VIDEOBUF2_DMA_CONTIG
+ select V4L2_MEM2MEM_DEV
+ help
+ This is a v4l2 driver for Amlogic GE2D 2D graphics accelerator.
+ GE2D is a standalone 2D graphic acceleration unit, with color converter,
+ image scaling, BitBLT & alpha blending operations.
+
+ To compile this driver as a module choose m here.
+
config VIDEO_SAMSUNG_S5P_G2D
tristate "Samsung S5P and EXYNOS4 G2D 2d graphics accelerator driver"
depends on VIDEO_DEV && VIDEO_V4L2
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 62b6cdc8c730..1d63aa956bcd 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o
obj-$(CONFIG_VIDEO_RENESAS_JPU) += rcar_jpu.o
obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/
+obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += rockchip/rkisp1/
obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip/rga/
obj-y += omap/
@@ -80,3 +81,5 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss/
obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/
obj-y += sunxi/
+
+obj-$(CONFIG_VIDEO_MESON_GE2D) += meson/ge2d/
diff --git a/drivers/media/platform/coda/coda-bit.c b/drivers/media/platform/coda/coda-bit.c
index bf75927bac4e..2f42808c43a4 100644
--- a/drivers/media/platform/coda/coda-bit.c
+++ b/drivers/media/platform/coda/coda-bit.c
@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/platform_device.h>
+#include <linux/ratelimit.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
@@ -293,12 +294,11 @@ static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
coda_dbg(1, ctx,
"could not parse header, sequence initialization might fail\n");
}
- }
- /* Add padding before the first buffer, if it is too small */
- if (ctx->qsequence == 0 && payload < 512 &&
- ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
- coda_h264_bitstream_pad(ctx, 512 - payload);
+ /* Add padding before the first buffer, if it is too small */
+ if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
+ coda_h264_bitstream_pad(ctx, 512 - payload);
+ }
ret = coda_bitstream_queue(ctx, vaddr, payload);
if (ret < 0) {
@@ -1837,6 +1837,29 @@ static bool coda_reorder_enable(struct coda_ctx *ctx)
return profile > V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
}
+static void coda_decoder_drop_used_metas(struct coda_ctx *ctx)
+{
+ struct coda_buffer_meta *meta, *tmp;
+
+ /*
+ * All metas that end at or before the RD pointer (fifo out),
+ * are now consumed by the VPU and should be released.
+ */
+ spin_lock(&ctx->buffer_meta_lock);
+ list_for_each_entry_safe(meta, tmp, &ctx->buffer_meta_list, list) {
+ if (ctx->bitstream_fifo.kfifo.out >= meta->end) {
+ coda_dbg(2, ctx, "releasing meta: seq=%d start=%d end=%d\n",
+ meta->sequence, meta->start, meta->end);
+
+ list_del(&meta->list);
+ ctx->num_metas--;
+ ctx->first_frame_sequence++;
+ kfree(meta);
+ }
+ }
+ spin_unlock(&ctx->buffer_meta_lock);
+}
+
static int __coda_decoder_seq_init(struct coda_ctx *ctx)
{
struct coda_q_data *q_data_src, *q_data_dst;
@@ -1922,10 +1945,17 @@ static int __coda_decoder_seq_init(struct coda_ctx *ctx)
}
ctx->sequence_offset = ~0U;
ctx->initialized = 1;
+ ctx->first_frame_sequence = 0;
/* Update kfifo out pointer from coda bitstream read pointer */
coda_kfifo_sync_from_device(ctx);
+ /*
+ * After updating the read pointer, we need to check if
+ * any metas are consumed and should be released.
+ */
+ coda_decoder_drop_used_metas(ctx);
+
if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
v4l2_err(&dev->v4l2_dev,
"CODA_COMMAND_SEQ_INIT failed, error code = 0x%x\n",
@@ -2005,21 +2035,13 @@ static void coda_dec_seq_init_work(struct work_struct *work)
struct coda_ctx *ctx = container_of(work,
struct coda_ctx, seq_init_work);
struct coda_dev *dev = ctx->dev;
- int ret;
mutex_lock(&ctx->buffer_mutex);
mutex_lock(&dev->coda_mutex);
- if (ctx->initialized == 1)
- goto out;
-
- ret = __coda_decoder_seq_init(ctx);
- if (ret < 0)
- goto out;
-
- ctx->initialized = 1;
+ if (!ctx->initialized)
+ __coda_decoder_seq_init(ctx);
-out:
mutex_unlock(&dev->coda_mutex);
mutex_unlock(&ctx->buffer_mutex);
}
@@ -2348,9 +2370,12 @@ static void coda_finish_decode(struct coda_ctx *ctx)
}
err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
- if (err_mb > 0)
- v4l2_err(&dev->v4l2_dev,
- "errors in %d macroblocks\n", err_mb);
+ if (err_mb > 0) {
+ if (__ratelimit(&dev->mb_err_rs))
+ coda_dbg(1, ctx, "errors in %d macroblocks\n", err_mb);
+ v4l2_ctrl_s_ctrl(ctx->mb_err_cnt_ctrl,
+ v4l2_ctrl_g_ctrl(ctx->mb_err_cnt_ctrl) + err_mb);
+ }
if (dev->devtype->product == CODA_HX4 ||
dev->devtype->product == CODA_7541) {
@@ -2404,12 +2429,16 @@ static void coda_finish_decode(struct coda_ctx *ctx)
v4l2_err(&dev->v4l2_dev,
"decoded frame index out of range: %d\n", decoded_idx);
} else {
+ int sequence;
+
decoded_frame = &ctx->internal_frames[decoded_idx];
val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM);
if (ctx->sequence_offset == -1)
ctx->sequence_offset = val;
- val -= ctx->sequence_offset;
+
+ sequence = val + ctx->first_frame_sequence
+ - ctx->sequence_offset;
spin_lock(&ctx->buffer_meta_lock);
if (!list_empty(&ctx->buffer_meta_list)) {
meta = list_first_entry(&ctx->buffer_meta_list,
@@ -2424,10 +2453,10 @@ static void coda_finish_decode(struct coda_ctx *ctx)
* should be enough to detect most errors and saves us
* from doing different things based on the format.
*/
- if ((val & 0xffff) != (meta->sequence & 0xffff)) {
+ if ((sequence & 0xffff) != (meta->sequence & 0xffff)) {
v4l2_err(&dev->v4l2_dev,
"sequence number mismatch (%d(%d) != %d)\n",
- val, ctx->sequence_offset,
+ sequence, ctx->sequence_offset,
meta->sequence);
}
decoded_frame->meta = *meta;
@@ -2437,7 +2466,7 @@ static void coda_finish_decode(struct coda_ctx *ctx)
v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
memset(&decoded_frame->meta, 0,
sizeof(struct coda_buffer_meta));
- decoded_frame->meta.sequence = val;
+ decoded_frame->meta.sequence = sequence;
decoded_frame->meta.last = false;
ctx->sequence_offset++;
}
diff --git a/drivers/media/platform/coda/coda-common.c b/drivers/media/platform/coda/coda-common.c
index 87a2c706f747..995e95272e51 100644
--- a/drivers/media/platform/coda/coda-common.c
+++ b/drivers/media/platform/coda/coda-common.c
@@ -25,7 +25,7 @@
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/of.h>
-#include <linux/platform_data/media/coda.h>
+#include <linux/ratelimit.h>
#include <linux/reset.h>
#include <media/v4l2-ctrls.h>
@@ -172,7 +172,7 @@ struct coda_video_device {
};
static const struct coda_video_device coda_bit_encoder = {
- .name = "coda-encoder",
+ .name = "coda-video-encoder",
.type = CODA_INST_ENCODER,
.ops = &coda_bit_encode_ops,
.src_formats = {
@@ -202,7 +202,7 @@ static const struct coda_video_device coda_bit_jpeg_encoder = {
};
static const struct coda_video_device coda_bit_decoder = {
- .name = "coda-decoder",
+ .name = "coda-video-decoder",
.type = CODA_INST_DECODER,
.ops = &coda_bit_decode_ops,
.src_formats = {
@@ -2062,6 +2062,7 @@ static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
if (q_data_dst->fourcc == V4L2_PIX_FMT_JPEG)
ctx->params.gop_size = 1;
ctx->gopcounter = ctx->params.gop_size - 1;
+ v4l2_ctrl_s_ctrl(ctx->mb_err_cnt_ctrl, 0);
ret = ctx->ops->start_streaming(ctx);
if (ctx->inst_type == CODA_INST_DECODER) {
@@ -2462,6 +2463,15 @@ static void coda_decode_ctrls(struct coda_ctx *ctx)
ctx->mpeg4_level_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
}
+static const struct v4l2_ctrl_config coda_mb_err_cnt_ctrl_config = {
+ .id = V4L2_CID_CODA_MB_ERR_CNT,
+ .name = "Macroblocks Error Count",
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .min = 0,
+ .max = 0x7fffffff,
+ .step = 1,
+};
+
static int coda_ctrls_setup(struct coda_ctx *ctx)
{
v4l2_ctrl_handler_init(&ctx->ctrls, 2);
@@ -2484,6 +2494,12 @@ static int coda_ctrls_setup(struct coda_ctx *ctx)
1, 1, 1, 1);
if (ctx->cvd->src_formats[0] == V4L2_PIX_FMT_H264)
coda_decode_ctrls(ctx);
+
+ ctx->mb_err_cnt_ctrl = v4l2_ctrl_new_custom(&ctx->ctrls,
+ &coda_mb_err_cnt_ctrl_config,
+ NULL);
+ if (ctx->mb_err_cnt_ctrl)
+ ctx->mb_err_cnt_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
}
if (ctx->ctrls.error) {
@@ -2851,17 +2867,17 @@ err_clk_per:
static int coda_register_device(struct coda_dev *dev, int i)
{
struct video_device *vfd = &dev->vfd[i];
- enum coda_inst_type type;
+ const char *name;
int ret;
if (i >= dev->devtype->num_vdevs)
return -EINVAL;
- type = dev->devtype->vdevs[i]->type;
+ name = dev->devtype->vdevs[i]->name;
strscpy(vfd->name, dev->devtype->vdevs[i]->name, sizeof(vfd->name));
vfd->fops = &coda_fops;
vfd->ioctl_ops = &coda_ioctl_ops;
- vfd->release = video_device_release_empty,
+ vfd->release = video_device_release_empty;
vfd->lock = &dev->dev_mutex;
vfd->v4l2_dev = &dev->v4l2_dev;
vfd->vfl_dir = VFL_DIR_M2M;
@@ -2876,8 +2892,7 @@ static int coda_register_device(struct coda_dev *dev, int i)
ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
if (!ret)
v4l2_info(&dev->v4l2_dev, "%s registered as %s\n",
- type == CODA_INST_ENCODER ? "encoder" : "decoder",
- video_device_node_name(vfd));
+ name, video_device_node_name(vfd));
return ret;
}
@@ -3086,13 +3101,6 @@ static const struct coda_devtype coda_devdata[] = {
},
};
-static const struct platform_device_id coda_platform_ids[] = {
- { .name = "coda-imx27", .driver_data = CODA_IMX27 },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(platform, coda_platform_ids);
-
-#ifdef CONFIG_OF
static const struct of_device_id coda_dt_ids[] = {
{ .compatible = "fsl,imx27-vpu", .data = &coda_devdata[CODA_IMX27] },
{ .compatible = "fsl,imx51-vpu", .data = &coda_devdata[CODA_IMX51] },
@@ -3102,14 +3110,9 @@ static const struct of_device_id coda_dt_ids[] = {
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, coda_dt_ids);
-#endif
static int coda_probe(struct platform_device *pdev)
{
- const struct of_device_id *of_id =
- of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
- const struct platform_device_id *pdev_id;
- struct coda_platform_data *pdata = pdev->dev.platform_data;
struct device_node *np = pdev->dev.of_node;
struct gen_pool *pool;
struct coda_dev *dev;
@@ -3119,14 +3122,7 @@ static int coda_probe(struct platform_device *pdev)
if (!dev)
return -ENOMEM;
- pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
-
- if (of_id)
- dev->devtype = of_id->data;
- else if (pdev_id)
- dev->devtype = &coda_devdata[pdev_id->driver_data];
- else
- return -EINVAL;
+ dev->devtype = of_device_get_match_data(&pdev->dev);
dev->dev = &pdev->dev;
dev->clk_per = devm_clk_get(&pdev->dev, "per");
@@ -3154,7 +3150,7 @@ static int coda_probe(struct platform_device *pdev)
return irq;
ret = devm_request_irq(&pdev->dev, irq, coda_irq_handler, 0,
- dev_name(&pdev->dev), dev);
+ CODA_NAME "-video", dev);
if (ret < 0) {
dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
return ret;
@@ -3168,7 +3164,7 @@ static int coda_probe(struct platform_device *pdev)
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
coda9_jpeg_irq_handler,
- IRQF_ONESHOT, CODA_NAME " jpeg",
+ IRQF_ONESHOT, CODA_NAME "-jpeg",
dev);
if (ret < 0) {
dev_err(&pdev->dev, "failed to request jpeg irq\n");
@@ -3184,10 +3180,8 @@ static int coda_probe(struct platform_device *pdev)
return ret;
}
- /* Get IRAM pool from device tree or platform data */
+ /* Get IRAM pool from device tree */
pool = of_gen_pool_get(np, "iram", 0);
- if (!pool && pdata)
- pool = gen_pool_get(pdata->iram_dev, NULL);
if (!pool) {
dev_err(&pdev->dev, "iram pool not available\n");
return -ENOMEM;
@@ -3203,6 +3197,7 @@ static int coda_probe(struct platform_device *pdev)
if (ret)
return ret;
+ ratelimit_default_init(&dev->mb_err_rs);
mutex_init(&dev->dev_mutex);
mutex_init(&dev->coda_mutex);
ida_init(&dev->ida);
@@ -3325,7 +3320,6 @@ static struct platform_driver coda_driver = {
.of_match_table = of_match_ptr(coda_dt_ids),
.pm = &coda_pm_ops,
},
- .id_table = coda_platform_ids,
};
module_platform_driver(coda_driver);
diff --git a/drivers/media/platform/coda/coda.h b/drivers/media/platform/coda/coda.h
index b81f3aca9209..dcf35641c603 100644
--- a/drivers/media/platform/coda/coda.h
+++ b/drivers/media/platform/coda/coda.h
@@ -17,6 +17,7 @@
#include <linux/mutex.h>
#include <linux/kfifo.h>
#include <linux/videodev2.h>
+#include <linux/ratelimit.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
@@ -28,6 +29,13 @@
#define CODA_MAX_FRAMEBUFFERS 19
#define FMO_SLICE_SAVE_BUF_SIZE (32)
+/*
+ * This control allows applications to read the per-stream
+ * (i.e. per-context) Macroblocks Error Count. This value
+ * is CODA specific.
+ */
+#define V4L2_CID_CODA_MB_ERR_CNT (V4L2_CID_USER_CODA_BASE + 0)
+
enum {
V4L2_M2M_SRC = 0,
V4L2_M2M_DST = 1,
@@ -92,6 +100,7 @@ struct coda_dev {
struct v4l2_m2m_dev *m2m_dev;
struct ida ida;
struct dentry *debugfs_root;
+ struct ratelimit_state mb_err_rs;
};
struct coda_codec {
@@ -242,6 +251,7 @@ struct coda_ctx {
struct v4l2_ctrl *mpeg2_level_ctrl;
struct v4l2_ctrl *mpeg4_profile_ctrl;
struct v4l2_ctrl *mpeg4_level_ctrl;
+ struct v4l2_ctrl *mb_err_cnt_ctrl;
struct v4l2_fh fh;
int gopcounter;
int runcounter;
@@ -259,6 +269,7 @@ struct coda_ctx {
struct list_head buffer_meta_list;
spinlock_t buffer_meta_lock;
int num_metas;
+ unsigned int first_frame_sequence;
struct coda_aux_buf workbuf;
int num_internal_frames;
int idx;
diff --git a/drivers/media/platform/davinci/isif.c b/drivers/media/platform/davinci/isif.c
index c98edb67cfb2..c53cecd072b1 100644
--- a/drivers/media/platform/davinci/isif.c
+++ b/drivers/media/platform/davinci/isif.c
@@ -1075,10 +1075,14 @@ fail_base_iomap:
release_mem_region(res->start, resource_size(res));
i--;
fail_nobase_res:
- if (isif_cfg.base_addr)
+ if (isif_cfg.base_addr) {
iounmap(isif_cfg.base_addr);
- if (isif_cfg.linear_tbl0_addr)
+ isif_cfg.base_addr = NULL;
+ }
+ if (isif_cfg.linear_tbl0_addr) {
iounmap(isif_cfg.linear_tbl0_addr);
+ isif_cfg.linear_tbl0_addr = NULL;
+ }
while (i >= 0) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
@@ -1096,8 +1100,11 @@ static int isif_remove(struct platform_device *pdev)
int i = 0;
iounmap(isif_cfg.base_addr);
+ isif_cfg.base_addr = NULL;
iounmap(isif_cfg.linear_tbl0_addr);
+ isif_cfg.linear_tbl0_addr = NULL;
iounmap(isif_cfg.linear_tbl1_addr);
+ isif_cfg.linear_tbl1_addr = NULL;
while (i < 3) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
if (res)
diff --git a/drivers/media/platform/exynos4-is/fimc-capture.c b/drivers/media/platform/exynos4-is/fimc-capture.c
index 6000a4e789ad..13c838d3f947 100644
--- a/drivers/media/platform/exynos4-is/fimc-capture.c
+++ b/drivers/media/platform/exynos4-is/fimc-capture.c
@@ -201,7 +201,7 @@ void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf)
if (!list_empty(&cap->pending_buf_q)) {
v_buf = fimc_pending_queue_pop(cap);
- fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
+ fimc_hw_set_output_addr(fimc, &v_buf->addr, cap->buf_index);
v_buf->index = cap->buf_index;
/* Move the buffer to the capture active queue */
@@ -410,7 +410,7 @@ static void buffer_queue(struct vb2_buffer *vb)
int min_bufs;
spin_lock_irqsave(&fimc->slock, flags);
- fimc_prepare_addr(ctx, &buf->vb.vb2_buf, &ctx->d_frame, &buf->paddr);
+ fimc_prepare_addr(ctx, &buf->vb.vb2_buf, &ctx->d_frame, &buf->addr);
if (!test_bit(ST_CAPT_SUSPENDED, &fimc->state) &&
!test_bit(ST_CAPT_STREAM, &fimc->state) &&
@@ -419,7 +419,7 @@ static void buffer_queue(struct vb2_buffer *vb)
int buf_id = (vid_cap->reqbufs_count == 1) ? -1 :
vid_cap->buf_index;
- fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id);
+ fimc_hw_set_output_addr(fimc, &buf->addr, buf_id);
buf->index = vid_cap->buf_index;
fimc_active_queue_add(vid_cap, buf);
diff --git a/drivers/media/platform/exynos4-is/fimc-core.c b/drivers/media/platform/exynos4-is/fimc-core.c
index 08d1f39a914c..bfdee771cef9 100644
--- a/drivers/media/platform/exynos4-is/fimc-core.c
+++ b/drivers/media/platform/exynos4-is/fimc-core.c
@@ -214,11 +214,13 @@ static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
while (sh--) {
u32 tmp = 1 << sh;
if (src >= tar * tmp) {
- *shift = sh, *ratio = tmp;
+ *shift = sh;
+ *ratio = tmp;
return 0;
}
}
- *shift = 0, *ratio = 1;
+ *shift = 0;
+ *ratio = 1;
return 0;
}
@@ -325,7 +327,7 @@ out:
/* The color format (colplanes, memplanes) must be already configured. */
int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
- struct fimc_frame *frame, struct fimc_addr *paddr)
+ struct fimc_frame *frame, struct fimc_addr *addr)
{
int ret = 0;
u32 pix_size;
@@ -338,42 +340,40 @@ int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
dbg("memplanes= %d, colplanes= %d, pix_size= %d",
frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
- paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
+ addr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
if (frame->fmt->memplanes == 1) {
switch (frame->fmt->colplanes) {
case 1:
- paddr->cb = 0;
- paddr->cr = 0;
+ addr->cb = 0;
+ addr->cr = 0;
break;
case 2:
/* decompose Y into Y/Cb */
- paddr->cb = (u32)(paddr->y + pix_size);
- paddr->cr = 0;
+ addr->cb = (u32)(addr->y + pix_size);
+ addr->cr = 0;
break;
case 3:
- paddr->cb = (u32)(paddr->y + pix_size);
+ addr->cb = (u32)(addr->y + pix_size);
/* decompose Y into Y/Cb/Cr */
if (FIMC_FMT_YCBCR420 == frame->fmt->color)
- paddr->cr = (u32)(paddr->cb
- + (pix_size >> 2));
+ addr->cr = (u32)(addr->cb + (pix_size >> 2));
else /* 422 */
- paddr->cr = (u32)(paddr->cb
- + (pix_size >> 1));
+ addr->cr = (u32)(addr->cb + (pix_size >> 1));
break;
default:
return -EINVAL;
}
} else if (!frame->fmt->mdataplanes) {
if (frame->fmt->memplanes >= 2)
- paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
+ addr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
if (frame->fmt->memplanes == 3)
- paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
+ addr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
}
- dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
- paddr->y, paddr->cb, paddr->cr, ret);
+ dbg("DMA ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
+ addr->y, addr->cb, addr->cr, ret);
return ret;
}
diff --git a/drivers/media/platform/exynos4-is/fimc-core.h b/drivers/media/platform/exynos4-is/fimc-core.h
index e4a56232907a..58b72a052cef 100644
--- a/drivers/media/platform/exynos4-is/fimc-core.h
+++ b/drivers/media/platform/exynos4-is/fimc-core.h
@@ -202,10 +202,10 @@ struct fimc_scaler {
};
/**
- * struct fimc_addr - the FIMC physical address set for DMA
- * @y: luminance plane physical address
- * @cb: Cb plane physical address
- * @cr: Cr plane physical address
+ * struct fimc_addr - the FIMC address set for DMA
+ * @y: luminance plane address
+ * @cb: Cb plane address
+ * @cr: Cr plane address
*/
struct fimc_addr {
u32 y;
@@ -217,13 +217,13 @@ struct fimc_addr {
* struct fimc_vid_buffer - the driver's video buffer
* @vb: v4l videobuf buffer
* @list: linked list structure for buffer queue
- * @paddr: precalculated physical address set
+ * @addr: precalculated DMA address set
* @index: buffer index for the output DMA engine
*/
struct fimc_vid_buffer {
struct vb2_v4l2_buffer vb;
struct list_head list;
- struct fimc_addr paddr;
+ struct fimc_addr addr;
int index;
};
@@ -239,7 +239,7 @@ struct fimc_vid_buffer {
* @height: image pixel weight
* @payload: image size in bytes (w x h x bpp)
* @bytesperline: bytesperline value for each plane
- * @paddr: image frame buffer physical addresses
+ * @addr: image frame buffer DMA addresses
* @dma_offset: DMA offset in bytes
* @fmt: fimc color format pointer
*/
@@ -254,7 +254,7 @@ struct fimc_frame {
u32 height;
unsigned int payload[VIDEO_MAX_PLANES];
unsigned int bytesperline[VIDEO_MAX_PLANES];
- struct fimc_addr paddr;
+ struct fimc_addr addr;
struct fimc_dma_offset dma_offset;
struct fimc_fmt *fmt;
u8 alpha;
@@ -626,7 +626,7 @@ int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
int fimc_set_scaler_info(struct fimc_ctx *ctx);
int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
- struct fimc_frame *frame, struct fimc_addr *paddr);
+ struct fimc_frame *frame, struct fimc_addr *addr);
void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
void fimc_set_yuv_order(struct fimc_ctx *ctx);
void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c
index 32ab01e89196..972d9601d236 100644
--- a/drivers/media/platform/exynos4-is/fimc-is.c
+++ b/drivers/media/platform/exynos4-is/fimc-is.c
@@ -268,7 +268,7 @@ int fimc_is_cpu_set_power(struct fimc_is *is, int on)
mcuctl_write(0, is, REG_WDT_ISP);
/* Cortex-A5 start address setting */
- mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
+ mcuctl_write(is->memory.addr, is, MCUCTL_REG_BBOAR);
/* Enable and start Cortex-A5 */
pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
@@ -335,26 +335,26 @@ static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
struct device *dev = &is->pdev->dev;
is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
- &is->memory.paddr, GFP_KERNEL);
+ &is->memory.addr, GFP_KERNEL);
if (is->memory.vaddr == NULL)
return -ENOMEM;
is->memory.size = FIMC_IS_CPU_MEM_SIZE;
- dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
+ dev_info(dev, "FIMC-IS CPU memory base: %pad\n", &is->memory.addr);
- if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
+ if (((u32)is->memory.addr) & FIMC_IS_FW_ADDR_MASK) {
dev_err(dev, "invalid firmware memory alignment: %#x\n",
- (u32)is->memory.paddr);
+ (u32)is->memory.addr);
dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
- is->memory.paddr);
+ is->memory.addr);
return -EIO;
}
is->is_p_region = (struct is_region *)(is->memory.vaddr +
FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
- is->is_dma_p_region = is->memory.paddr +
+ is->is_dma_p_region = is->memory.addr +
FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
@@ -370,7 +370,7 @@ static void fimc_is_free_cpu_memory(struct fimc_is *is)
return;
dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
- is->memory.paddr);
+ is->memory.addr);
}
static void fimc_is_load_firmware(const struct firmware *fw, void *context)
@@ -415,7 +415,7 @@ static void fimc_is_load_firmware(const struct firmware *fw, void *context)
dev_info(dev, "loaded firmware: %s, rev. %s\n",
is->fw.info, is->fw.version);
- dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr);
+ dev_dbg(dev, "FW size: %zu, DMA addr: %pad\n", fw->size, &is->memory.addr);
is->is_shared_region->chip_id = 0xe4412;
is->is_shared_region->chip_rev_no = 1;
@@ -698,7 +698,7 @@ int fimc_is_hw_initialize(struct fimc_is *is)
}
pr_debug("shared region: %pad, parameter region: %pad\n",
- &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
+ &is->memory.addr + FIMC_IS_SHARED_REGION_OFFSET,
&is->is_dma_p_region);
is->setfile.sub_index = 0;
diff --git a/drivers/media/platform/exynos4-is/fimc-is.h b/drivers/media/platform/exynos4-is/fimc-is.h
index 7ee96a058d40..ce30b007bc55 100644
--- a/drivers/media/platform/exynos4-is/fimc-is.h
+++ b/drivers/media/platform/exynos4-is/fimc-is.h
@@ -174,7 +174,7 @@ struct is_af_info {
struct fimc_is_firmware {
const struct firmware *f_w;
- dma_addr_t paddr;
+ dma_addr_t addr;
void *vaddr;
unsigned int size;
@@ -185,8 +185,8 @@ struct fimc_is_firmware {
};
struct fimc_is_memory {
- /* physical base address */
- dma_addr_t paddr;
+ /* DMA base address */
+ dma_addr_t addr;
/* virtual base address */
void *vaddr;
/* total length */
diff --git a/drivers/media/platform/exynos4-is/fimc-lite-reg.c b/drivers/media/platform/exynos4-is/fimc-lite-reg.c
index 85f765e0f4e1..57996b4104b4 100644
--- a/drivers/media/platform/exynos4-is/fimc-lite-reg.c
+++ b/drivers/media/platform/exynos4-is/fimc-lite-reg.c
@@ -272,9 +272,9 @@ void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf)
index = buf->index;
if (index == 0)
- writel(buf->paddr, dev->regs + FLITE_REG_CIOSA);
+ writel(buf->addr, dev->regs + FLITE_REG_CIOSA);
else
- writel(buf->paddr, dev->regs + FLITE_REG_CIOSAN(index - 1));
+ writel(buf->addr, dev->regs + FLITE_REG_CIOSAN(index - 1));
cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);
cfg |= BIT(index);
diff --git a/drivers/media/platform/exynos4-is/fimc-lite.c b/drivers/media/platform/exynos4-is/fimc-lite.c
index fdd0d369b192..fe20af3a7178 100644
--- a/drivers/media/platform/exynos4-is/fimc-lite.c
+++ b/drivers/media/platform/exynos4-is/fimc-lite.c
@@ -409,7 +409,7 @@ static void buffer_queue(struct vb2_buffer *vb)
unsigned long flags;
spin_lock_irqsave(&fimc->slock, flags);
- buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
+ buf->addr = vb2_dma_contig_plane_dma_addr(vb, 0);
buf->index = fimc->buf_index++;
if (fimc->buf_index >= fimc->reqbufs_count)
diff --git a/drivers/media/platform/exynos4-is/fimc-lite.h b/drivers/media/platform/exynos4-is/fimc-lite.h
index e6846c5fc9ac..e2d4d628b5aa 100644
--- a/drivers/media/platform/exynos4-is/fimc-lite.h
+++ b/drivers/media/platform/exynos4-is/fimc-lite.h
@@ -93,13 +93,13 @@ struct flite_frame {
* struct flite_buffer - video buffer structure
* @vb: vb2 buffer
* @list: list head for the buffers queue
- * @paddr: DMA buffer start address
+ * @addr: DMA buffer start address
* @index: DMA start address register's index
*/
struct flite_buffer {
struct vb2_v4l2_buffer vb;
struct list_head list;
- dma_addr_t paddr;
+ dma_addr_t addr;
unsigned short index;
};
diff --git a/drivers/media/platform/exynos4-is/fimc-m2m.c b/drivers/media/platform/exynos4-is/fimc-m2m.c
index 4acb179556c4..c9704a147e5c 100644
--- a/drivers/media/platform/exynos4-is/fimc-m2m.c
+++ b/drivers/media/platform/exynos4-is/fimc-m2m.c
@@ -115,12 +115,12 @@ static void fimc_device_run(void *priv)
}
src_vb = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
- ret = fimc_prepare_addr(ctx, &src_vb->vb2_buf, sf, &sf->paddr);
+ ret = fimc_prepare_addr(ctx, &src_vb->vb2_buf, sf, &sf->addr);
if (ret)
goto dma_unlock;
dst_vb = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
- ret = fimc_prepare_addr(ctx, &dst_vb->vb2_buf, df, &df->paddr);
+ ret = fimc_prepare_addr(ctx, &dst_vb->vb2_buf, df, &df->addr);
if (ret)
goto dma_unlock;
@@ -152,8 +152,8 @@ static void fimc_device_run(void *priv)
fimc_hw_set_rgb_alpha(ctx);
fimc_hw_set_output_path(ctx);
}
- fimc_hw_set_input_addr(fimc, &sf->paddr);
- fimc_hw_set_output_addr(fimc, &df->paddr, -1);
+ fimc_hw_set_input_addr(fimc, &sf->addr);
+ fimc_hw_set_output_addr(fimc, &df->addr, -1);
fimc_activate_capture(ctx);
ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP);
diff --git a/drivers/media/platform/exynos4-is/fimc-reg.c b/drivers/media/platform/exynos4-is/fimc-reg.c
index 8764999a5fd7..95165a2cc7d1 100644
--- a/drivers/media/platform/exynos4-is/fimc-reg.c
+++ b/drivers/media/platform/exynos4-is/fimc-reg.c
@@ -526,30 +526,30 @@ void fimc_hw_set_output_path(struct fimc_ctx *ctx)
writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
}
-void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
+void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *addr)
{
u32 cfg = readl(dev->regs + FIMC_REG_CIREAL_ISIZE);
cfg |= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
- writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0));
- writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0));
- writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0));
+ writel(addr->y, dev->regs + FIMC_REG_CIIYSA(0));
+ writel(addr->cb, dev->regs + FIMC_REG_CIICBSA(0));
+ writel(addr->cr, dev->regs + FIMC_REG_CIICRSA(0));
cfg &= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS;
writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE);
}
void fimc_hw_set_output_addr(struct fimc_dev *dev,
- struct fimc_addr *paddr, int index)
+ struct fimc_addr *addr, int index)
{
int i = (index == -1) ? 0 : index;
do {
- writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i));
- writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
- writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
+ writel(addr->y, dev->regs + FIMC_REG_CIOYSA(i));
+ writel(addr->cb, dev->regs + FIMC_REG_CIOCBSA(i));
+ writel(addr->cr, dev->regs + FIMC_REG_CIOCRSA(i));
dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
- i, paddr->y, paddr->cb, paddr->cr);
+ i, addr->y, addr->cb, addr->cr);
} while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
}
diff --git a/drivers/media/platform/exynos4-is/fimc-reg.h b/drivers/media/platform/exynos4-is/fimc-reg.h
index b81826d04936..d7a62465c14e 100644
--- a/drivers/media/platform/exynos4-is/fimc-reg.h
+++ b/drivers/media/platform/exynos4-is/fimc-reg.h
@@ -302,8 +302,8 @@ void fimc_hw_set_rgb_alpha(struct fimc_ctx *ctx);
void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
void fimc_hw_set_input_path(struct fimc_ctx *ctx);
void fimc_hw_set_output_path(struct fimc_ctx *ctx);
-void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
-void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
+void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *addr);
+void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *addr,
int index);
int fimc_hw_set_camera_source(struct fimc_dev *fimc,
struct fimc_source_info *cam);
diff --git a/drivers/media/platform/fsl-viu.c b/drivers/media/platform/fsl-viu.c
index 4f2a0f992905..1f1042d5c865 100644
--- a/drivers/media/platform/fsl-viu.c
+++ b/drivers/media/platform/fsl-viu.c
@@ -31,12 +31,6 @@
#define DRV_NAME "fsl_viu"
#define VIU_VERSION "0.5.1"
-/* Allow building this driver with COMPILE_TEST */
-#if !defined(CONFIG_PPC) && !defined(CONFIG_MICROBLAZE) && !defined(CONFIG_M68K)
-#define out_be32(v, a) iowrite32be(a, (void __iomem *)v)
-#define in_be32(a) ioread32be((void __iomem *)a)
-#endif
-
#define BUFFER_TIMEOUT msecs_to_jiffies(500) /* 0.5 seconds */
#define VIU_VID_MEM_LIMIT 4 /* Video memory limit, in Mb */
@@ -250,8 +244,8 @@ static void viu_start_dma(struct viu_dev *dev)
dev->field = 0;
/* Enable DMA operation */
- out_be32(&vr->status_cfg, SOFT_RST);
- out_be32(&vr->status_cfg, INT_FIELD_EN);
+ iowrite32be(SOFT_RST, &vr->status_cfg);
+ iowrite32be(INT_FIELD_EN, &vr->status_cfg);
}
static void viu_stop_dma(struct viu_dev *dev)
@@ -260,27 +254,27 @@ static void viu_stop_dma(struct viu_dev *dev)
int cnt = 100;
u32 status_cfg;
- out_be32(&vr->status_cfg, 0);
+ iowrite32be(0, &vr->status_cfg);
/* Clear pending interrupts */
- status_cfg = in_be32(&vr->status_cfg);
+ status_cfg = ioread32be(&vr->status_cfg);
if (status_cfg & 0x3f0000)
- out_be32(&vr->status_cfg, status_cfg & 0x3f0000);
+ iowrite32be(status_cfg & 0x3f0000, &vr->status_cfg);
if (status_cfg & DMA_ACT) {
do {
- status_cfg = in_be32(&vr->status_cfg);
+ status_cfg = ioread32be(&vr->status_cfg);
if (status_cfg & INT_DMA_END_STATUS)
break;
} while (cnt--);
if (cnt < 0) {
/* timed out, issue soft reset */
- out_be32(&vr->status_cfg, SOFT_RST);
- out_be32(&vr->status_cfg, 0);
+ iowrite32be(SOFT_RST, &vr->status_cfg);
+ iowrite32be(0, &vr->status_cfg);
} else {
/* clear DMA_END and other pending irqs */
- out_be32(&vr->status_cfg, status_cfg & 0x3f0000);
+ iowrite32be(status_cfg & 0x3f0000, &vr->status_cfg);
}
}
@@ -381,8 +375,6 @@ static void free_buffer(struct videobuf_queue *vq, struct viu_buf *buf)
struct videobuf_buffer *vb = &buf->vb;
void *vaddr = NULL;
- BUG_ON(in_interrupt());
-
videobuf_waiton(vq, &buf->vb, 0, 0);
if (vq->int_ops && vq->int_ops->vaddr)
@@ -436,9 +428,9 @@ inline int buffer_activate(struct viu_dev *dev, struct viu_buf *buf)
if (!V4L2_FIELD_HAS_BOTH(buf->vb.field))
reg_val.dma_inc = 0;
- out_be32(&vr->dma_inc, reg_val.dma_inc);
- out_be32(&vr->picture_count, reg_val.picture_count);
- out_be32(&vr->field_base_addr, reg_val.field_base_addr);
+ iowrite32be(reg_val.dma_inc, &vr->dma_inc);
+ iowrite32be(reg_val.picture_count, &vr->picture_count);
+ iowrite32be(reg_val.field_base_addr, &vr->field_base_addr);
mod_timer(&dev->vidq.timeout, jiffies + BUFFER_TIMEOUT);
return 0;
}
@@ -698,9 +690,9 @@ static int verify_preview(struct viu_dev *dev, struct v4l2_window *win)
inline void viu_activate_overlay(struct viu_reg __iomem *vr)
{
- out_be32(&vr->field_base_addr, reg_val.field_base_addr);
- out_be32(&vr->dma_inc, reg_val.dma_inc);
- out_be32(&vr->picture_count, reg_val.picture_count);
+ iowrite32be(reg_val.field_base_addr, &vr->field_base_addr);
+ iowrite32be(reg_val.dma_inc, &vr->dma_inc);
+ iowrite32be(reg_val.picture_count, &vr->picture_count);
}
static int viu_setup_preview(struct viu_dev *dev, struct viu_fh *fh)
@@ -978,14 +970,14 @@ inline void viu_activate_next_buf(struct viu_dev *dev,
inline void viu_default_settings(struct viu_reg __iomem *vr)
{
- out_be32(&vr->luminance, 0x9512A254);
- out_be32(&vr->chroma_r, 0x03310000);
- out_be32(&vr->chroma_g, 0x06600F38);
- out_be32(&vr->chroma_b, 0x00000409);
- out_be32(&vr->alpha, 0x000000ff);
- out_be32(&vr->req_alarm, 0x00000090);
+ iowrite32be(0x9512A254, &vr->luminance);
+ iowrite32be(0x03310000, &vr->chroma_r);
+ iowrite32be(0x06600F38, &vr->chroma_g);
+ iowrite32be(0x00000409, &vr->chroma_b);
+ iowrite32be(0x000000ff, &vr->alpha);
+ iowrite32be(0x00000090, &vr->req_alarm);
dprintk(1, "status reg: 0x%08x, field base: 0x%08x\n",
- in_be32(&vr->status_cfg), in_be32(&vr->field_base_addr));
+ ioread32be(&vr->status_cfg), ioread32be(&vr->field_base_addr));
}
static void viu_overlay_intr(struct viu_dev *dev, u32 status)
@@ -1003,17 +995,15 @@ static void viu_overlay_intr(struct viu_dev *dev, u32 status)
if (status & FIELD_NO)
addr += reg_val.dma_inc;
- out_be32(&vr->field_base_addr, addr);
- out_be32(&vr->dma_inc, reg_val.dma_inc);
- out_be32(&vr->status_cfg,
- (status & 0xffc0ffff) |
+ iowrite32be(addr, &vr->field_base_addr);
+ iowrite32be(reg_val.dma_inc, &vr->dma_inc);
+ iowrite32be((status & 0xffc0ffff) |
(status & INT_ALL_STATUS) |
- reg_val.status_cfg);
+ reg_val.status_cfg, &vr->status_cfg);
} else if (status & INT_VSYNC_STATUS) {
- out_be32(&vr->status_cfg,
- (status & 0xffc0ffff) |
+ iowrite32be((status & 0xffc0ffff) |
(status & INT_ALL_STATUS) |
- reg_val.status_cfg);
+ reg_val.status_cfg, &vr->status_cfg);
}
}
}
@@ -1059,12 +1049,11 @@ static void viu_capture_intr(struct viu_dev *dev, u32 status)
dprintk(1, "field 1, 0x%lx, dev field %d\n",
(unsigned long)addr, dev->field);
}
- out_be32(&vr->field_base_addr, addr);
- out_be32(&vr->dma_inc, reg_val.dma_inc);
- out_be32(&vr->status_cfg,
- (status & 0xffc0ffff) |
+ iowrite32be(addr, &vr->field_base_addr);
+ iowrite32be(reg_val.dma_inc, &vr->dma_inc);
+ iowrite32be((status & 0xffc0ffff) |
(status & INT_ALL_STATUS) |
- reg_val.status_cfg);
+ reg_val.status_cfg, &vr->status_cfg);
return;
}
}
@@ -1076,7 +1065,7 @@ static void viu_capture_intr(struct viu_dev *dev, u32 status)
dprintk(1, "viu/0: [%p/%d] 0x%lx/0x%lx: dma complete\n",
buf, buf->vb.i,
(unsigned long)videobuf_to_dma_contig(&buf->vb),
- (unsigned long)in_be32(&vr->field_base_addr));
+ (unsigned long)ioread32be(&vr->field_base_addr));
if (waitqueue_active(&buf->vb.done)) {
list_del(&buf->vb.queue);
@@ -1097,7 +1086,7 @@ static irqreturn_t viu_intr(int irq, void *dev_id)
u32 status;
u32 error;
- status = in_be32(&vr->status_cfg);
+ status = ioread32be(&vr->status_cfg);
if (status & INT_ERROR_STATUS) {
dev->irqs.error_irq++;
@@ -1106,8 +1095,8 @@ static irqreturn_t viu_intr(int irq, void *dev_id)
dprintk(1, "Err: error(%d), times:%d!\n",
error >> 4, dev->irqs.error_irq);
/* Clear interrupt error bit and error flags */
- out_be32(&vr->status_cfg,
- (status & 0xffc0ffff) | INT_ERROR_STATUS);
+ iowrite32be((status & 0xffc0ffff) | INT_ERROR_STATUS,
+ &vr->status_cfg);
}
if (status & INT_DMA_END_STATUS) {
@@ -1136,9 +1125,9 @@ static irqreturn_t viu_intr(int irq, void *dev_id)
}
/* clear all pending irqs */
- status = in_be32(&vr->status_cfg);
- out_be32(&vr->status_cfg,
- (status & 0xffc0ffff) | (status & INT_ALL_STATUS));
+ status = ioread32be(&vr->status_cfg);
+ iowrite32be((status & 0xffc0ffff) | (status & INT_ALL_STATUS),
+ &vr->status_cfg);
if (dev->ovenable) {
viu_overlay_intr(dev, status);
@@ -1207,14 +1196,14 @@ static int viu_open(struct file *file)
viu_default_settings(vr);
- status_cfg = in_be32(&vr->status_cfg);
- out_be32(&vr->status_cfg,
- status_cfg & ~(INT_VSYNC_EN | INT_HSYNC_EN |
+ status_cfg = ioread32be(&vr->status_cfg);
+ iowrite32be(status_cfg & ~(INT_VSYNC_EN | INT_HSYNC_EN |
INT_FIELD_EN | INT_VSTART_EN |
- INT_DMA_END_EN | INT_ERROR_EN | INT_ECC_EN));
+ INT_DMA_END_EN | INT_ERROR_EN | INT_ECC_EN),
+ &vr->status_cfg);
- status_cfg = in_be32(&vr->status_cfg);
- out_be32(&vr->status_cfg, status_cfg | INT_ALL_STATUS);
+ status_cfg = ioread32be(&vr->status_cfg);
+ iowrite32be(status_cfg | INT_ALL_STATUS, &vr->status_cfg);
spin_lock_init(&fh->vbq_lock);
videobuf_queue_dma_contig_init(&fh->vb_vidq, &viu_video_qops,
@@ -1294,16 +1283,16 @@ static int viu_release(struct file *file)
static void viu_reset(struct viu_reg __iomem *reg)
{
- out_be32(&reg->status_cfg, 0);
- out_be32(&reg->luminance, 0x9512a254);
- out_be32(&reg->chroma_r, 0x03310000);
- out_be32(&reg->chroma_g, 0x06600f38);
- out_be32(&reg->chroma_b, 0x00000409);
- out_be32(&reg->field_base_addr, 0);
- out_be32(&reg->dma_inc, 0);
- out_be32(&reg->picture_count, 0x01e002d0);
- out_be32(&reg->req_alarm, 0x00000090);
- out_be32(&reg->alpha, 0x000000ff);
+ iowrite32be(0, &reg->status_cfg);
+ iowrite32be(0x9512a254, &reg->luminance);
+ iowrite32be(0x03310000, &reg->chroma_r);
+ iowrite32be(0x06600f38, &reg->chroma_g);
+ iowrite32be(0x00000409, &reg->chroma_b);
+ iowrite32be(0, &reg->field_base_addr);
+ iowrite32be(0, &reg->dma_inc);
+ iowrite32be(0x01e002d0, &reg->picture_count);
+ iowrite32be(0x00000090, &reg->req_alarm);
+ iowrite32be(0x000000ff, &reg->alpha);
}
static int viu_mmap(struct file *file, struct vm_area_struct *vma)
diff --git a/drivers/media/platform/marvell-ccic/mmp-driver.c b/drivers/media/platform/marvell-ccic/mmp-driver.c
index 63fce1b85d26..032fdddbbecc 100644
--- a/drivers/media/platform/marvell-ccic/mmp-driver.c
+++ b/drivers/media/platform/marvell-ccic/mmp-driver.c
@@ -307,8 +307,7 @@ static int mmpcam_platform_remove(struct platform_device *pdev)
* Suspend/resume support.
*/
-#ifdef CONFIG_PM
-static int mmpcam_runtime_resume(struct device *dev)
+static int __maybe_unused mmpcam_runtime_resume(struct device *dev)
{
struct mmp_camera *cam = dev_get_drvdata(dev);
struct mcam_camera *mcam = &cam->mcam;
@@ -322,7 +321,7 @@ static int mmpcam_runtime_resume(struct device *dev)
return 0;
}
-static int mmpcam_runtime_suspend(struct device *dev)
+static int __maybe_unused mmpcam_runtime_suspend(struct device *dev)
{
struct mmp_camera *cam = dev_get_drvdata(dev);
struct mcam_camera *mcam = &cam->mcam;
@@ -353,7 +352,6 @@ static int __maybe_unused mmpcam_resume(struct device *dev)
return mccic_resume(&cam->mcam);
return 0;
}
-#endif
static const struct dev_pm_ops mmpcam_pm_ops = {
SET_RUNTIME_PM_OPS(mmpcam_runtime_suspend, mmpcam_runtime_resume, NULL)
diff --git a/drivers/media/platform/meson/ge2d/Makefile b/drivers/media/platform/meson/ge2d/Makefile
new file mode 100644
index 000000000000..450586df27d7
--- /dev/null
+++ b/drivers/media/platform/meson/ge2d/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_VIDEO_MESON_GE2D) += ge2d.o
diff --git a/drivers/media/platform/meson/ge2d/ge2d-regs.h b/drivers/media/platform/meson/ge2d/ge2d-regs.h
new file mode 100644
index 000000000000..2a76dd4c0ccb
--- /dev/null
+++ b/drivers/media/platform/meson/ge2d/ge2d-regs.h
@@ -0,0 +1,360 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __GE2D_REGS__
+#define __GE2D_REGS__
+
+/* Registers starts at (GE2D_REG(0x8a0 * 4) */
+#define GE2D_REG(x) ((0x8a0 + (x)) * 4)
+
+#define GE2D_GEN_CTRL0 GE2D_REG(0x00)
+
+#define GE2D_DST_BYTEMASK_ONLY BIT(31)
+#define GE2D_DST_BITMASK_EN BIT(30)
+#define GE2D_SRC2_KEY_EN BIT(29)
+#define GE2D_SRC2_KEY_MODE BIT(28)
+#define GE2D_SRC1_KEY_EN BIT(27)
+#define GE2D_SRC1_KEY_MODE BIT(26)
+#define GE2D_DST1_8B_MODE_SEL GENMASK(25, 24)
+#define GE2D_DST_CLIP_MODE BIT(23)
+#define GE2D_SRC2_8B_MODE_SEL GENMASK(16, 15)
+#define GE2D_SRC2_FILL_MODE BIT(14)
+#define GE2D_SRC2_PIC_STRUCT GENMASK(13, 12)
+#define GE2D_SRC2_X_YC_RATIO BIT(11)
+#define GE2D_SRC1_8B_MODE_SEL GENMASK(6, 5)
+#define GE2D_SRC1_FILL_MODE BIT(4)
+#define GE2D_SRC1_LUT_EN BIT(3)
+#define GE2D_SRC1_PIC_STRUCT GENMASK(2, 1)
+
+#define GE2D_GEN_CTRL1 GE2D_REG(0x01)
+
+#define GE2D_SOFT_RST BIT(31)
+#define GE2D_DST_WRITE_RESP_CNT_RST BIT(30)
+#define GE2D_DST_WRITE_RESP_CNT_ADD_DIS BIT(29)
+#define GE2D_COLOR_CONVERSION_MODE1 BIT(26)
+#define GE2D_INTERRUPT_CTRL GENMASK(25, 24)
+#define GE2D_SRC2_BURST_SIZE_CTRL GENMASK(23, 22)
+#define GE2D_SRC1_BURST_SIZE_CTRL GENMASK(21, 16)
+#define GE2D_DST1_PIC_STRUCT GENMASK(15, 14)
+#define GE2D_SRC_RD_CTRL GENMASK(13, 12)
+#define GE2D_DST2_URGENT_EN BIT(11)
+#define GE2D_SRC1_URGENT_EN BIT(10)
+#define GE2D_SRC2_URGENT_EN BIT(9)
+#define GE2D_DST1_URGENT_EN BIT(8)
+#define GE2D_SRC1_GB_ALPHA GENMASK(7, 0)
+
+#define GE2D_GEN_CTRL2 GE2D_REG(0x02)
+
+#define GE2D_ALPHA_CONVERSION_MODE0 BIT(31)
+#define GE2D_COLOR_CONVERSION_MODE0 BIT(30)
+#define GE2D_SRC1_GB_ALPHA_EN BIT(29)
+#define GE2D_DST1_COLOR_ROUND_MODE BIT(28)
+#define GE2D_SRC2_COLOR_EXPAND_MODE BIT(27)
+#define GE2D_SRC2_ALPHA_EXPAND_MODE BIT(26)
+#define GE2D_SRC1_COLOR_EXPAND_MODE BIT(25)
+#define GE2D_SRC1_ALPHA_EXPAND_MODE BIT(24)
+#define GE2D_DST_LITTLE_ENDIAN BIT(23)
+#define GE2D_DST1_COLOR_MAP GENMASK(22, 19)
+#define GE2D_ALU_MULT_MODE BIT(18)
+#define GE2D_DST1_FORMAT GENMASK(17, 16)
+#define GE2D_SRC2_LITTLE_ENDIAN BIT(15)
+#define GE2D_SRC2_COLOR_MAP GENMASK(14, 11)
+#define GE2D_ALPHA_CONVERSION_MODE1 BIT(10)
+#define GE2D_SRC2_FORMAT GENMASK(9, 8)
+#define GE2D_SRC1_LITTLE_ENDIAN BIT(7)
+#define GE2D_SRC1_COLOR_MAP GENMASK(6, 3)
+#define GE2D_SRC1_DEEPCOLOR BIT(2)
+#define GE2D_SRC1_FORMAT GENMASK(1, 0)
+
+#define GE2D_FORMAT_8BIT 0
+#define GE2D_FORMAT_16BIT 1
+#define GE2D_FORMAT_24BIT 2
+#define GE2D_FORMAT_32BIT 3
+
+/* 16 bit */
+#define GE2D_COLOR_MAP_YUV422 0
+#define GE2D_COLOR_MAP_RGB655 1
+#define GE2D_COLOR_MAP_YUV655 1
+#define GE2D_COLOR_MAP_RGB844 2
+#define GE2D_COLOR_MAP_YUV844 2
+#define GE2D_COLOR_MAP_RGBA6442 3
+#define GE2D_COLOR_MAP_YUVA6442 3
+#define GE2D_COLOR_MAP_RGBA4444 4
+#define GE2D_COLOR_MAP_YUVA4444 4
+#define GE2D_COLOR_MAP_RGB565 5
+#define GE2D_COLOR_MAP_YUV565 5
+#define GE2D_COLOR_MAP_ARGB4444 6
+#define GE2D_COLOR_MAP_AYUV4444 6
+#define GE2D_COLOR_MAP_ARGB1555 7
+#define GE2D_COLOR_MAP_AYUV1555 7
+#define GE2D_COLOR_MAP_RGBA4642 8
+#define GE2D_COLOR_MAP_YUVA4642 8
+
+/* 24 bit */
+#define GE2D_COLOR_MAP_RGB888 0
+#define GE2D_COLOR_MAP_YUV444 0
+#define GE2D_COLOR_MAP_RGBA5658 1
+#define GE2D_COLOR_MAP_YUVA5658 1
+#define GE2D_COLOR_MAP_ARGB8565 2
+#define GE2D_COLOR_MAP_AYUV8565 2
+#define GE2D_COLOR_MAP_RGBA6666 3
+#define GE2D_COLOR_MAP_YUVA6666 3
+#define GE2D_COLOR_MAP_ARGB6666 4
+#define GE2D_COLOR_MAP_AYUV6666 4
+#define GE2D_COLOR_MAP_BGR888 5
+#define GE2D_COLOR_MAP_VUY888 5
+
+/* 32 bit */
+#define GE2D_COLOR_MAP_RGBA8888 0
+#define GE2D_COLOR_MAP_YUVA8888 0
+#define GE2D_COLOR_MAP_ARGB8888 1
+#define GE2D_COLOR_MAP_AYUV8888 1
+#define GE2D_COLOR_MAP_ABGR8888 2
+#define GE2D_COLOR_MAP_AVUY8888 2
+#define GE2D_COLOR_MAP_BGRA8888 3
+#define GE2D_COLOR_MAP_VUYA8888 3
+
+#define GE2D_CMD_CTRL GE2D_REG(0x03)
+
+#define GE2D_SRC2_FILL_COLOR_EN BIT(9)
+#define GE2D_SRC1_FILL_COLOR_EN BIT(8)
+#define GE2D_DST_XY_SWAP BIT(7)
+#define GE2D_DST_X_REV BIT(6)
+#define GE2D_DST_Y_REV BIT(5)
+#define GE2D_SRC2_X_REV BIT(4)
+#define GE2D_SRC2_Y_REV BIT(3)
+#define GE2D_SRC1_X_REV BIT(2)
+#define GE2D_SRC1_Y_REV BIT(1)
+#define GE2D_CBUS_CMD_WR BIT(0)
+
+#define GE2D_STATUS0 GE2D_REG(0x04)
+
+#define GE2D_DST_WRITE_RSP_CNT GENMASK(28, 17)
+#define GE2D_DP_STATUS GENMASK(16, 7)
+#define GE2D_R1CMD_RDY BIT(6)
+#define GE2D_R2CMD_RDY BIT(5)
+#define GE2D_PDPCMD_VALID BIT(4)
+#define GE2D_DPCMD_RDY BIT(3)
+#define GE2D_BUF_CMD_VALID BIT(2)
+#define GE2D_CURR_CMD_VALID BIT(1)
+#define GE2D_GE2D_BUSY BIT(0)
+
+#define GE2D_STATUS1 GE2D_REG(0x05)
+
+#define GE2D_WR_DST1_STATUS GENMASK(29, 16)
+#define GE2D_RD_SRC2_FIFO_EMPTY BIT(15)
+#define GE2D_RD_SRC2_FIFO_OVERFLOW BIT(14)
+#define GE2D_RD_SRC2_STATE_Y GENMASK(13, 12)
+#define GE2D_RD_SRC2_WIN_ERR BIT(11)
+#define GE2D_RD_SRC2_CMD_BUSY BIT(10)
+#define GE2D_RD_SRC1_FIFO_EMPTY BIT(9)
+#define GE2D_RD_SRC1_FIFO_OVERFLOW BIT(8)
+#define GE2D_RD_SRC1_STATE_CR GENMASK(7, 6)
+#define GE2D_RD_SRC1_STATE_CB GENMASK(5, 4)
+#define GE2D_RD_SRC1_STATE_Y GENMASK(3, 2)
+#define GE2D_RD_SRC1_WIN_ERR BIT(1)
+#define GE2D_RD_SRC1_CMD_BUSY BIT(0)
+
+#define GE2D_SRC1_DEF_COLOR GE2D_REG(0x06)
+
+#define GE2D_COLOR_R_Y GENMASK(31, 24)
+#define GE2D_COLOR_B_CB GENMASK(23, 16)
+#define GE2D_COLOR_B_CR GENMASK(15, 8)
+#define GE2D_COLOR_ALPHA GENMASK(7, 0)
+
+#define GE2D_SRC1_CLIPX_START_END GE2D_REG(0x07)
+
+#define GE2D_START_EXTRA BIT(31) /* For GE2D_SRC1_CLIPX/Y_START_END */
+#define GE2D_START_EXTRA0 BIT(30) /* For GE2D_SRC1_X/Y_START_END */
+#define GE2D_START GENMASK(28, 16)
+#define GE2D_END_EXTRA BIT(15) /* For GE2D_SRC1_CLIPX/Y_START_END */
+#define GE2D_END_EXTRA0 BIT(14) /* For GE2D_SRC1_X/Y_START_END */
+#define GE2D_END GENMASK(12, 0)
+
+#define GE2D_SRC1_CLIPY_START_END GE2D_REG(0x08)
+#define GE2D_SRC1_CANVAS GE2D_REG(0x09)
+
+#define GE2D_SRC1_CANVAS_ADDR GENMASK(31, 24)
+
+#define GE2D_SRC1_X_START_END GE2D_REG(0x0a)
+#define GE2D_SRC1_Y_START_END GE2D_REG(0x0b)
+#define GE2D_SRC1_LUT_ADDR GE2D_REG(0x0c)
+
+#define GE2D_LUT_READ BIT(8)
+#define GE2D_LUT_ADDR GENMASK(7, 0)
+
+#define GE2D_SRC1_LUT_DAT GE2D_REG(0x0d)
+#define GE2D_SRC1_FMT_CTRL GE2D_REG(0x0e)
+#define GE2D_SRC2_DEF_COLOR GE2D_REG(0x0f)
+#define GE2D_SRC2_CLIPX_START_END GE2D_REG(0x10)
+#define GE2D_SRC2_CLIPY_START_END GE2D_REG(0x11)
+#define GE2D_SRC2_X_START_END GE2D_REG(0x12)
+#define GE2D_SRC2_Y_START_END GE2D_REG(0x13)
+#define GE2D_DST_CLIPX_START_END GE2D_REG(0x14)
+#define GE2D_DST_CLIPY_START_END GE2D_REG(0x15)
+#define GE2D_DST_X_START_END GE2D_REG(0x16)
+#define GE2D_DST_Y_START_END GE2D_REG(0x17)
+#define GE2D_SRC2_DST_CANVAS GE2D_REG(0x18)
+
+#define GE2D_DST2_CANVAS_ADDR GENMASK(23, 16)
+#define GE2D_SRC2_CANVAS_ADDR GENMASK(15, 8)
+#define GE2D_DST1_CANVAS_ADDR GENMASK(7, 0)
+
+#define GE2D_VSC_START_PHASE_STEP GE2D_REG(0x19)
+#define GE2D_VSC_PHASE_SLOPE GE2D_REG(0x1a)
+#define GE2D_VSC_INI_CTRL GE2D_REG(0x1b)
+#define GE2D_HSC_START_PHASE_STEP GE2D_REG(0x1c)
+#define GE2D_HSC_PHASE_SLOPE GE2D_REG(0x1d)
+#define GE2D_HSC_INI_CTRL GE2D_REG(0x1e)
+#define GE2D_HSC_ADV_CTRL GE2D_REG(0x1f)
+#define GE2D_SC_MISC_CTRL GE2D_REG(0x20)
+#define GE2D_VSC_NRND_POINT GE2D_REG(0x21)
+#define GE2D_VSC_NRND_PHASE GE2D_REG(0x22)
+#define GE2D_HSC_NRND_POINT GE2D_REG(0x23)
+#define GE2D_HSC_NRND_PHASE GE2D_REG(0x24)
+#define GE2D_MATRIX_PRE_OFFSET GE2D_REG(0x25)
+#define GE2D_MATRIX_COEF00_01 GE2D_REG(0x26)
+#define GE2D_MATRIX_COEF02_10 GE2D_REG(0x27)
+#define GE2D_MATRIX_COEF11_12 GE2D_REG(0x28)
+#define GE2D_MATRIX_COEF20_21 GE2D_REG(0x29)
+#define GE2D_MATRIX_COEF22_CTRL GE2D_REG(0x2a)
+#define GE2D_MATRIX_OFFSET GE2D_REG(0x2b)
+#define GE2D_ALU_OP_CTRL GE2D_REG(0x2c)
+
+#define GE2D_SRC1_COLOR_MULT_ALPHA_SEL GENMASK(26, 25)
+#define GE2D_SRC2_COLOR_MULT_ALPHA_SEL BIT(24)
+#define GE2D_ALU_BLEND_MODE GENMASK(22, 20)
+
+#define OPERATION_ADD 0 /* Cd = Cs*Fs+Cd*Fd */
+#define OPERATION_SUB 1 /* Cd = Cs*Fs-Cd*Fd */
+#define OPERATION_REVERSE_SUB 2 /* Cd = Cd*Fd-Cs*Fs */
+#define OPERATION_MIN 3 /* Cd = Min(Cd*Fd,Cs*Fs) */
+#define OPERATION_MAX 4 /* Cd = Max(Cd*Fd,Cs*Fs) */
+#define OPERATION_LOGIC 5
+
+#define GE2D_ALU_SRC_COLOR_BLEND_FACTOR GENMASK(19, 16)
+#define GE2D_ALU_DST_COLOR_BLEND_FACTOR GENMASK(15, 12)
+
+#define COLOR_FACTOR_ZERO 0
+#define COLOR_FACTOR_ONE 1
+#define COLOR_FACTOR_SRC_COLOR 2
+#define COLOR_FACTOR_ONE_MINUS_SRC_COLOR 3
+#define COLOR_FACTOR_DST_COLOR 4
+#define COLOR_FACTOR_ONE_MINUS_DST_COLOR 5
+#define COLOR_FACTOR_SRC_ALPHA 6
+#define COLOR_FACTOR_ONE_MINUS_SRC_ALPHA 7
+#define COLOR_FACTOR_DST_ALPHA 8
+#define COLOR_FACTOR_ONE_MINUS_DST_ALPHA 9
+#define COLOR_FACTOR_CONST_COLOR 10
+#define COLOR_FACTOR_ONE_MINUS_CONST_COLOR 11
+#define COLOR_FACTOR_CONST_ALPHA 12
+#define COLOR_FACTOR_ONE_MINUS_CONST_ALPHA 13
+#define COLOR_FACTOR_SRC_ALPHA_SATURATE 14
+
+#define GE2D_ALU_OPERATION_LOGIC GENMASK(15, 12)
+
+#define LOGIC_OPERATION_CLEAR 0
+#define LOGIC_OPERATION_COPY 1
+#define LOGIC_OPERATION_NOOP 2
+#define LOGIC_OPERATION_SET 3
+#define LOGIC_OPERATION_COPY_INVERT 4
+#define LOGIC_OPERATION_INVERT 5
+#define LOGIC_OPERATION_AND_REVERSE 6
+#define LOGIC_OPERATION_OR_REVERSE 7
+#define LOGIC_OPERATION_AND 8
+#define LOGIC_OPERATION_OR 9
+#define LOGIC_OPERATION_NAND 10
+#define LOGIC_OPERATION_NOR 11
+#define LOGIC_OPERATION_XOR 12
+#define LOGIC_OPERATION_EQUIV 13
+#define LOGIC_OPERATION_AND_INVERT 14
+#define LOGIC_OPERATION_OR_INVERT 15
+
+#define GE2D_ALU_ALPHA_BLEND_MODE GENMASK(10, 8)
+#define GE2D_ALU_SRC_ALPHA_BLEND_FACTOR GENMASK(7, 4)
+#define GE2D_ALU_DST_ALPHA_BLEND_FACTOR GENMASK(3, 0)
+
+#define ALPHA_FACTOR_ZERO 0
+#define ALPHA_FACTOR_ONE 1
+#define ALPHA_FACTOR_SRC_ALPHA 2
+#define ALPHA_FACTOR_ONE_MINUS_SRC_ALPHA 3
+#define ALPHA_FACTOR_DST_ALPHA 4
+#define ALPHA_FACTOR_ONE_MINUS_DST_ALPHA 5
+#define ALPHA_FACTOR_CONST_ALPHA 6
+#define ALPHA_FACTOR_ONE_MINUS_CONST_ALPHA 7
+
+#define GE2D_ALU_ALPHA_OPERATION_LOGIC GENMASK(3, 0)
+
+#define GE2D_ALU_COLOR_OP(__op, __src_factor, __dst_factor) \
+ (FIELD_PREP(GE2D_ALU_BLEND_MODE, __op) | \
+ FIELD_PREP(GE2D_ALU_SRC_COLOR_BLEND_FACTOR, __src_factor) | \
+ FIELD_PREP(GE2D_ALU_DST_COLOR_BLEND_FACTOR, __dst_factor))
+
+#define GE2D_ALU_DO_COLOR_OPERATION_LOGIC(__op, __src_factor) \
+ GE2D_ALU_COLOR_OP(OPERATION_LOGIC, __src_factor, __op)
+
+#define GE2D_ALU_ALPHA_OP(__op, __src_factor, __dst_factor) \
+ (FIELD_PREP(GE2D_ALU_ALPHA_BLEND_MODE, __op) | \
+ FIELD_PREP(GE2D_ALU_SRC_ALPHA_BLEND_FACTOR, __src_factor) | \
+ FIELD_PREP(GE2D_ALU_DST_ALPHA_BLEND_FACTOR, __dst_factor))
+
+#define GE2D_ALU_DO_ALPHA_OPERATION_LOGIC(__op, __src_factor) \
+ GE2D_ALU_ALPHA_OP(OPERATION_LOGIC, __src_factor, __op)
+
+#define GE2D_ALU_CONST_COLOR GE2D_REG(0x2d)
+#define GE2D_SRC1_KEY GE2D_REG(0x2e)
+#define GE2D_SRC1_KEY_MASK GE2D_REG(0x2f)
+#define GE2D_SRC2_KEY GE2D_REG(0x30)
+#define GE2D_SRC2_KEY_MASK GE2D_REG(0x31)
+#define GE2D_DST_BITMASK GE2D_REG(0x32)
+#define GE2D_DP_ONOFF_CTRL GE2D_REG(0x33)
+#define GE2D_SCALE_COEF_IDX GE2D_REG(0x34)
+#define GE2D_SCALE_COEF GE2D_REG(0x35)
+#define GE2D_SRC_OUTSIDE_ALPHA GE2D_REG(0x36)
+#define GE2D_ANTIFLICK_CTRL0 GE2D_REG(0x38)
+#define GE2D_ANTIFLICK_CTRL1 GE2D_REG(0x39)
+#define GE2D_ANTIFLICK_COLOR_FILT0 GE2D_REG(0x3a)
+#define GE2D_ANTIFLICK_COLOR_FILT1 GE2D_REG(0x3b)
+#define GE2D_ANTIFLICK_COLOR_FILT2 GE2D_REG(0x3c)
+#define GE2D_ANTIFLICK_COLOR_FILT3 GE2D_REG(0x3d)
+#define GE2D_ANTIFLICK_ALPHA_FILT0 GE2D_REG(0x3e)
+#define GE2D_ANTIFLICK_ALPHA_FILT1 GE2D_REG(0x3f)
+#define GE2D_ANTIFLICK_ALPHA_FILT2 GE2D_REG(0x40)
+#define GE2D_ANTIFLICK_ALPHA_FILT3 GE2D_REG(0x41)
+#define GE2D_SRC1_RANGE_MAP_Y_CTRL GE2D_REG(0x43)
+#define GE2D_SRC1_RANGE_MAP_CB_CTRL GE2D_REG(0x44)
+#define GE2D_SRC1_RANGE_MAP_CR_CTRL GE2D_REG(0x45)
+#define GE2D_ARB_BURST_NUM GE2D_REG(0x46)
+#define GE2D_TID_TOKEN GE2D_REG(0x47)
+#define GE2D_GEN_CTRL3 GE2D_REG(0x48)
+
+#define GE2D_DST2_BYTEMASK_VAL GENMASK(31, 28)
+#define GE2D_DST2_PIC_STRUCT GENMASK(27, 26)
+#define GE2D_DST2_8B_MODE_SEL GENMASK(25, 24)
+#define GE2D_DST2_COLOR_MAP GENMASK(22, 19)
+#define GE2D_DST2_FORMAT GENMASK(17, 16)
+#define GE2D_DST2_COLOR_ROUND_MODE BIT(14)
+#define GE2D_DST2_X_DISCARD_MODE GENMASK(13, 12)
+#define GE2D_DST2_Y_DISCARD_MODE GENMASK(11, 10)
+#define GE2D_DST2_ENABLE BIT(8)
+#define GE2D_DST1_X_DISCARD_MODE GENMASK(5, 4)
+#define GE2D_DST1_Y_DISCARD_MODE GENMASK(3, 2)
+#define GE2D_DST1_ENABLE BIT(0)
+
+#define GE2D_STATUS2 GE2D_REG(0x49)
+#define GE2D_GEN_CTRL4 GE2D_REG(0x4a)
+#define GE2D_DST1_BADDR_CTRL GE2D_REG(0x51)
+#define GE2D_DST1_STRIDE_CTRL GE2D_REG(0x52)
+
+#define GE2D_STRIDE_SIZE GENMASK(19, 0)
+
+#define GE2D_SRC1_BADDR_CTRL GE2D_REG(0x53)
+#define GE2D_SRC1_STRIDE_CTRL GE2D_REG(0x54)
+#define GE2D_SRC2_BADDR_CTRL GE2D_REG(0x55)
+#define GE2D_SRC2_STRIDE_CTRL GE2D_REG(0x56)
+
+#endif /* __GE2D_REGS__ */
diff --git a/drivers/media/platform/meson/ge2d/ge2d.c b/drivers/media/platform/meson/ge2d/ge2d.c
new file mode 100644
index 000000000000..f526501bd473
--- /dev/null
+++ b/drivers/media/platform/meson/ge2d/ge2d.c
@@ -0,0 +1,1067 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/bitfield.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/reset.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/regmap.h>
+
+#include <linux/platform_device.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-ctrls.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "ge2d-regs.h"
+
+#define GE2D_NAME "meson-ge2d"
+
+#define DEFAULT_WIDTH 128
+#define DEFAULT_HEIGHT 128
+#define DEFAULT_STRIDE 512
+
+#define MAX_WIDTH 8191
+#define MAX_HEIGHT 8191
+
+/*
+ * Missing features:
+ * - Scaling
+ * - Simple 1/2 vertical scaling
+ * - YUV input support
+ * - Source global alpha
+ * - Colorspace conversion
+ */
+
+struct ge2d_fmt {
+ u32 fourcc;
+ bool alpha;
+ bool le;
+ unsigned int depth;
+ unsigned int hw_fmt;
+ unsigned int hw_map;
+};
+
+struct ge2d_frame {
+ struct vb2_v4l2_buffer *buf;
+
+ /* Image Format */
+ struct v4l2_pix_format pix_fmt;
+
+ /* Crop */
+ struct v4l2_rect crop;
+
+ /* Image format */
+ const struct ge2d_fmt *fmt;
+};
+
+struct ge2d_ctx {
+ struct v4l2_fh fh;
+ struct meson_ge2d *ge2d;
+ struct ge2d_frame in;
+ struct ge2d_frame out;
+ struct v4l2_ctrl_handler ctrl_handler;
+
+ unsigned long sequence_out, sequence_cap;
+
+ /* Control values */
+ u32 hflip;
+ u32 vflip;
+ u32 xy_swap;
+};
+
+struct meson_ge2d {
+ struct v4l2_device v4l2_dev;
+ struct v4l2_m2m_dev *m2m_dev;
+ struct video_device *vfd;
+
+ struct device *dev;
+ struct regmap *map;
+ struct clk *clk;
+
+ /* vb2 queue lock */
+ struct mutex mutex;
+
+ struct ge2d_ctx *curr;
+};
+
+#define FMT(_fourcc, _alpha, _depth, _map) \
+{ \
+ .fourcc = _fourcc, \
+ .alpha = (_alpha), \
+ .depth = (_depth), \
+ .hw_fmt = GE2D_FORMAT_ ## _depth ## BIT, \
+ .hw_map = GE2D_COLOR_MAP_ ## _map, \
+}
+
+/* TOFIX Handle the YUV input formats */
+static const struct ge2d_fmt formats[] = {
+ /* FOURCC Alpha HW FMT HW MAP */
+ FMT(V4L2_PIX_FMT_XRGB32, false, 32, BGRA8888),
+ FMT(V4L2_PIX_FMT_RGB32, true, 32, BGRA8888),
+ FMT(V4L2_PIX_FMT_ARGB32, true, 32, BGRA8888),
+ FMT(V4L2_PIX_FMT_RGBX32, false, 32, ABGR8888),
+ FMT(V4L2_PIX_FMT_RGBA32, true, 32, ABGR8888),
+ FMT(V4L2_PIX_FMT_BGRX32, false, 32, RGBA8888),
+ FMT(V4L2_PIX_FMT_BGRA32, true, 32, RGBA8888),
+ FMT(V4L2_PIX_FMT_BGR32, true, 32, ARGB8888),
+ FMT(V4L2_PIX_FMT_ABGR32, true, 32, ARGB8888),
+ FMT(V4L2_PIX_FMT_XBGR32, false, 32, ARGB8888),
+
+ FMT(V4L2_PIX_FMT_RGB24, false, 24, BGR888),
+ FMT(V4L2_PIX_FMT_BGR24, false, 24, RGB888),
+
+ FMT(V4L2_PIX_FMT_XRGB555X, false, 16, ARGB1555),
+ FMT(V4L2_PIX_FMT_ARGB555X, true, 16, ARGB1555),
+ FMT(V4L2_PIX_FMT_RGB565, false, 16, RGB565),
+ FMT(V4L2_PIX_FMT_RGBX444, false, 16, RGBA4444),
+ FMT(V4L2_PIX_FMT_RGBA444, true, 16, RGBA4444),
+ FMT(V4L2_PIX_FMT_XRGB444, false, 16, ARGB4444),
+ FMT(V4L2_PIX_FMT_ARGB444, true, 16, ARGB4444),
+};
+
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct ge2d_fmt *find_fmt(struct v4l2_format *f)
+{
+ unsigned int i;
+
+ for (i = 0; i < NUM_FORMATS; i++) {
+ if (formats[i].fourcc == f->fmt.pix.pixelformat)
+ return &formats[i];
+ }
+
+ /*
+ * TRY_FMT/S_FMT should never return an error when the requested format
+ * is not supported. Drivers should always return a valid format,
+ * preferably a format that is as widely supported by applications as
+ * possible.
+ */
+ return &formats[0];
+}
+
+static struct ge2d_frame *get_frame(struct ge2d_ctx *ctx,
+ enum v4l2_buf_type type)
+{
+ switch (type) {
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ return &ctx->in;
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ return &ctx->out;
+ default:
+ /* This should never happen, warn and return OUTPUT frame */
+ dev_warn(ctx->ge2d->dev, "%s: invalid buffer type\n", __func__);
+ return &ctx->in;
+ }
+}
+
+static void ge2d_hw_start(struct meson_ge2d *ge2d)
+{
+ struct ge2d_ctx *ctx = ge2d->curr;
+ u32 reg;
+
+ /* Reset */
+ regmap_update_bits(ge2d->map, GE2D_GEN_CTRL1,
+ GE2D_SOFT_RST, GE2D_SOFT_RST);
+ regmap_update_bits(ge2d->map, GE2D_GEN_CTRL1,
+ GE2D_SOFT_RST, 0);
+
+ usleep_range(100, 200);
+
+ /* Implement CANVAS for non-AXG */
+ regmap_write(ge2d->map, GE2D_SRC1_BADDR_CTRL,
+ (vb2_dma_contig_plane_dma_addr(&ctx->in.buf->vb2_buf, 0) + 7) >> 3);
+ regmap_write(ge2d->map, GE2D_SRC1_STRIDE_CTRL,
+ (ctx->in.pix_fmt.bytesperline + 7) >> 3);
+ regmap_write(ge2d->map, GE2D_SRC2_BADDR_CTRL,
+ (vb2_dma_contig_plane_dma_addr(&ctx->out.buf->vb2_buf, 0) + 7) >> 3);
+ regmap_write(ge2d->map, GE2D_SRC2_STRIDE_CTRL,
+ (ctx->out.pix_fmt.bytesperline + 7) >> 3);
+ regmap_write(ge2d->map, GE2D_DST1_BADDR_CTRL,
+ (vb2_dma_contig_plane_dma_addr(&ctx->out.buf->vb2_buf, 0) + 7) >> 3);
+ regmap_write(ge2d->map, GE2D_DST1_STRIDE_CTRL,
+ (ctx->out.pix_fmt.bytesperline + 7) >> 3);
+
+ regmap_write(ge2d->map, GE2D_GEN_CTRL0, 0);
+ regmap_write(ge2d->map, GE2D_GEN_CTRL1,
+ FIELD_PREP(GE2D_INTERRUPT_CTRL, 2) |
+ FIELD_PREP(GE2D_SRC2_BURST_SIZE_CTRL, 3) |
+ FIELD_PREP(GE2D_SRC1_BURST_SIZE_CTRL, 0x3f));
+
+ regmap_write(ge2d->map, GE2D_GEN_CTRL2,
+ GE2D_SRC1_LITTLE_ENDIAN |
+ GE2D_SRC2_LITTLE_ENDIAN |
+ GE2D_DST_LITTLE_ENDIAN |
+ FIELD_PREP(GE2D_DST1_COLOR_MAP, ctx->out.fmt->hw_map) |
+ FIELD_PREP(GE2D_DST1_FORMAT, ctx->out.fmt->hw_fmt) |
+ FIELD_PREP(GE2D_SRC2_COLOR_MAP, ctx->out.fmt->hw_map) |
+ FIELD_PREP(GE2D_SRC2_FORMAT, ctx->out.fmt->hw_fmt) |
+ FIELD_PREP(GE2D_SRC1_COLOR_MAP, ctx->in.fmt->hw_map) |
+ FIELD_PREP(GE2D_SRC1_FORMAT, ctx->in.fmt->hw_fmt));
+ regmap_write(ge2d->map, GE2D_GEN_CTRL3,
+ GE2D_DST1_ENABLE);
+
+ regmap_write(ge2d->map, GE2D_SRC1_CLIPY_START_END,
+ FIELD_PREP(GE2D_START, ctx->in.crop.top) |
+ FIELD_PREP(GE2D_END, ctx->in.crop.top + ctx->in.crop.height));
+ regmap_write(ge2d->map, GE2D_SRC1_CLIPX_START_END,
+ FIELD_PREP(GE2D_START, ctx->in.crop.left) |
+ FIELD_PREP(GE2D_END, ctx->in.crop.left + ctx->in.crop.width));
+ regmap_write(ge2d->map, GE2D_SRC2_CLIPY_START_END,
+ FIELD_PREP(GE2D_START, ctx->out.crop.top) |
+ FIELD_PREP(GE2D_END, ctx->out.crop.top + ctx->out.crop.height));
+ regmap_write(ge2d->map, GE2D_SRC2_CLIPX_START_END,
+ FIELD_PREP(GE2D_START, ctx->out.crop.left) |
+ FIELD_PREP(GE2D_END, ctx->out.crop.left + ctx->out.crop.width));
+ regmap_write(ge2d->map, GE2D_DST_CLIPY_START_END,
+ FIELD_PREP(GE2D_START, ctx->out.crop.top) |
+ FIELD_PREP(GE2D_END, ctx->out.crop.top + ctx->out.crop.height));
+ regmap_write(ge2d->map, GE2D_DST_CLIPX_START_END,
+ FIELD_PREP(GE2D_START, ctx->out.crop.left) |
+ FIELD_PREP(GE2D_END, ctx->out.crop.left + ctx->out.crop.width));
+
+ regmap_write(ge2d->map, GE2D_SRC1_Y_START_END,
+ FIELD_PREP(GE2D_END, ctx->in.pix_fmt.height));
+ regmap_write(ge2d->map, GE2D_SRC1_X_START_END,
+ FIELD_PREP(GE2D_END, ctx->in.pix_fmt.width));
+ regmap_write(ge2d->map, GE2D_SRC2_Y_START_END,
+ FIELD_PREP(GE2D_END, ctx->out.pix_fmt.height));
+ regmap_write(ge2d->map, GE2D_SRC2_X_START_END,
+ FIELD_PREP(GE2D_END, ctx->out.pix_fmt.width));
+ regmap_write(ge2d->map, GE2D_DST_Y_START_END,
+ FIELD_PREP(GE2D_END, ctx->out.pix_fmt.height));
+ regmap_write(ge2d->map, GE2D_DST_X_START_END,
+ FIELD_PREP(GE2D_END, ctx->out.pix_fmt.width));
+
+ /* Color, no blend, use source color */
+ reg = GE2D_ALU_DO_COLOR_OPERATION_LOGIC(LOGIC_OPERATION_COPY,
+ COLOR_FACTOR_SRC_COLOR);
+
+ if (ctx->in.fmt->alpha && ctx->out.fmt->alpha)
+ /* Take source alpha */
+ reg |= GE2D_ALU_DO_ALPHA_OPERATION_LOGIC(LOGIC_OPERATION_COPY,
+ COLOR_FACTOR_SRC_ALPHA);
+ else if (!ctx->out.fmt->alpha)
+ /* Set alpha to 0 */
+ reg |= GE2D_ALU_DO_ALPHA_OPERATION_LOGIC(LOGIC_OPERATION_SET,
+ COLOR_FACTOR_ZERO);
+ else
+ /* Keep original alpha */
+ reg |= GE2D_ALU_DO_ALPHA_OPERATION_LOGIC(LOGIC_OPERATION_COPY,
+ COLOR_FACTOR_DST_ALPHA);
+
+ regmap_write(ge2d->map, GE2D_ALU_OP_CTRL, reg);
+
+ /* Start */
+ regmap_write(ge2d->map, GE2D_CMD_CTRL,
+ (ctx->xy_swap ? GE2D_DST_XY_SWAP : 0) |
+ (ctx->hflip ? GE2D_SRC1_Y_REV : 0) |
+ (ctx->vflip ? GE2D_SRC1_X_REV : 0) |
+ GE2D_CBUS_CMD_WR);
+}
+
+static void device_run(void *priv)
+{
+ struct ge2d_ctx *ctx = priv;
+ struct meson_ge2d *ge2d = ctx->ge2d;
+
+ ge2d->curr = ctx;
+
+ ctx->in.buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+ ctx->out.buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
+
+ ge2d_hw_start(ge2d);
+}
+
+static irqreturn_t ge2d_isr(int irq, void *priv)
+{
+ struct meson_ge2d *ge2d = priv;
+ u32 intr;
+
+ regmap_read(ge2d->map, GE2D_STATUS0, &intr);
+
+ if (!(intr & GE2D_GE2D_BUSY)) {
+ struct vb2_v4l2_buffer *src, *dst;
+ struct ge2d_ctx *ctx = ge2d->curr;
+
+ ge2d->curr = NULL;
+
+ src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+ dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+ src->sequence = ctx->sequence_out++;
+ dst->sequence = ctx->sequence_cap++;
+
+ dst->timecode = src->timecode;
+ dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
+ dst->flags = src->flags;
+
+ v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
+ v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
+ v4l2_m2m_job_finish(ge2d->m2m_dev, ctx->fh.m2m_ctx);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static const struct v4l2_m2m_ops ge2d_m2m_ops = {
+ .device_run = device_run,
+};
+
+static int ge2d_queue_setup(struct vb2_queue *vq,
+ unsigned int *nbuffers, unsigned int *nplanes,
+ unsigned int sizes[], struct device *alloc_devs[])
+{
+ struct ge2d_ctx *ctx = vb2_get_drv_priv(vq);
+ struct ge2d_frame *f = get_frame(ctx, vq->type);
+
+ if (*nplanes)
+ return sizes[0] < f->pix_fmt.sizeimage ? -EINVAL : 0;
+
+ sizes[0] = f->pix_fmt.sizeimage;
+ *nplanes = 1;
+
+ return 0;
+}
+
+static int ge2d_buf_prepare(struct vb2_buffer *vb)
+{
+ struct ge2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct ge2d_frame *f = get_frame(ctx, vb->vb2_queue->type);
+
+ vbuf->field = V4L2_FIELD_NONE;
+
+ vb2_set_plane_payload(vb, 0, f->pix_fmt.sizeimage);
+
+ return 0;
+}
+
+static void ge2d_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct ge2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
+}
+
+static int ge2d_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ struct ge2d_ctx *ctx = vb2_get_drv_priv(vq);
+
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ ctx->sequence_out = 0;
+ else
+ ctx->sequence_cap = 0;
+
+ return 0;
+}
+
+static void ge2d_stop_streaming(struct vb2_queue *vq)
+{
+ struct ge2d_ctx *ctx = vb2_get_drv_priv(vq);
+ struct vb2_v4l2_buffer *vbuf;
+
+ for (;;) {
+ if (V4L2_TYPE_IS_OUTPUT(vq->type))
+ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+ else
+ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+ if (!vbuf)
+ break;
+ v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
+ }
+}
+
+static const struct vb2_ops ge2d_qops = {
+ .queue_setup = ge2d_queue_setup,
+ .buf_prepare = ge2d_buf_prepare,
+ .buf_queue = ge2d_buf_queue,
+ .start_streaming = ge2d_start_streaming,
+ .stop_streaming = ge2d_stop_streaming,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+};
+
+static int
+queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
+{
+ struct ge2d_ctx *ctx = priv;
+ int ret;
+
+ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+ src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+ src_vq->drv_priv = ctx;
+ src_vq->ops = &ge2d_qops;
+ src_vq->mem_ops = &vb2_dma_contig_memops;
+ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ src_vq->lock = &ctx->ge2d->mutex;
+ src_vq->dev = ctx->ge2d->v4l2_dev.dev;
+
+ ret = vb2_queue_init(src_vq);
+ if (ret)
+ return ret;
+
+ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+ dst_vq->drv_priv = ctx;
+ dst_vq->ops = &ge2d_qops;
+ dst_vq->mem_ops = &vb2_dma_contig_memops;
+ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+ dst_vq->lock = &ctx->ge2d->mutex;
+ dst_vq->dev = ctx->ge2d->v4l2_dev.dev;
+
+ return vb2_queue_init(dst_vq);
+}
+
+static int
+vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
+{
+ strscpy(cap->driver, GE2D_NAME, sizeof(cap->driver));
+ strscpy(cap->card, GE2D_NAME, sizeof(cap->card));
+ strscpy(cap->bus_info, "platform:" GE2D_NAME, sizeof(cap->bus_info));
+
+ return 0;
+}
+
+static int vidioc_enum_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f)
+{
+ const struct ge2d_fmt *fmt;
+
+ if (f->index >= NUM_FORMATS)
+ return -EINVAL;
+
+ fmt = &formats[f->index];
+ f->pixelformat = fmt->fourcc;
+
+ return 0;
+}
+
+static int vidioc_g_selection(struct file *file, void *priv,
+ struct v4l2_selection *s)
+{
+ struct ge2d_ctx *ctx = priv;
+ struct ge2d_frame *f;
+ bool use_frame = false;
+
+ if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT &&
+ s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ f = get_frame(ctx, s->type);
+
+ switch (s->target) {
+ case V4L2_SEL_TGT_COMPOSE_DEFAULT:
+ case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ break;
+ case V4L2_SEL_TGT_CROP_DEFAULT:
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+ return -EINVAL;
+ break;
+ case V4L2_SEL_TGT_COMPOSE:
+ if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ use_frame = true;
+ break;
+ case V4L2_SEL_TGT_CROP:
+ if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+ return -EINVAL;
+ use_frame = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (use_frame) {
+ s->r = f->crop;
+ } else {
+ s->r.left = 0;
+ s->r.top = 0;
+ s->r.width = f->pix_fmt.width;
+ s->r.height = f->pix_fmt.height;
+ }
+
+ return 0;
+}
+
+static int vidioc_s_selection(struct file *file, void *priv,
+ struct v4l2_selection *s)
+{
+ struct ge2d_ctx *ctx = priv;
+ struct meson_ge2d *ge2d = ctx->ge2d;
+ struct ge2d_frame *f;
+ int ret = 0;
+
+ if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT &&
+ s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ f = get_frame(ctx, s->type);
+
+ switch (s->target) {
+ case V4L2_SEL_TGT_COMPOSE:
+ /*
+ * COMPOSE target is only valid for capture buffer type, return
+ * error for output buffer type
+ */
+ if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ break;
+ case V4L2_SEL_TGT_CROP:
+ /*
+ * CROP target is only valid for output buffer type, return
+ * error for capture buffer type
+ */
+ if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
+ return -EINVAL;
+ break;
+ /*
+ * bound and default crop/compose targets are invalid targets to
+ * try/set
+ */
+ default:
+ return -EINVAL;
+ }
+
+ if (s->r.top < 0 || s->r.left < 0) {
+ v4l2_err(&ge2d->v4l2_dev,
+ "doesn't support negative values for top & left.\n");
+ return -EINVAL;
+ }
+
+ if (s->r.left + s->r.width > f->pix_fmt.width ||
+ s->r.top + s->r.height > f->pix_fmt.height) {
+ v4l2_err(&ge2d->v4l2_dev, "unsupported rectangle value.\n");
+ return -EINVAL;
+ }
+
+ f->crop = s->r;
+
+ return ret;
+}
+
+static void vidioc_setup_cap_fmt(struct ge2d_ctx *ctx, struct v4l2_pix_format *f)
+{
+ struct ge2d_frame *frm_out = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
+
+ *f = frm_out->pix_fmt;
+
+ if (ctx->xy_swap) {
+ f->width = frm_out->pix_fmt.height;
+ f->height = frm_out->pix_fmt.width;
+ }
+}
+
+static int vidioc_try_fmt_cap(struct file *file, void *priv, struct v4l2_format *f)
+{
+ const struct ge2d_fmt *fmt = find_fmt(f);
+ struct ge2d_ctx *ctx = priv;
+ struct v4l2_pix_format fmt_cap;
+
+ vidioc_setup_cap_fmt(ctx, &fmt_cap);
+
+ fmt_cap.pixelformat = fmt->fourcc;
+
+ fmt_cap.bytesperline = max(f->fmt.pix.bytesperline,
+ ALIGN((fmt_cap.width * fmt->depth) >> 3, 8));
+
+ fmt_cap.sizeimage = max(f->fmt.pix.sizeimage,
+ fmt_cap.height * fmt_cap.bytesperline);
+
+ f->fmt.pix = fmt_cap;
+
+ return 0;
+}
+
+static int vidioc_s_fmt_cap(struct file *file, void *priv, struct v4l2_format *f)
+{
+ struct ge2d_ctx *ctx = priv;
+ struct meson_ge2d *ge2d = ctx->ge2d;
+ struct vb2_queue *vq;
+ struct ge2d_frame *frm;
+ int ret = 0;
+
+ /* Adjust all values accordingly to the hardware capabilities
+ * and chosen format.
+ */
+ ret = vidioc_try_fmt_cap(file, priv, f);
+ if (ret)
+ return ret;
+
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+ if (vb2_is_busy(vq)) {
+ v4l2_err(&ge2d->v4l2_dev, "queue (%d) bust\n", f->type);
+ return -EBUSY;
+ }
+
+ frm = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
+
+ frm->pix_fmt = f->fmt.pix;
+ frm->fmt = find_fmt(f);
+ f->fmt.pix.pixelformat = frm->fmt->fourcc;
+
+ /* Reset crop settings */
+ frm->crop.left = 0;
+ frm->crop.top = 0;
+ frm->crop.width = frm->pix_fmt.width;
+ frm->crop.height = frm->pix_fmt.height;
+
+ return 0;
+}
+
+static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+ struct ge2d_ctx *ctx = priv;
+ struct vb2_queue *vq;
+ struct ge2d_frame *frm;
+
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+ if (!vq)
+ return -EINVAL;
+
+ frm = get_frame(ctx, f->type);
+
+ f->fmt.pix = frm->pix_fmt;
+ f->fmt.pix.pixelformat = frm->fmt->fourcc;
+
+ return 0;
+}
+
+static int vidioc_try_fmt_out(struct file *file, void *priv, struct v4l2_format *f)
+{
+ const struct ge2d_fmt *fmt = find_fmt(f);
+
+ f->fmt.pix.field = V4L2_FIELD_NONE;
+ f->fmt.pix.pixelformat = fmt->fourcc;
+
+ if (f->fmt.pix.width > MAX_WIDTH)
+ f->fmt.pix.width = MAX_WIDTH;
+ if (f->fmt.pix.height > MAX_HEIGHT)
+ f->fmt.pix.height = MAX_HEIGHT;
+
+ f->fmt.pix.bytesperline = max(f->fmt.pix.bytesperline,
+ ALIGN((f->fmt.pix.width * fmt->depth) >> 3, 8));
+
+ f->fmt.pix.sizeimage = max(f->fmt.pix.sizeimage,
+ f->fmt.pix.height * f->fmt.pix.bytesperline);
+
+ return 0;
+}
+
+static int vidioc_s_fmt_out(struct file *file, void *priv, struct v4l2_format *f)
+{
+ struct ge2d_ctx *ctx = priv;
+ struct meson_ge2d *ge2d = ctx->ge2d;
+ struct vb2_queue *vq;
+ struct ge2d_frame *frm, *frm_cap;
+ int ret = 0;
+
+ /* Adjust all values accordingly to the hardware capabilities
+ * and chosen format.
+ */
+ ret = vidioc_try_fmt_out(file, priv, f);
+ if (ret)
+ return ret;
+
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+ if (vb2_is_busy(vq)) {
+ v4l2_err(&ge2d->v4l2_dev, "queue (%d) bust\n", f->type);
+ return -EBUSY;
+ }
+
+ frm = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
+ frm_cap = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
+
+ frm->pix_fmt = f->fmt.pix;
+ frm->fmt = find_fmt(f);
+ f->fmt.pix.pixelformat = frm->fmt->fourcc;
+
+ /* Reset crop settings */
+ frm->crop.left = 0;
+ frm->crop.top = 0;
+ frm->crop.width = frm->pix_fmt.width;
+ frm->crop.height = frm->pix_fmt.height;
+
+ /* Propagate settings to capture */
+ vidioc_setup_cap_fmt(ctx, &frm_cap->pix_fmt);
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops ge2d_ioctl_ops = {
+ .vidioc_querycap = vidioc_querycap,
+
+ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_cap,
+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_cap,
+
+ .vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
+ .vidioc_g_fmt_vid_out = vidioc_g_fmt,
+ .vidioc_try_fmt_vid_out = vidioc_try_fmt_out,
+ .vidioc_s_fmt_vid_out = vidioc_s_fmt_out,
+
+ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
+ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
+ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
+ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
+ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
+ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
+ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
+
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+
+ .vidioc_streamon = v4l2_m2m_ioctl_streamon,
+ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
+
+ .vidioc_g_selection = vidioc_g_selection,
+ .vidioc_s_selection = vidioc_s_selection,
+};
+
+static int ge2d_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ge2d_ctx *ctx = container_of(ctrl->handler, struct ge2d_ctx,
+ ctrl_handler);
+ struct v4l2_pix_format fmt;
+ struct vb2_queue *vq;
+
+ switch (ctrl->id) {
+ case V4L2_CID_HFLIP:
+ ctx->hflip = ctrl->val;
+ break;
+ case V4L2_CID_VFLIP:
+ ctx->vflip = ctrl->val;
+ break;
+ case V4L2_CID_ROTATE:
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
+ if (vb2_is_busy(vq))
+ return -EBUSY;
+
+ if (ctrl->val == 90) {
+ ctx->hflip = 0;
+ ctx->vflip = 0;
+ ctx->xy_swap = 1;
+ } else if (ctrl->val == 180) {
+ ctx->hflip = 1;
+ ctx->vflip = 1;
+ ctx->xy_swap = 0;
+ } else if (ctrl->val == 270) {
+ ctx->hflip = 1;
+ ctx->vflip = 1;
+ ctx->xy_swap = 1;
+ } else {
+ ctx->hflip = 0;
+ ctx->vflip = 0;
+ ctx->xy_swap = 0;
+ }
+
+ vidioc_setup_cap_fmt(ctx, &fmt);
+
+ /*
+ * If the rotation parameter changes the OUTPUT frames
+ * parameters, take them in account
+ */
+ if (fmt.width != ctx->out.pix_fmt.width ||
+ fmt.height != ctx->out.pix_fmt.width ||
+ fmt.bytesperline > ctx->out.pix_fmt.bytesperline ||
+ fmt.sizeimage > ctx->out.pix_fmt.sizeimage)
+ ctx->out.pix_fmt = fmt;
+
+ break;
+ }
+
+ return 0;
+}
+
+static const struct v4l2_ctrl_ops ge2d_ctrl_ops = {
+ .s_ctrl = ge2d_s_ctrl,
+};
+
+static int ge2d_setup_ctrls(struct ge2d_ctx *ctx)
+{
+ struct meson_ge2d *ge2d = ctx->ge2d;
+
+ v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
+
+ v4l2_ctrl_new_std(&ctx->ctrl_handler, &ge2d_ctrl_ops,
+ V4L2_CID_HFLIP, 0, 1, 1, 0);
+
+ v4l2_ctrl_new_std(&ctx->ctrl_handler, &ge2d_ctrl_ops,
+ V4L2_CID_VFLIP, 0, 1, 1, 0);
+
+ v4l2_ctrl_new_std(&ctx->ctrl_handler, &ge2d_ctrl_ops,
+ V4L2_CID_ROTATE, 0, 270, 90, 0);
+
+ if (ctx->ctrl_handler.error) {
+ int err = ctx->ctrl_handler.error;
+
+ v4l2_err(&ge2d->v4l2_dev, "%s failed\n", __func__);
+ v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct ge2d_frame def_frame = {
+ .pix_fmt = {
+ .width = DEFAULT_WIDTH,
+ .height = DEFAULT_HEIGHT,
+ .bytesperline = DEFAULT_STRIDE,
+ .sizeimage = DEFAULT_STRIDE * DEFAULT_HEIGHT,
+ .field = V4L2_FIELD_NONE,
+ },
+ .crop.width = DEFAULT_WIDTH,
+ .crop.height = DEFAULT_HEIGHT,
+ .fmt = &formats[0],
+};
+
+static int ge2d_open(struct file *file)
+{
+ struct meson_ge2d *ge2d = video_drvdata(file);
+ struct ge2d_ctx *ctx = NULL;
+ int ret = 0;
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+ ctx->ge2d = ge2d;
+
+ /* Set default formats */
+ ctx->in = def_frame;
+ ctx->out = def_frame;
+
+ if (mutex_lock_interruptible(&ge2d->mutex)) {
+ kfree(ctx);
+ return -ERESTARTSYS;
+ }
+ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(ge2d->m2m_dev, ctx, &queue_init);
+ if (IS_ERR(ctx->fh.m2m_ctx)) {
+ ret = PTR_ERR(ctx->fh.m2m_ctx);
+ mutex_unlock(&ge2d->mutex);
+ kfree(ctx);
+ return ret;
+ }
+ v4l2_fh_init(&ctx->fh, video_devdata(file));
+ file->private_data = &ctx->fh;
+ v4l2_fh_add(&ctx->fh);
+
+ ge2d_setup_ctrls(ctx);
+
+ /* Write the default values to the ctx struct */
+ v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
+
+ ctx->fh.ctrl_handler = &ctx->ctrl_handler;
+ mutex_unlock(&ge2d->mutex);
+
+ return 0;
+}
+
+static int ge2d_release(struct file *file)
+{
+ struct ge2d_ctx *ctx =
+ container_of(file->private_data, struct ge2d_ctx, fh);
+ struct meson_ge2d *ge2d = ctx->ge2d;
+
+ mutex_lock(&ge2d->mutex);
+
+ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
+
+ v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+ v4l2_fh_del(&ctx->fh);
+ v4l2_fh_exit(&ctx->fh);
+ kfree(ctx);
+
+ mutex_unlock(&ge2d->mutex);
+
+ return 0;
+}
+
+static const struct v4l2_file_operations ge2d_fops = {
+ .owner = THIS_MODULE,
+ .open = ge2d_open,
+ .release = ge2d_release,
+ .poll = v4l2_m2m_fop_poll,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = v4l2_m2m_fop_mmap,
+};
+
+static const struct video_device ge2d_videodev = {
+ .name = "meson-ge2d",
+ .fops = &ge2d_fops,
+ .ioctl_ops = &ge2d_ioctl_ops,
+ .minor = -1,
+ .release = video_device_release,
+ .vfl_dir = VFL_DIR_M2M,
+ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
+};
+
+static const struct regmap_config meson_ge2d_regmap_conf = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = GE2D_SRC2_STRIDE_CTRL,
+};
+
+static int ge2d_probe(struct platform_device *pdev)
+{
+ struct reset_control *rst;
+ struct video_device *vfd;
+ struct meson_ge2d *ge2d;
+ struct resource *res;
+ void __iomem *regs;
+ int ret = 0;
+ int irq;
+
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+
+ ge2d = devm_kzalloc(&pdev->dev, sizeof(*ge2d), GFP_KERNEL);
+ if (!ge2d)
+ return -ENOMEM;
+
+ ge2d->dev = &pdev->dev;
+ mutex_init(&ge2d->mutex);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_ioremap_resource(ge2d->dev, res);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ ge2d->map = devm_regmap_init_mmio(ge2d->dev, regs,
+ &meson_ge2d_regmap_conf);
+ if (IS_ERR(ge2d->map))
+ return PTR_ERR(ge2d->map);
+
+ irq = platform_get_irq(pdev, 0);
+ ret = devm_request_irq(ge2d->dev, irq, ge2d_isr, 0,
+ dev_name(ge2d->dev), ge2d);
+ if (ret < 0) {
+ dev_err(ge2d->dev, "failed to request irq\n");
+ return ret;
+ }
+
+ rst = devm_reset_control_get(ge2d->dev, NULL);
+ if (IS_ERR(rst)) {
+ dev_err(ge2d->dev, "failed to get core reset controller\n");
+ return PTR_ERR(rst);
+ }
+
+ ge2d->clk = devm_clk_get(ge2d->dev, NULL);
+ if (IS_ERR(ge2d->clk)) {
+ dev_err(ge2d->dev, "failed to get clock\n");
+ return PTR_ERR(ge2d->clk);
+ }
+
+ reset_control_assert(rst);
+ udelay(1);
+ reset_control_deassert(rst);
+
+ ret = clk_prepare_enable(ge2d->clk);
+ if (ret) {
+ dev_err(ge2d->dev, "Cannot enable ge2d sclk: %d\n", ret);
+ return ret;
+ }
+
+ ret = v4l2_device_register(&pdev->dev, &ge2d->v4l2_dev);
+ if (ret)
+ goto disable_clks;
+
+ vfd = video_device_alloc();
+ if (!vfd) {
+ v4l2_err(&ge2d->v4l2_dev, "Failed to allocate video device\n");
+ goto unreg_v4l2_dev;
+ }
+
+ *vfd = ge2d_videodev;
+ vfd->lock = &ge2d->mutex;
+ vfd->v4l2_dev = &ge2d->v4l2_dev;
+
+ video_set_drvdata(vfd, ge2d);
+ ge2d->vfd = vfd;
+
+ platform_set_drvdata(pdev, ge2d);
+ ge2d->m2m_dev = v4l2_m2m_init(&ge2d_m2m_ops);
+ if (IS_ERR(ge2d->m2m_dev)) {
+ v4l2_err(&ge2d->v4l2_dev, "Failed to init mem2mem device\n");
+ ret = PTR_ERR(ge2d->m2m_dev);
+ goto rel_vdev;
+ }
+
+ ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ v4l2_err(&ge2d->v4l2_dev, "Failed to register video device\n");
+ goto rel_m2m;
+ }
+
+ v4l2_info(&ge2d->v4l2_dev, "Registered %s as /dev/%s\n",
+ vfd->name, video_device_node_name(vfd));
+
+ return 0;
+
+rel_m2m:
+ v4l2_m2m_release(ge2d->m2m_dev);
+rel_vdev:
+ video_device_release(ge2d->vfd);
+unreg_v4l2_dev:
+ v4l2_device_unregister(&ge2d->v4l2_dev);
+disable_clks:
+ clk_disable_unprepare(ge2d->clk);
+
+ return ret;
+}
+
+static int ge2d_remove(struct platform_device *pdev)
+{
+ struct meson_ge2d *ge2d = platform_get_drvdata(pdev);
+
+ video_unregister_device(ge2d->vfd);
+ v4l2_m2m_release(ge2d->m2m_dev);
+ video_device_release(ge2d->vfd);
+ v4l2_device_unregister(&ge2d->v4l2_dev);
+ clk_disable_unprepare(ge2d->clk);
+
+ return 0;
+}
+
+static const struct of_device_id meson_ge2d_match[] = {
+ {
+ .compatible = "amlogic,axg-ge2d",
+ },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, meson_ge2d_match);
+
+static struct platform_driver ge2d_drv = {
+ .probe = ge2d_probe,
+ .remove = ge2d_remove,
+ .driver = {
+ .name = "meson-ge2d",
+ .of_match_table = meson_ge2d_match,
+ },
+};
+
+module_platform_driver(ge2d_drv);
+
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_DESCRIPTION("Amlogic 2D Graphic Acceleration Unit");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
index 227245ccaedc..88a23bce569d 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
@@ -1306,6 +1306,7 @@ static int mtk_jpeg_clk_init(struct mtk_jpeg_dev *jpeg)
jpeg->variant->clks);
if (ret) {
dev_err(&pdev->dev, "failed to get jpeg clock:%d\n", ret);
+ put_device(&pdev->dev);
return ret;
}
@@ -1331,6 +1332,12 @@ static void mtk_jpeg_job_timeout_work(struct work_struct *work)
v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
}
+
+static inline void mtk_jpeg_clk_release(struct mtk_jpeg_dev *jpeg)
+{
+ put_device(jpeg->larb);
+}
+
static int mtk_jpeg_probe(struct platform_device *pdev)
{
struct mtk_jpeg_dev *jpeg;
@@ -1435,6 +1442,7 @@ err_m2m_init:
v4l2_device_unregister(&jpeg->v4l2_dev);
err_dev_register:
+ mtk_jpeg_clk_release(jpeg);
err_clk_init:
@@ -1452,6 +1460,7 @@ static int mtk_jpeg_remove(struct platform_device *pdev)
video_device_release(jpeg->vdev);
v4l2_m2m_release(jpeg->m2m_dev);
v4l2_device_unregister(&jpeg->v4l2_dev);
+ mtk_jpeg_clk_release(jpeg);
return 0;
}
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
index 145686d2c219..147dfef1638d 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_drv.c
@@ -232,14 +232,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
mtk_v4l2_err("Could not get vdec IPI device");
return -ENODEV;
}
- if (!pdev->dev.dma_parms) {
- pdev->dev.dma_parms = devm_kzalloc(&pdev->dev,
- sizeof(*pdev->dev.dma_parms),
- GFP_KERNEL);
- if (!pdev->dev.dma_parms)
- return -ENOMEM;
- }
- dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
+ dma_set_max_seg_size(&pdev->dev, UINT_MAX);
dev->fw_handler = mtk_vcodec_fw_select(dev, fw_type, DECODER);
if (IS_ERR(dev->fw_handler))
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
index 36dfe3fc056a..ddee7046ce42 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec_pm.c
@@ -47,11 +47,14 @@ int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev)
dec_clk->clk_info = devm_kcalloc(&pdev->dev,
dec_clk->clk_num, sizeof(*clk_info),
GFP_KERNEL);
- if (!dec_clk->clk_info)
- return -ENOMEM;
+ if (!dec_clk->clk_info) {
+ ret = -ENOMEM;
+ goto put_device;
+ }
} else {
mtk_v4l2_err("Failed to get vdec clock count");
- return -EINVAL;
+ ret = -EINVAL;
+ goto put_device;
}
for (i = 0; i < dec_clk->clk_num; i++) {
@@ -60,25 +63,29 @@ int mtk_vcodec_init_dec_pm(struct mtk_vcodec_dev *mtkdev)
"clock-names", i, &clk_info->clk_name);
if (ret) {
mtk_v4l2_err("Failed to get clock name id = %d", i);
- return ret;
+ goto put_device;
}
clk_info->vcodec_clk = devm_clk_get(&pdev->dev,
clk_info->clk_name);
if (IS_ERR(clk_info->vcodec_clk)) {
mtk_v4l2_err("devm_clk_get (%d)%s fail", i,
clk_info->clk_name);
- return PTR_ERR(clk_info->vcodec_clk);
+ ret = PTR_ERR(clk_info->vcodec_clk);
+ goto put_device;
}
}
pm_runtime_enable(&pdev->dev);
-
+ return 0;
+put_device:
+ put_device(pm->larbvdec);
return ret;
}
void mtk_vcodec_release_dec_pm(struct mtk_vcodec_dev *dev)
{
pm_runtime_disable(dev->pm.dev);
+ put_device(dev->pm.larbvdec);
}
void mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm)
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
index 3be8a04c4c67..dfb42e19bf81 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c
@@ -284,14 +284,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev)
mtk_v4l2_err("Could not get venc IPI device");
return -ENODEV;
}
- if (!pdev->dev.dma_parms) {
- pdev->dev.dma_parms = devm_kzalloc(&pdev->dev,
- sizeof(*pdev->dev.dma_parms),
- GFP_KERNEL);
- if (!pdev->dev.dma_parms)
- return -ENOMEM;
- }
- dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
+ dma_set_max_seg_size(&pdev->dev, UINT_MAX);
dev->fw_handler = mtk_vcodec_fw_select(dev, fw_type, ENCODER);
if (IS_ERR(dev->fw_handler))
diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
index ee22902aaa71..3b7c54d6aa8f 100644
--- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
+++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_pm.c
@@ -47,14 +47,16 @@ int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *mtkdev)
node = of_parse_phandle(dev->of_node, "mediatek,larb", 1);
if (!node) {
mtk_v4l2_err("no mediatek,larb found");
- return -ENODEV;
+ ret = -ENODEV;
+ goto put_larbvenc;
}
pdev = of_find_device_by_node(node);
of_node_put(node);
if (!pdev) {
mtk_v4l2_err("no mediatek,larb device found");
- return -ENODEV;
+ ret = -ENODEV;
+ goto put_larbvenc;
}
pm->larbvenclt = &pdev->dev;
@@ -67,11 +69,14 @@ int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *mtkdev)
enc_clk->clk_info = devm_kcalloc(&pdev->dev,
enc_clk->clk_num, sizeof(*clk_info),
GFP_KERNEL);
- if (!enc_clk->clk_info)
- return -ENOMEM;
+ if (!enc_clk->clk_info) {
+ ret = -ENOMEM;
+ goto put_larbvenclt;
+ }
} else {
mtk_v4l2_err("Failed to get venc clock count");
- return -EINVAL;
+ ret = -EINVAL;
+ goto put_larbvenclt;
}
for (i = 0; i < enc_clk->clk_num; i++) {
@@ -80,22 +85,31 @@ int mtk_vcodec_init_enc_pm(struct mtk_vcodec_dev *mtkdev)
"clock-names", i, &clk_info->clk_name);
if (ret) {
mtk_v4l2_err("venc failed to get clk name %d", i);
- return ret;
+ goto put_larbvenclt;
}
clk_info->vcodec_clk = devm_clk_get(&pdev->dev,
clk_info->clk_name);
if (IS_ERR(clk_info->vcodec_clk)) {
mtk_v4l2_err("venc devm_clk_get (%d)%s fail", i,
clk_info->clk_name);
- return PTR_ERR(clk_info->vcodec_clk);
+ ret = PTR_ERR(clk_info->vcodec_clk);
+ goto put_larbvenclt;
}
}
+ return 0;
+
+put_larbvenclt:
+ put_device(pm->larbvenclt);
+put_larbvenc:
+ put_device(pm->larbvenc);
return ret;
}
void mtk_vcodec_release_enc_pm(struct mtk_vcodec_dev *mtkdev)
{
+ put_device(mtkdev->pm.larbvenclt);
+ put_device(mtkdev->pm.larbvenc);
}
diff --git a/drivers/media/platform/mtk-vpu/mtk_vpu.c b/drivers/media/platform/mtk-vpu/mtk_vpu.c
index 36cb9b6131f7..043894f7188c 100644
--- a/drivers/media/platform/mtk-vpu/mtk_vpu.c
+++ b/drivers/media/platform/mtk-vpu/mtk_vpu.c
@@ -27,6 +27,7 @@
#define INIT_TIMEOUT_MS 2000U
#define IPI_TIMEOUT_MS 2000U
+#define VPU_IDLE_TIMEOUT_MS 1000U
#define VPU_FW_VER_LEN 16
/* maximum program/data TCM (Tightly-Coupled Memory) size */
@@ -57,11 +58,17 @@
#define VPU_DMEM_EXT0_ADDR 0x0014
#define VPU_DMEM_EXT1_ADDR 0x0018
#define HOST_TO_VPU 0x0024
+#define VPU_IDLE_REG 0x002C
+#define VPU_INT_STATUS 0x0034
#define VPU_PC_REG 0x0060
+#define VPU_SP_REG 0x0064
+#define VPU_RA_REG 0x0068
#define VPU_WDT_REG 0x0084
/* vpu inter-processor communication interrupt */
#define VPU_IPC_INT BIT(8)
+/* vpu idle state */
+#define VPU_IDLE_STATE BIT(23)
/**
* enum vpu_fw_type - VPU firmware type
@@ -263,6 +270,20 @@ static int vpu_clock_enable(struct mtk_vpu *vpu)
return ret;
}
+static void vpu_dump_status(struct mtk_vpu *vpu)
+{
+ dev_info(vpu->dev,
+ "vpu: run %x, pc = 0x%x, ra = 0x%x, sp = 0x%x, idle = 0x%x\n"
+ "vpu: int %x, hv = 0x%x, vh = 0x%x, wdt = 0x%x\n",
+ vpu_running(vpu), vpu_cfg_readl(vpu, VPU_PC_REG),
+ vpu_cfg_readl(vpu, VPU_RA_REG), vpu_cfg_readl(vpu, VPU_SP_REG),
+ vpu_cfg_readl(vpu, VPU_IDLE_REG),
+ vpu_cfg_readl(vpu, VPU_INT_STATUS),
+ vpu_cfg_readl(vpu, HOST_TO_VPU),
+ vpu_cfg_readl(vpu, VPU_TO_HOST),
+ vpu_cfg_readl(vpu, VPU_WDT_REG));
+}
+
int vpu_ipi_register(struct platform_device *pdev,
enum ipi_id id, ipi_handler_t handler,
const char *name, void *priv)
@@ -323,6 +344,7 @@ int vpu_ipi_send(struct platform_device *pdev,
if (time_after(jiffies, timeout)) {
dev_err(vpu->dev, "vpu_ipi_send: IPI timeout!\n");
ret = -EIO;
+ vpu_dump_status(vpu);
goto mut_unlock;
}
} while (vpu_cfg_readl(vpu, HOST_TO_VPU));
@@ -342,8 +364,9 @@ int vpu_ipi_send(struct platform_device *pdev,
ret = wait_event_timeout(vpu->ack_wq, vpu->ipi_id_ack[id], timeout);
vpu->ipi_id_ack[id] = false;
if (ret == 0) {
- dev_err(vpu->dev, "vpu ipi %d ack time out !", id);
+ dev_err(vpu->dev, "vpu ipi %d ack time out !\n", id);
ret = -EIO;
+ vpu_dump_status(vpu);
goto clock_disable;
}
vpu_clock_disable(vpu);
@@ -628,7 +651,7 @@ static ssize_t vpu_debug_read(struct file *file, char __user *user_buf,
{
char buf[256];
unsigned int len;
- unsigned int running, pc, vpu_to_host, host_to_vpu, wdt;
+ unsigned int running, pc, vpu_to_host, host_to_vpu, wdt, idle, ra, sp;
int ret;
struct device *dev = file->private_data;
struct mtk_vpu *vpu = dev_get_drvdata(dev);
@@ -645,6 +668,10 @@ static ssize_t vpu_debug_read(struct file *file, char __user *user_buf,
wdt = vpu_cfg_readl(vpu, VPU_WDT_REG);
host_to_vpu = vpu_cfg_readl(vpu, HOST_TO_VPU);
vpu_to_host = vpu_cfg_readl(vpu, VPU_TO_HOST);
+ ra = vpu_cfg_readl(vpu, VPU_RA_REG);
+ sp = vpu_cfg_readl(vpu, VPU_SP_REG);
+ idle = vpu_cfg_readl(vpu, VPU_IDLE_REG);
+
vpu_clock_disable(vpu);
if (running) {
@@ -653,9 +680,12 @@ static ssize_t vpu_debug_read(struct file *file, char __user *user_buf,
"PC: 0x%x\n"
"WDT: 0x%x\n"
"Host to VPU: 0x%x\n"
- "VPU to Host: 0x%x\n",
+ "VPU to Host: 0x%x\n"
+ "SP: 0x%x\n"
+ "RA: 0x%x\n"
+ "idle: 0x%x\n",
vpu->run.fw_ver, pc, wdt,
- host_to_vpu, vpu_to_host);
+ host_to_vpu, vpu_to_host, sp, ra, idle);
} else {
len = snprintf(buf, sizeof(buf), "VPU not running\n");
}
@@ -945,11 +975,74 @@ static int mtk_vpu_remove(struct platform_device *pdev)
return 0;
}
+static int mtk_vpu_suspend(struct device *dev)
+{
+ struct mtk_vpu *vpu = dev_get_drvdata(dev);
+ unsigned long timeout;
+ int ret;
+
+ ret = vpu_clock_enable(vpu);
+ if (ret) {
+ dev_err(dev, "failed to enable vpu clock\n");
+ return ret;
+ }
+
+ mutex_lock(&vpu->vpu_mutex);
+ /* disable vpu timer interrupt */
+ vpu_cfg_writel(vpu, vpu_cfg_readl(vpu, VPU_INT_STATUS) | VPU_IDLE_STATE,
+ VPU_INT_STATUS);
+ /* check if vpu is idle for system suspend */
+ timeout = jiffies + msecs_to_jiffies(VPU_IDLE_TIMEOUT_MS);
+ do {
+ if (time_after(jiffies, timeout)) {
+ dev_err(dev, "vpu idle timeout\n");
+ mutex_unlock(&vpu->vpu_mutex);
+ vpu_clock_disable(vpu);
+ return -EIO;
+ }
+ } while (!vpu_cfg_readl(vpu, VPU_IDLE_REG));
+
+ mutex_unlock(&vpu->vpu_mutex);
+ vpu_clock_disable(vpu);
+ clk_unprepare(vpu->clk);
+
+ return 0;
+}
+
+static int mtk_vpu_resume(struct device *dev)
+{
+ struct mtk_vpu *vpu = dev_get_drvdata(dev);
+ int ret;
+
+ clk_prepare(vpu->clk);
+ ret = vpu_clock_enable(vpu);
+ if (ret) {
+ dev_err(dev, "failed to enable vpu clock\n");
+ return ret;
+ }
+
+ mutex_lock(&vpu->vpu_mutex);
+ /* enable vpu timer interrupt */
+ vpu_cfg_writel(vpu,
+ vpu_cfg_readl(vpu, VPU_INT_STATUS) & ~(VPU_IDLE_STATE),
+ VPU_INT_STATUS);
+ mutex_unlock(&vpu->vpu_mutex);
+ vpu_clock_disable(vpu);
+
+ return 0;
+}
+
+static const struct dev_pm_ops mtk_vpu_pm = {
+ .suspend = mtk_vpu_suspend,
+ .resume = mtk_vpu_resume,
+};
+
static struct platform_driver mtk_vpu_driver = {
.probe = mtk_vpu_probe,
.remove = mtk_vpu_remove,
.driver = {
.name = "mtk_vpu",
+ .pm = &mtk_vpu_pm,
.of_match_table = mtk_vpu_match,
},
};
diff --git a/drivers/media/platform/omap3isp/ispccdc.c b/drivers/media/platform/omap3isp/ispccdc.c
index 0fbb2aa6dd2c..4e8905ef362f 100644
--- a/drivers/media/platform/omap3isp/ispccdc.c
+++ b/drivers/media/platform/omap3isp/ispccdc.c
@@ -299,11 +299,10 @@ static int ccdc_lsc_busy(struct isp_ccdc_device *ccdc)
ISPCCDC_LSC_BUSY;
}
-/* __ccdc_lsc_configure - Apply a new configuration to the LSC engine
+/*
+ * __ccdc_lsc_configure - Apply a new configuration to the LSC engine
* @ccdc: Pointer to ISP CCDC device
* @req: New configuration request
- *
- * context: in_interrupt()
*/
static int __ccdc_lsc_configure(struct isp_ccdc_device *ccdc,
struct ispccdc_lsc_config_req *req)
diff --git a/drivers/media/platform/pxa_camera.c b/drivers/media/platform/pxa_camera.c
index e47520fcb93c..b664ce7558a1 100644
--- a/drivers/media/platform/pxa_camera.c
+++ b/drivers/media/platform/pxa_camera.c
@@ -1256,7 +1256,7 @@ static void pxa_camera_setup_cicr(struct pxa_camera_dev *pcdev,
* transformation. Note that UYVY is the only format that
* should be used if pxa framebuffer Overlay2 is used.
*/
- /* fall through */
+ fallthrough;
case V4L2_PIX_FMT_UYVY:
case V4L2_PIX_FMT_VYUY:
case V4L2_PIX_FMT_YUYV:
@@ -1667,7 +1667,7 @@ static int pxa_camera_get_formats(struct v4l2_device *v4l2_dev,
"Providing format %s using code %d\n",
pxa_camera_formats[0].name, code.code);
}
- /* fall through */
+ fallthrough;
case MEDIA_BUS_FMT_VYUY8_2X8:
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YVYU8_2X8:
diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index 2ffcda06706b..be3fe76f3dc3 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -383,7 +383,8 @@ static u32 csid_src_pad_code(struct csid_device *csid, u32 sink_code,
return 0;
return sink_code;
- } else if (csid->camss->version == CAMSS_8x96) {
+ } else if (csid->camss->version == CAMSS_8x96 ||
+ csid->camss->version == CAMSS_660) {
switch (sink_code) {
case MEDIA_BUS_FMT_SBGGR10_1X10:
{
@@ -718,7 +719,8 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable)
val |= df << CAMSS_CSID_CID_n_CFG_DECODE_FORMAT_SHIFT;
val |= CAMSS_CSID_CID_n_CFG_RDI_MODE_RAW_DUMP;
- if (csid->camss->version == CAMSS_8x96) {
+ if (csid->camss->version == CAMSS_8x96 ||
+ csid->camss->version == CAMSS_660) {
u32 sink_code = csid->fmt[MSM_CSID_PAD_SINK].code;
u32 src_code = csid->fmt[MSM_CSID_PAD_SRC].code;
@@ -1098,7 +1100,8 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid,
csid->formats = csid_formats_8x16;
csid->nformats =
ARRAY_SIZE(csid_formats_8x16);
- } else if (camss->version == CAMSS_8x96) {
+ } else if (camss->version == CAMSS_8x96 ||
+ camss->version == CAMSS_660) {
csid->formats = csid_formats_8x96;
csid->nformats =
ARRAY_SIZE(csid_formats_8x96);
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 2e65caf1ecae..97cb9de85031 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -8,6 +8,7 @@
* Copyright (C) 2016-2018 Linaro Ltd.
*/
+#include "camss.h"
#include "camss-csiphy.h"
#include <linux/delay.h>
@@ -21,6 +22,7 @@
#define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n))
#define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n))
#define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4
+#define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5
#define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n))
#define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02
#define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT 0x50
@@ -198,7 +200,10 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
- val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS;
+ if (csiphy->camss->version == CAMSS_660)
+ val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660;
+ else
+ val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS;
writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l));
val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE;
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
index 85b24054f35e..509c9a59c09c 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
@@ -113,9 +113,7 @@ static int csiphy_set_clock_rates(struct csiphy_device *csiphy)
for (i = 0; i < csiphy->nclocks; i++) {
struct camss_clock *clock = &csiphy->clock[i];
- if (!strcmp(clock->name, "csiphy0_timer") ||
- !strcmp(clock->name, "csiphy1_timer") ||
- !strcmp(clock->name, "csiphy2_timer")) {
+ if (csiphy->rate_set[i]) {
u8 bpp = csiphy_get_bpp(csiphy->formats,
csiphy->nformats,
csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
@@ -554,7 +552,8 @@ int msm_csiphy_subdev_init(struct camss *camss,
csiphy->ops = &csiphy_ops_2ph_1_0;
csiphy->formats = csiphy_formats_8x16;
csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x16);
- } else if (camss->version == CAMSS_8x96) {
+ } else if (camss->version == CAMSS_8x96 ||
+ camss->version == CAMSS_660) {
csiphy->ops = &csiphy_ops_3ph_1_0;
csiphy->formats = csiphy_formats_8x96;
csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96);
@@ -612,6 +611,13 @@ int msm_csiphy_subdev_init(struct camss *camss,
if (!csiphy->clock)
return -ENOMEM;
+ csiphy->rate_set = devm_kcalloc(dev,
+ csiphy->nclocks,
+ sizeof(*csiphy->rate_set),
+ GFP_KERNEL);
+ if (!csiphy->rate_set)
+ return -ENOMEM;
+
for (i = 0; i < csiphy->nclocks; i++) {
struct camss_clock *clock = &csiphy->clock[i];
@@ -639,6 +645,17 @@ int msm_csiphy_subdev_init(struct camss *camss,
for (j = 0; j < clock->nfreqs; j++)
clock->freq[j] = res->clock_rate[i][j];
+
+ if (!strcmp(clock->name, "csiphy0_timer") ||
+ !strcmp(clock->name, "csiphy1_timer") ||
+ !strcmp(clock->name, "csiphy2_timer"))
+ csiphy->rate_set[i] = true;
+
+ if (camss->version == CAMSS_660 &&
+ (!strcmp(clock->name, "csi0_phy") ||
+ !strcmp(clock->name, "csi1_phy") ||
+ !strcmp(clock->name, "csi2_phy")))
+ csiphy->rate_set[i] = true;
}
return 0;
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
index 376f865ad383..f7967ef836dc 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.h
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
@@ -66,6 +66,7 @@ struct csiphy_device {
u32 irq;
char irq_name[30];
struct camss_clock *clock;
+ bool *rate_set;
int nclocks;
u32 timer_clk_rate;
struct csiphy_config cfg;
diff --git a/drivers/media/platform/qcom/camss/camss-ispif.c b/drivers/media/platform/qcom/camss/camss-ispif.c
index db94cfd6c508..adeb92808998 100644
--- a/drivers/media/platform/qcom/camss/camss-ispif.c
+++ b/drivers/media/platform/qcom/camss/camss-ispif.c
@@ -26,6 +26,7 @@
#define MSM_ISPIF_NAME "msm_ispif"
#define ISPIF_RST_CMD_0 0x008
+#define ISPIF_RST_CMD_1 0x00c
#define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)
#define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)
#define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)
@@ -179,7 +180,10 @@ static irqreturn_t ispif_isr_8x96(int irq, void *dev)
writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
if ((value0 >> 27) & 0x1)
- complete(&ispif->reset_complete);
+ complete(&ispif->reset_complete[0]);
+
+ if ((value3 >> 27) & 0x1)
+ complete(&ispif->reset_complete[1]);
if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n");
@@ -237,7 +241,7 @@ static irqreturn_t ispif_isr_8x16(int irq, void *dev)
writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
if ((value0 >> 27) & 0x1)
- complete(&ispif->reset_complete);
+ complete(&ispif->reset_complete[0]);
if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n");
@@ -257,33 +261,18 @@ static irqreturn_t ispif_isr_8x16(int irq, void *dev)
return IRQ_HANDLED;
}
-/*
- * ispif_reset - Trigger reset on ISPIF module and wait to complete
- * @ispif: ISPIF device
- *
- * Return 0 on success or a negative error code otherwise
- */
-static int ispif_reset(struct ispif_device *ispif)
+static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id)
{
unsigned long time;
u32 val;
- int ret;
-
- ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE0);
- if (ret < 0)
- return ret;
- ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE1);
- if (ret < 0)
- return ret;
-
- ret = camss_enable_clocks(ispif->nclocks_for_reset,
- ispif->clock_for_reset,
- to_device(ispif));
- if (ret < 0)
- return ret;
+ if (vfe_id > (to_camss(ispif)->vfe_num - 1)) {
+ dev_err(to_device(ispif),
+ "Error: asked reset for invalid VFE%d\n", vfe_id);
+ return -ENOENT;
+ }
- reinit_completion(&ispif->reset_complete);
+ reinit_completion(&ispif->reset_complete[vfe_id]);
val = ISPIF_RST_CMD_0_STROBED_RST_EN |
ISPIF_RST_CMD_0_MISC_LOGIC_RST |
@@ -303,15 +292,50 @@ static int ispif_reset(struct ispif_device *ispif)
ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
- writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
+ if (vfe_id == 1)
+ writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1);
+ else
+ writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
- time = wait_for_completion_timeout(&ispif->reset_complete,
+ time = wait_for_completion_timeout(&ispif->reset_complete[vfe_id],
msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
if (!time) {
- dev_err(to_device(ispif), "ISPIF reset timeout\n");
- ret = -EIO;
+ dev_err(to_device(ispif),
+ "ISPIF for VFE%d reset timeout\n", vfe_id);
+ return -EIO;
}
+ return 0;
+}
+
+/*
+ * ispif_reset - Trigger reset on ISPIF module and wait to complete
+ * @ispif: ISPIF device
+ *
+ * Return 0 on success or a negative error code otherwise
+ */
+static int ispif_reset(struct ispif_device *ispif, u8 vfe_id)
+{
+ int ret;
+
+ ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE0);
+ if (ret < 0)
+ return ret;
+
+ ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE1);
+ if (ret < 0)
+ return ret;
+
+ ret = camss_enable_clocks(ispif->nclocks_for_reset,
+ ispif->clock_for_reset,
+ to_device(ispif));
+ if (ret < 0)
+ return ret;
+
+ ret = ispif_vfe_reset(ispif, vfe_id);
+ if (ret)
+ dev_dbg(to_device(ispif), "ISPIF Reset failed\n");
+
camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE0);
@@ -355,7 +379,7 @@ static int ispif_set_power(struct v4l2_subdev *sd, int on)
goto exit;
}
- ret = ispif_reset(ispif);
+ ret = ispif_reset(ispif, line->vfe_id);
if (ret < 0) {
pm_runtime_put_sync(dev);
camss_disable_clocks(ispif->nclocks, ispif->clock);
@@ -801,7 +825,8 @@ static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
ispif_select_csid(ispif, intf, csid, vfe, 1);
ispif_select_cid(ispif, intf, cid, vfe, 1);
ispif_config_irq(ispif, intf, vfe, 1);
- if (to_camss(ispif)->version == CAMSS_8x96)
+ if (to_camss(ispif)->version == CAMSS_8x96 ||
+ to_camss(ispif)->version == CAMSS_660)
ispif_config_pack(ispif,
line->fmt[MSM_ISPIF_PAD_SINK].code,
intf, cid, vfe, 1);
@@ -818,7 +843,8 @@ static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
return ret;
mutex_lock(&ispif->config_lock);
- if (to_camss(ispif)->version == CAMSS_8x96)
+ if (to_camss(ispif)->version == CAMSS_8x96 ||
+ to_camss(ispif)->version == CAMSS_660)
ispif_config_pack(ispif,
line->fmt[MSM_ISPIF_PAD_SINK].code,
intf, cid, vfe, 0);
@@ -1074,7 +1100,8 @@ int msm_ispif_subdev_init(struct ispif_device *ispif,
/* Number of ISPIF lines - same as number of CSID hardware modules */
if (to_camss(ispif)->version == CAMSS_8x16)
ispif->line_num = 2;
- else if (to_camss(ispif)->version == CAMSS_8x96)
+ else if (to_camss(ispif)->version == CAMSS_8x96 ||
+ to_camss(ispif)->version == CAMSS_660)
ispif->line_num = 4;
else
return -EINVAL;
@@ -1092,7 +1119,8 @@ int msm_ispif_subdev_init(struct ispif_device *ispif,
ispif->line[i].formats = ispif_formats_8x16;
ispif->line[i].nformats =
ARRAY_SIZE(ispif_formats_8x16);
- } else if (to_camss(ispif)->version == CAMSS_8x96) {
+ } else if (to_camss(ispif)->version == CAMSS_8x96 ||
+ to_camss(ispif)->version == CAMSS_660) {
ispif->line[i].formats = ispif_formats_8x96;
ispif->line[i].nformats =
ARRAY_SIZE(ispif_formats_8x96);
@@ -1132,7 +1160,8 @@ int msm_ispif_subdev_init(struct ispif_device *ispif,
if (to_camss(ispif)->version == CAMSS_8x16)
ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
- else if (to_camss(ispif)->version == CAMSS_8x96)
+ else if (to_camss(ispif)->version == CAMSS_8x96 ||
+ to_camss(ispif)->version == CAMSS_660)
ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
else
@@ -1192,7 +1221,8 @@ int msm_ispif_subdev_init(struct ispif_device *ispif,
mutex_init(&ispif->config_lock);
- init_completion(&ispif->reset_complete);
+ for (i = 0; i < MSM_ISPIF_VFE_NUM; i++)
+ init_completion(&ispif->reset_complete[i]);
return 0;
}
diff --git a/drivers/media/platform/qcom/camss/camss-ispif.h b/drivers/media/platform/qcom/camss/camss-ispif.h
index 1a5ba2425a42..4132174f7ea1 100644
--- a/drivers/media/platform/qcom/camss/camss-ispif.h
+++ b/drivers/media/platform/qcom/camss/camss-ispif.h
@@ -56,7 +56,7 @@ struct ispif_device {
int nclocks;
struct camss_clock *clock_for_reset;
int nclocks_for_reset;
- struct completion reset_complete;
+ struct completion reset_complete[MSM_ISPIF_VFE_NUM];
int power_count;
struct mutex power_lock;
struct ispif_intf_cmd_reg intf_cmd[MSM_ISPIF_VFE_NUM];
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c
index 0dca8bf9281e..b5704a2f119b 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c
@@ -133,6 +133,11 @@
#define VFE_0_BUS_BDG_QOS_CFG_7 0x420
#define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa9
+#define VFE48_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5
+#define VFE48_0_BUS_BDG_QOS_CFG_3_CFG 0xaa55aaa5
+#define VFE48_0_BUS_BDG_QOS_CFG_4_CFG 0xaa55aa55
+#define VFE48_0_BUS_BDG_QOS_CFG_7_CFG 0x0005aa55
+
#define VFE_0_BUS_BDG_DS_CFG_0 0x424
#define VFE_0_BUS_BDG_DS_CFG_0_CFG 0xcccc0011
#define VFE_0_BUS_BDG_DS_CFG_1 0x428
@@ -153,6 +158,9 @@
#define VFE_0_BUS_BDG_DS_CFG_16 0x464
#define VFE_0_BUS_BDG_DS_CFG_16_CFG 0x40000103
+#define VFE48_0_BUS_BDG_DS_CFG_0_CFG 0xcccc1111
+#define VFE48_0_BUS_BDG_DS_CFG_16_CFG 0x00000110
+
#define VFE_0_RDI_CFG_x(x) (0x46c + (0x4 * (x)))
#define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28
#define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28)
@@ -231,6 +239,9 @@
#define VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL BIT(3)
#define VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE BIT(4)
+#define VFE48_0_BUS_IMAGE_MASTER_CMD 0xcec
+#define VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(x) (2 * (x))
+
#define CAMIF_TIMEOUT_SLEEP_US 1000
#define CAMIF_TIMEOUT_ALL_US 1000000
@@ -246,7 +257,7 @@ static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev)
dev_err(dev, "VFE HW Version = 0x%08x\n", hw_version);
}
-static u16 vfe_get_ub_size(u8 vfe_id)
+static u16 vfe47_get_ub_size(u8 vfe_id)
{
if (vfe_id == 0)
return MSM_VFE_VFE0_UB_SIZE_RDI;
@@ -299,7 +310,7 @@ static void vfe_halt_clear(struct vfe_device *vfe)
writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);
}
-static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable)
+static void vfe47_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable)
{
if (enable)
vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm),
@@ -883,7 +894,7 @@ static void vfe_set_clamp_cfg(struct vfe_device *vfe)
writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG);
}
-static void vfe_set_qos(struct vfe_device *vfe)
+static void vfe47_set_qos(struct vfe_device *vfe)
{
u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG;
u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG;
@@ -898,7 +909,7 @@ static void vfe_set_qos(struct vfe_device *vfe)
writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7);
}
-static void vfe_set_ds(struct vfe_device *vfe)
+static void vfe47_set_ds(struct vfe_device *vfe)
{
u32 val = VFE_0_BUS_BDG_DS_CFG_0_CFG;
u32 val16 = VFE_0_BUS_BDG_DS_CFG_16_CFG;
@@ -1098,11 +1109,115 @@ static irqreturn_t vfe_isr(int irq, void *dev)
const struct vfe_hw_ops vfe_ops_4_7 = {
.hw_version_read = vfe_hw_version_read,
- .get_ub_size = vfe_get_ub_size,
+ .get_ub_size = vfe47_get_ub_size,
+ .global_reset = vfe_global_reset,
+ .halt_request = vfe_halt_request,
+ .halt_clear = vfe_halt_clear,
+ .wm_enable = vfe47_wm_enable,
+ .wm_frame_based = vfe_wm_frame_based,
+ .wm_line_based = vfe_wm_line_based,
+ .wm_set_framedrop_period = vfe_wm_set_framedrop_period,
+ .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern,
+ .wm_set_ub_cfg = vfe_wm_set_ub_cfg,
+ .bus_reload_wm = vfe_bus_reload_wm,
+ .wm_set_ping_addr = vfe_wm_set_ping_addr,
+ .wm_set_pong_addr = vfe_wm_set_pong_addr,
+ .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status,
+ .bus_enable_wr_if = vfe_bus_enable_wr_if,
+ .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi,
+ .wm_set_subsample = vfe_wm_set_subsample,
+ .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi,
+ .set_xbar_cfg = vfe_set_xbar_cfg,
+ .set_realign_cfg = vfe_set_realign_cfg,
+ .set_rdi_cid = vfe_set_rdi_cid,
+ .reg_update = vfe_reg_update,
+ .reg_update_clear = vfe_reg_update_clear,
+ .enable_irq_wm_line = vfe_enable_irq_wm_line,
+ .enable_irq_pix_line = vfe_enable_irq_pix_line,
+ .enable_irq_common = vfe_enable_irq_common,
+ .set_demux_cfg = vfe_set_demux_cfg,
+ .set_scale_cfg = vfe_set_scale_cfg,
+ .set_crop_cfg = vfe_set_crop_cfg,
+ .set_clamp_cfg = vfe_set_clamp_cfg,
+ .set_qos = vfe47_set_qos,
+ .set_ds = vfe47_set_ds,
+ .set_cgc_override = vfe_set_cgc_override,
+ .set_camif_cfg = vfe_set_camif_cfg,
+ .set_camif_cmd = vfe_set_camif_cmd,
+ .set_module_cfg = vfe_set_module_cfg,
+ .camif_wait_for_stop = vfe_camif_wait_for_stop,
+ .isr_read = vfe_isr_read,
+ .violation_read = vfe_violation_read,
+ .isr = vfe_isr,
+};
+
+static u16 vfe48_get_ub_size(u8 vfe_id)
+{
+ /* On VFE4.8 the ub-size is the same on both instances */
+ return MSM_VFE_VFE0_UB_SIZE_RDI;
+}
+
+static void vfe48_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable)
+{
+ if (enable)
+ writel_relaxed(2 << VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(wm),
+ vfe->base + VFE48_0_BUS_IMAGE_MASTER_CMD);
+ else
+ writel_relaxed(1 << VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(wm),
+ vfe->base + VFE48_0_BUS_IMAGE_MASTER_CMD);
+
+ /* The WM must be enabled before sending other commands */
+ wmb();
+}
+
+static void vfe48_set_qos(struct vfe_device *vfe)
+{
+ u32 val = VFE48_0_BUS_BDG_QOS_CFG_0_CFG;
+ u32 val3 = VFE48_0_BUS_BDG_QOS_CFG_3_CFG;
+ u32 val4 = VFE48_0_BUS_BDG_QOS_CFG_4_CFG;
+ u32 val7 = VFE48_0_BUS_BDG_QOS_CFG_7_CFG;
+
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2);
+ writel_relaxed(val3, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3);
+ writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4);
+ writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5);
+ writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6);
+ writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7);
+}
+
+static void vfe48_set_ds(struct vfe_device *vfe)
+{
+ u32 val = VFE48_0_BUS_BDG_DS_CFG_0_CFG;
+ u32 val16 = VFE48_0_BUS_BDG_DS_CFG_16_CFG;
+
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14);
+ writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15);
+ writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16);
+}
+
+const struct vfe_hw_ops vfe_ops_4_8 = {
+ .hw_version_read = vfe_hw_version_read,
+ .get_ub_size = vfe48_get_ub_size,
.global_reset = vfe_global_reset,
.halt_request = vfe_halt_request,
.halt_clear = vfe_halt_clear,
- .wm_enable = vfe_wm_enable,
+ .wm_enable = vfe48_wm_enable,
.wm_frame_based = vfe_wm_frame_based,
.wm_line_based = vfe_wm_line_based,
.wm_set_framedrop_period = vfe_wm_set_framedrop_period,
@@ -1128,8 +1243,8 @@ const struct vfe_hw_ops vfe_ops_4_7 = {
.set_scale_cfg = vfe_set_scale_cfg,
.set_crop_cfg = vfe_set_crop_cfg,
.set_clamp_cfg = vfe_set_clamp_cfg,
- .set_qos = vfe_set_qos,
- .set_ds = vfe_set_ds,
+ .set_qos = vfe48_set_qos,
+ .set_ds = vfe48_set_ds,
.set_cgc_override = vfe_set_cgc_override,
.set_camif_cfg = vfe_set_camif_cfg,
.set_camif_cmd = vfe_set_camif_cmd,
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index b7d2293a5004..fae2b513b2f9 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -205,7 +205,8 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
return sink_code;
}
- else if (vfe->camss->version == CAMSS_8x96)
+ else if (vfe->camss->version == CAMSS_8x96 ||
+ vfe->camss->version == CAMSS_660)
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_2X8:
{
@@ -1991,12 +1992,19 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe,
vfe->isr_ops.comp_done = vfe_isr_comp_done;
vfe->isr_ops.wm_done = vfe_isr_wm_done;
- if (camss->version == CAMSS_8x16)
+ switch (camss->version) {
+ case CAMSS_8x16:
vfe->ops = &vfe_ops_4_1;
- else if (camss->version == CAMSS_8x96)
+ break;
+ case CAMSS_8x96:
vfe->ops = &vfe_ops_4_7;
- else
+ break;
+ case CAMSS_660:
+ vfe->ops = &vfe_ops_4_8;
+ break;
+ default:
return -EINVAL;
+ }
/* Memory */
@@ -2095,7 +2103,8 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe,
l->formats = formats_rdi_8x16;
l->nformats = ARRAY_SIZE(formats_rdi_8x16);
}
- } else if (camss->version == CAMSS_8x96) {
+ } else if (camss->version == CAMSS_8x96 ||
+ camss->version == CAMSS_660) {
if (i == VFE_LINE_PIX) {
l->formats = formats_pix_8x96;
l->nformats = ARRAY_SIZE(formats_pix_8x96);
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
index a90b0d2cc6de..5bce6736e4bb 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.h
+++ b/drivers/media/platform/qcom/camss/camss-vfe.h
@@ -180,5 +180,6 @@ void msm_vfe_get_vfe_line_id(struct media_entity *entity, enum vfe_line_id *id);
extern const struct vfe_hw_ops vfe_ops_4_1;
extern const struct vfe_hw_ops vfe_ops_4_7;
+extern const struct vfe_hw_ops vfe_ops_4_8;
#endif /* QC_MSM_CAMSS_VFE_H */
diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/media/platform/qcom/camss/camss-video.c
index 114c3ae4a4ab..bd9334af1c73 100644
--- a/drivers/media/platform/qcom/camss/camss-video.c
+++ b/drivers/media/platform/qcom/camss/camss-video.c
@@ -535,20 +535,38 @@ static int video_querycap(struct file *file, void *fh,
return 0;
}
-/*
- * Returns the index in the video->formats[] array of the element which
- * has the "ndx"th unique value of pixelformat field.
- * If not found (no more unique pixelformat's) returns -EINVAL.
- */
-static int video_get_unique_pixelformat_by_index(struct camss_video *video,
- int ndx)
+static int video_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f)
{
+ struct camss_video *video = video_drvdata(file);
int i, j, k;
+ u32 mcode = f->mbus_code;
- /* find index "i" of "k"th unique pixelformat in formats array */
+ if (f->type != video->type)
+ return -EINVAL;
+
+ if (f->index >= video->nformats)
+ return -EINVAL;
+
+ /*
+ * Find index "i" of "k"th unique pixelformat in formats array.
+ *
+ * If f->mbus_code passed to video_enum_fmt() is not zero, a device
+ * with V4L2_CAP_IO_MC capability restricts enumeration to only the
+ * pixel formats that can be produced from that media bus code.
+ * This is implemented by skipping video->formats[] entries with
+ * code != f->mbus_code (if f->mbus_code is not zero).
+ * If the f->mbus_code passed to video_enum_fmt() is not supported,
+ * -EINVAL is returned.
+ * If f->mbus_code is zero, all the pixel formats are enumerated.
+ */
k = -1;
for (i = 0; i < video->nformats; i++) {
+ if (mcode != 0 && video->formats[i].code != mcode)
+ continue;
+
for (j = 0; j < i; j++) {
+ if (mcode != 0 && video->formats[j].code != mcode)
+ continue;
if (video->formats[i].pixelformat ==
video->formats[j].pixelformat)
break;
@@ -557,53 +575,16 @@ static int video_get_unique_pixelformat_by_index(struct camss_video *video,
if (j == i)
k++;
- if (k == ndx)
- return i;
- }
-
- return -EINVAL;
-}
-
-/*
- * Returns the index in the video->formats[] array of the element which
- * has code equal to mcode.
- * If not found returns -EINVAL.
- */
-static int video_get_pixelformat_by_mbus_code(struct camss_video *video,
- u32 mcode)
-{
- int i;
-
- for (i = 0; i < video->nformats; i++) {
- if (video->formats[i].code == mcode)
- return i;
- }
-
- return -EINVAL;
-}
-
-static int video_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f)
-{
- struct camss_video *video = video_drvdata(file);
- int i;
-
- if (f->type != video->type)
- return -EINVAL;
-
- if (f->index >= video->nformats)
- return -EINVAL;
-
- if (f->mbus_code) {
- /* Each entry in formats[] table has unique mbus_code */
- if (f->index > 0)
- return -EINVAL;
-
- i = video_get_pixelformat_by_mbus_code(video, f->mbus_code);
- } else {
- i = video_get_unique_pixelformat_by_index(video, f->index);
+ if (k == f->index)
+ break;
}
- if (i < 0)
+ if (k < f->index)
+ /*
+ * All the unique pixel formats matching the arguments
+ * have been enumerated (k >= 0 and f->index > 0), or
+ * no pixel formats match the non-zero f->mbus_code (k == -1).
+ */
return -EINVAL;
f->pixelformat = video->formats[i].pixelformat;
@@ -970,7 +951,8 @@ int msm_video_register(struct camss_video *video, struct v4l2_device *v4l2_dev,
video->formats = formats_rdi_8x16;
video->nformats = ARRAY_SIZE(formats_rdi_8x16);
}
- } else if (video->camss->version == CAMSS_8x96) {
+ } else if (video->camss->version == CAMSS_8x96 ||
+ video->camss->version == CAMSS_660) {
if (is_pix) {
video->formats = formats_pix_8x96;
video->nformats = ARRAY_SIZE(formats_pix_8x96);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 9186881afc98..8fefce57bc49 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -283,6 +283,188 @@ static const struct resources vfe_res_8x96[] = {
}
};
+static const struct resources csiphy_res_660[] = {
+ /* CSIPHY0 */
+ {
+ .regulator = { NULL },
+ .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer",
+ "csi0_phy", "csiphy_ahb2crif" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000, 269333333 },
+ { 0 } },
+ .reg = { "csiphy0", "csiphy0_clk_mux" },
+ .interrupt = { "csiphy0" }
+ },
+
+ /* CSIPHY1 */
+ {
+ .regulator = { NULL },
+ .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer",
+ "csi1_phy", "csiphy_ahb2crif" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000, 269333333 },
+ { 0 } },
+ .reg = { "csiphy1", "csiphy1_clk_mux" },
+ .interrupt = { "csiphy1" }
+ },
+
+ /* CSIPHY2 */
+ {
+ .regulator = { NULL },
+ .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer",
+ "csi2_phy", "csiphy_ahb2crif" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000, 269333333 },
+ { 0 } },
+ .reg = { "csiphy2", "csiphy2_clk_mux" },
+ .interrupt = { "csiphy2" }
+ }
+};
+
+static const struct resources csid_res_660[] = {
+ /* CSID0 */
+ {
+ .regulator = { "vdda", "vdd_sec" },
+ .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
+ "csi0", "csi0_phy", "csi0_pix", "csi0_rdi",
+ "cphy_csid0" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000, 310000000,
+ 404000000, 465000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" }
+ },
+
+ /* CSID1 */
+ {
+ .regulator = { "vdda", "vdd_sec" },
+ .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
+ "csi1", "csi1_phy", "csi1_pix", "csi1_rdi",
+ "cphy_csid1" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000, 310000000,
+ 404000000, 465000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" }
+ },
+
+ /* CSID2 */
+ {
+ .regulator = { "vdda", "vdd_sec" },
+ .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
+ "csi2", "csi2_phy", "csi2_pix", "csi2_rdi",
+ "cphy_csid2" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000, 310000000,
+ 404000000, 465000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" }
+ },
+
+ /* CSID3 */
+ {
+ .regulator = { "vdda", "vdd_sec" },
+ .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
+ "csi3", "csi3_phy", "csi3_pix", "csi3_rdi",
+ "cphy_csid3" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 100000000, 200000000, 310000000,
+ 404000000, 465000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid3" },
+ .interrupt = { "csid3" }
+ }
+};
+
+static const struct resources_ispif ispif_res_660 = {
+ /* ISPIF */
+ .clock = { "top_ahb", "ahb", "ispif_ahb",
+ "csi0", "csi0_pix", "csi0_rdi",
+ "csi1", "csi1_pix", "csi1_rdi",
+ "csi2", "csi2_pix", "csi2_rdi",
+ "csi3", "csi3_pix", "csi3_rdi" },
+ .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
+ .reg = { "ispif", "csi_clk_mux" },
+ .interrupt = "ispif"
+};
+
+static const struct resources vfe_res_660[] = {
+ /* VFE0 */
+ {
+ .regulator = { NULL },
+ .clock = { "throttle_axi", "top_ahb", "ahb", "vfe0",
+ "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi",
+ "vfe0_stream"},
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 120000000, 200000000, 256000000,
+ 300000000, 404000000, 480000000,
+ 540000000, 576000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" }
+ },
+
+ /* VFE1 */
+ {
+ .regulator = { NULL },
+ .clock = { "throttle_axi", "top_ahb", "ahb", "vfe1",
+ "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi",
+ "vfe1_stream"},
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 120000000, 200000000, 256000000,
+ 300000000, 404000000, 480000000,
+ 540000000, 576000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" }
+ }
+};
+
/*
* camss_add_clock_margin - Add margin to clock frequency rate
* @rate: Clock frequency rate
@@ -397,7 +579,8 @@ int camss_get_pixel_clock(struct media_entity *entity, u32 *pixel_clock)
int camss_pm_domain_on(struct camss *camss, int id)
{
- if (camss->version == CAMSS_8x96) {
+ if (camss->version == CAMSS_8x96 ||
+ camss->version == CAMSS_660) {
camss->genpd_link[id] = device_link_add(camss->dev,
camss->genpd[id], DL_FLAG_STATELESS |
DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
@@ -411,7 +594,8 @@ int camss_pm_domain_on(struct camss *camss, int id)
void camss_pm_domain_off(struct camss *camss, int id)
{
- if (camss->version == CAMSS_8x96)
+ if (camss->version == CAMSS_8x96 ||
+ camss->version == CAMSS_660)
device_link_del(camss->genpd_link[id]);
}
@@ -533,6 +717,11 @@ static int camss_init_subdevices(struct camss *camss)
csid_res = csid_res_8x96;
ispif_res = &ispif_res_8x96;
vfe_res = vfe_res_8x96;
+ } else if (camss->version == CAMSS_660) {
+ csiphy_res = csiphy_res_660;
+ csid_res = csid_res_660;
+ ispif_res = &ispif_res_660;
+ vfe_res = vfe_res_660;
} else {
return -EINVAL;
}
@@ -833,6 +1022,12 @@ static int camss_probe(struct platform_device *pdev)
camss->csiphy_num = 3;
camss->csid_num = 4;
camss->vfe_num = 2;
+ } else if (of_device_is_compatible(dev->of_node,
+ "qcom,sdm660-camss")) {
+ camss->version = CAMSS_660;
+ camss->csiphy_num = 3;
+ camss->csid_num = 4;
+ camss->vfe_num = 2;
} else {
ret = -EINVAL;
goto err_free;
@@ -919,7 +1114,8 @@ static int camss_probe(struct platform_device *pdev)
}
}
- if (camss->version == CAMSS_8x96) {
+ if (camss->version == CAMSS_8x96 ||
+ camss->version == CAMSS_660) {
camss->genpd[PM_DOMAIN_VFE0] = dev_pm_domain_attach_by_id(
camss->dev, PM_DOMAIN_VFE0);
if (IS_ERR(camss->genpd[PM_DOMAIN_VFE0]))
@@ -958,7 +1154,8 @@ void camss_delete(struct camss *camss)
pm_runtime_disable(camss->dev);
- if (camss->version == CAMSS_8x96) {
+ if (camss->version == CAMSS_8x96 ||
+ camss->version == CAMSS_660) {
dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE0], true);
dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE1], true);
}
@@ -989,6 +1186,7 @@ static int camss_remove(struct platform_device *pdev)
static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss" },
{ .compatible = "qcom,msm8996-camss" },
+ { .compatible = "qcom,sdm660-camss" },
{ }
};
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 1376b07889bf..3a0484683cd6 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -65,6 +65,7 @@ enum pm_domain {
enum camss_version {
CAMSS_8x16,
CAMSS_8x96,
+ CAMSS_660,
};
struct camss {
diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c
index 6103aaf43987..bdd293faaad0 100644
--- a/drivers/media/platform/qcom/venus/core.c
+++ b/drivers/media/platform/qcom/venus/core.c
@@ -345,6 +345,14 @@ static int venus_remove(struct platform_device *pdev)
return ret;
}
+static void venus_core_shutdown(struct platform_device *pdev)
+{
+ struct venus_core *core = platform_get_drvdata(pdev);
+
+ venus_shutdown(core);
+ venus_firmware_deinit(core);
+}
+
static __maybe_unused int venus_runtime_suspend(struct device *dev)
{
struct venus_core *core = dev_get_drvdata(dev);
@@ -355,12 +363,26 @@ static __maybe_unused int venus_runtime_suspend(struct device *dev)
if (ret)
return ret;
+ if (pm_ops->core_power) {
+ ret = pm_ops->core_power(dev, POWER_OFF);
+ if (ret)
+ return ret;
+ }
+
ret = icc_set_bw(core->cpucfg_path, 0, 0);
if (ret)
- return ret;
+ goto err_cpucfg_path;
- if (pm_ops->core_power)
- ret = pm_ops->core_power(dev, POWER_OFF);
+ ret = icc_set_bw(core->video_path, 0, 0);
+ if (ret)
+ goto err_video_path;
+
+ return ret;
+
+err_video_path:
+ icc_set_bw(core->cpucfg_path, kbps_to_icc(1000), 0);
+err_cpucfg_path:
+ pm_ops->core_power(dev, POWER_ON);
return ret;
}
@@ -371,16 +393,20 @@ static __maybe_unused int venus_runtime_resume(struct device *dev)
const struct venus_pm_ops *pm_ops = core->pm_ops;
int ret;
+ ret = icc_set_bw(core->video_path, kbps_to_icc(20000), 0);
+ if (ret)
+ return ret;
+
+ ret = icc_set_bw(core->cpucfg_path, kbps_to_icc(1000), 0);
+ if (ret)
+ return ret;
+
if (pm_ops->core_power) {
ret = pm_ops->core_power(dev, POWER_ON);
if (ret)
return ret;
}
- ret = icc_set_bw(core->cpucfg_path, 0, kbps_to_icc(1000));
- if (ret)
- return ret;
-
return hfi_core_resume(core, false);
}
@@ -602,6 +628,7 @@ static struct platform_driver qcom_venus_driver = {
.of_match_table = venus_dt_match,
.pm = &venus_pm_ops,
},
+ .shutdown = venus_core_shutdown,
};
module_platform_driver(qcom_venus_driver);
diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h
index 05c9fbd51f0c..f03ed427accd 100644
--- a/drivers/media/platform/qcom/venus/core.h
+++ b/drivers/media/platform/qcom/venus/core.h
@@ -372,6 +372,7 @@ struct venus_inst {
unsigned int streamon_cap, streamon_out;
u32 width;
u32 height;
+ struct v4l2_rect crop;
u32 out_width;
u32 out_height;
u32 colorspace;
diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/platform/qcom/venus/firmware.c
index 1db64a854b88..d03e2dd5808c 100644
--- a/drivers/media/platform/qcom/venus/firmware.c
+++ b/drivers/media/platform/qcom/venus/firmware.c
@@ -171,9 +171,14 @@ static int venus_shutdown_no_tz(struct venus_core *core)
iommu = core->fw.iommu_domain;
- unmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, mapped);
- if (unmapped != mapped)
- dev_err(dev, "failed to unmap firmware\n");
+ if (core->fw.mapped_mem_size && iommu) {
+ unmapped = iommu_unmap(iommu, VENUS_FW_START_ADDR, mapped);
+
+ if (unmapped != mapped)
+ dev_err(dev, "failed to unmap firmware\n");
+ else
+ core->fw.mapped_mem_size = 0;
+ }
return 0;
}
@@ -305,7 +310,11 @@ void venus_firmware_deinit(struct venus_core *core)
iommu = core->fw.iommu_domain;
iommu_detach_device(iommu, core->fw.dev);
- iommu_domain_free(iommu);
+
+ if (core->fw.iommu_domain) {
+ iommu_domain_free(iommu);
+ core->fw.iommu_domain = NULL;
+ }
platform_device_unregister(to_platform_device(core->fw.dev));
}
diff --git a/drivers/media/platform/qcom/venus/hfi.c b/drivers/media/platform/qcom/venus/hfi.c
index a59022adb14c..638ed5cfe05e 100644
--- a/drivers/media/platform/qcom/venus/hfi.c
+++ b/drivers/media/platform/qcom/venus/hfi.c
@@ -198,6 +198,18 @@ int hfi_session_init(struct venus_inst *inst, u32 pixfmt)
const struct hfi_ops *ops = core->ops;
int ret;
+ /*
+ * If core shutdown is in progress or if we are in system
+ * recovery, return an error as during system error recovery
+ * session_init() can't pass successfully
+ */
+ mutex_lock(&core->lock);
+ if (!core->ops || core->sys_error) {
+ mutex_unlock(&core->lock);
+ return -EIO;
+ }
+ mutex_unlock(&core->lock);
+
if (inst->state != INST_UNINIT)
return -EINVAL;
diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c
index a9538c2cc3c9..ca99908ca3d3 100644
--- a/drivers/media/platform/qcom/venus/pm_helpers.c
+++ b/drivers/media/platform/qcom/venus/pm_helpers.c
@@ -212,6 +212,16 @@ static int load_scale_bw(struct venus_core *core)
}
mutex_unlock(&core->lock);
+ /*
+ * keep minimum bandwidth vote for "video-mem" path,
+ * so that clks can be disabled during vdec_session_release().
+ * Actual bandwidth drop will be done during device supend
+ * so that device can power down without any warnings.
+ */
+
+ if (!total_avg && !total_peak)
+ total_avg = kbps_to_icc(1000);
+
dev_dbg(core->dev, VDBGL "total: avg_bw: %u, peak_bw: %u\n",
total_avg, total_peak);
@@ -928,7 +938,7 @@ static unsigned long calculate_inst_freq(struct venus_inst *inst,
u32 fps = (u32)inst->fps;
u32 mbs_per_sec;
- mbs_per_sec = load_per_instance(inst) / fps;
+ mbs_per_sec = load_per_instance(inst);
vpp_freq = mbs_per_sec * inst->clk_data.codec_freq_data->vpp_freq;
/* 21 / 20 is overhead factor */
diff --git a/drivers/media/platform/qcom/venus/vdec.c b/drivers/media/platform/qcom/venus/vdec.c
index ea13170a6a2c..8488411204c3 100644
--- a/drivers/media/platform/qcom/venus/vdec.c
+++ b/drivers/media/platform/qcom/venus/vdec.c
@@ -325,6 +325,10 @@ static int vdec_s_fmt(struct file *file, void *fh, struct v4l2_format *f)
inst->width = format.fmt.pix_mp.width;
inst->height = format.fmt.pix_mp.height;
+ inst->crop.top = 0;
+ inst->crop.left = 0;
+ inst->crop.width = inst->width;
+ inst->crop.height = inst->height;
if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
inst->fmt_out = fmt;
@@ -343,6 +347,9 @@ vdec_g_selection(struct file *file, void *fh, struct v4l2_selection *s)
s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
return -EINVAL;
+ s->r.top = 0;
+ s->r.left = 0;
+
switch (s->target) {
case V4L2_SEL_TGT_CROP_BOUNDS:
case V4L2_SEL_TGT_CROP_DEFAULT:
@@ -363,16 +370,12 @@ vdec_g_selection(struct file *file, void *fh, struct v4l2_selection *s)
case V4L2_SEL_TGT_COMPOSE:
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
- s->r.width = inst->out_width;
- s->r.height = inst->out_height;
+ s->r = inst->crop;
break;
default:
return -EINVAL;
}
- s->r.top = 0;
- s->r.left = 0;
-
return 0;
}
@@ -1309,6 +1312,21 @@ static void vdec_event_change(struct venus_inst *inst,
inst->width = format.fmt.pix_mp.width;
inst->height = format.fmt.pix_mp.height;
+ /*
+ * Some versions of the firmware do not report crop information for
+ * all codecs. For these cases, set the crop to the coded resolution.
+ */
+ if (ev_data->input_crop.width > 0 && ev_data->input_crop.height > 0) {
+ inst->crop.left = ev_data->input_crop.left;
+ inst->crop.top = ev_data->input_crop.top;
+ inst->crop.width = ev_data->input_crop.width;
+ inst->crop.height = ev_data->input_crop.height;
+ } else {
+ inst->crop.left = 0;
+ inst->crop.top = 0;
+ inst->crop.width = ev_data->width;
+ inst->crop.height = ev_data->height;
+ }
inst->out_width = ev_data->width;
inst->out_height = ev_data->height;
@@ -1412,6 +1430,10 @@ static void vdec_inst_init(struct venus_inst *inst)
inst->fmt_cap = &vdec_formats[0];
inst->width = frame_width_min(inst);
inst->height = ALIGN(frame_height_min(inst), 32);
+ inst->crop.left = 0;
+ inst->crop.top = 0;
+ inst->crop.width = inst->width;
+ inst->crop.height = inst->height;
inst->out_width = frame_width_min(inst);
inst->out_height = frame_height_min(inst);
inst->fps = 30;
diff --git a/drivers/media/platform/qcom/venus/venc.c b/drivers/media/platform/qcom/venus/venc.c
index 47246528ac7e..1c61602c5de1 100644
--- a/drivers/media/platform/qcom/venus/venc.c
+++ b/drivers/media/platform/qcom/venus/venc.c
@@ -1028,7 +1028,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq,
static void venc_inst_init(struct venus_inst *inst)
{
- inst->fmt_cap = &venc_formats[2];
+ inst->fmt_cap = &venc_formats[3];
inst->fmt_out = &venc_formats[0];
inst->width = 1280;
inst->height = ALIGN(720, 32);
diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
index 34d003e0e9b9..98bff765b02e 100644
--- a/drivers/media/platform/rcar-vin/rcar-core.c
+++ b/drivers/media/platform/rcar-vin/rcar-core.c
@@ -185,8 +185,8 @@ static int rvin_group_link_notify(struct media_link *link, u32 flags,
*/
sd = media_entity_to_v4l2_subdev(link->source->entity);
for (i = 0; i < RCAR_VIN_NUM; i++) {
- if (group->vin[i] && group->vin[i]->parallel &&
- group->vin[i]->parallel->subdev == sd) {
+ if (group->vin[i] &&
+ group->vin[i]->parallel.subdev == sd) {
group->vin[i]->is_csi = false;
ret = 0;
goto out;
@@ -440,20 +440,20 @@ static int rvin_parallel_subdevice_attach(struct rvin_dev *vin,
ret = rvin_find_pad(subdev, MEDIA_PAD_FL_SOURCE);
if (ret < 0)
return ret;
- vin->parallel->source_pad = ret;
+ vin->parallel.source_pad = ret;
ret = rvin_find_pad(subdev, MEDIA_PAD_FL_SINK);
- vin->parallel->sink_pad = ret < 0 ? 0 : ret;
+ vin->parallel.sink_pad = ret < 0 ? 0 : ret;
if (vin->info->use_mc) {
- vin->parallel->subdev = subdev;
+ vin->parallel.subdev = subdev;
return 0;
}
/* Find compatible subdevices mbus format */
vin->mbus_code = 0;
code.index = 0;
- code.pad = vin->parallel->source_pad;
+ code.pad = vin->parallel.source_pad;
while (!vin->mbus_code &&
!v4l2_subdev_call(subdev, pad, enum_mbus_code, NULL, &code)) {
code.index++;
@@ -512,7 +512,7 @@ static int rvin_parallel_subdevice_attach(struct rvin_dev *vin,
vin->vdev.ctrl_handler = &vin->ctrl_handler;
- vin->parallel->subdev = subdev;
+ vin->parallel.subdev = subdev;
return 0;
}
@@ -520,7 +520,7 @@ static int rvin_parallel_subdevice_attach(struct rvin_dev *vin,
static void rvin_parallel_subdevice_detach(struct rvin_dev *vin)
{
rvin_v4l2_unregister(vin);
- vin->parallel->subdev = NULL;
+ vin->parallel.subdev = NULL;
if (!vin->info->use_mc) {
v4l2_ctrl_handler_free(&vin->ctrl_handler);
@@ -551,11 +551,11 @@ static int rvin_parallel_notify_complete(struct v4l2_async_notifier *notifier)
return 0;
/* If we're running with media-controller, link the subdevs. */
- source = &vin->parallel->subdev->entity;
+ source = &vin->parallel.subdev->entity;
sink = &vin->vdev.entity;
- ret = media_create_pad_link(source, vin->parallel->source_pad,
- sink, vin->parallel->sink_pad, 0);
+ ret = media_create_pad_link(source, vin->parallel.source_pad,
+ sink, vin->parallel.sink_pad, 0);
if (ret)
vin_err(vin, "Error adding link from %s to %s: %d\n",
source->name, sink->name, ret);
@@ -592,8 +592,8 @@ static int rvin_parallel_notify_bound(struct v4l2_async_notifier *notifier,
v4l2_set_subdev_hostdata(subdev, vin);
vin_dbg(vin, "bound subdev %s source pad: %u sink pad: %u\n",
- subdev->name, vin->parallel->source_pad,
- vin->parallel->sink_pad);
+ subdev->name, vin->parallel.source_pad,
+ vin->parallel.sink_pad);
return 0;
}
@@ -604,33 +604,56 @@ static const struct v4l2_async_notifier_operations rvin_parallel_notify_ops = {
.complete = rvin_parallel_notify_complete,
};
-static int rvin_parallel_parse_v4l2(struct device *dev,
- struct v4l2_fwnode_endpoint *vep,
- struct v4l2_async_subdev *asd)
+static int rvin_parallel_parse_of(struct rvin_dev *vin)
{
- struct rvin_dev *vin = dev_get_drvdata(dev);
- struct rvin_parallel_entity *rvpe =
- container_of(asd, struct rvin_parallel_entity, asd);
+ struct fwnode_handle *ep, *fwnode;
+ struct v4l2_fwnode_endpoint vep = {
+ .bus_type = V4L2_MBUS_UNKNOWN,
+ };
+ struct v4l2_async_subdev *asd;
+ int ret;
- if (vep->base.port || vep->base.id)
- return -ENOTCONN;
+ ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(vin->dev), 0, 0, 0);
+ if (!ep)
+ return 0;
- vin->parallel = rvpe;
- vin->parallel->mbus_type = vep->bus_type;
+ fwnode = fwnode_graph_get_remote_endpoint(ep);
+ ret = v4l2_fwnode_endpoint_parse(ep, &vep);
+ fwnode_handle_put(ep);
+ if (ret) {
+ vin_err(vin, "Failed to parse %pOF\n", to_of_node(fwnode));
+ ret = -EINVAL;
+ goto out;
+ }
- switch (vin->parallel->mbus_type) {
+ switch (vep.bus_type) {
case V4L2_MBUS_PARALLEL:
case V4L2_MBUS_BT656:
vin_dbg(vin, "Found %s media bus\n",
- vin->parallel->mbus_type == V4L2_MBUS_PARALLEL ?
+ vep.bus_type == V4L2_MBUS_PARALLEL ?
"PARALLEL" : "BT656");
- vin->parallel->bus = vep->bus.parallel;
+ vin->parallel.mbus_type = vep.bus_type;
+ vin->parallel.bus = vep.bus.parallel;
break;
default:
vin_err(vin, "Unknown media bus type\n");
- return -EINVAL;
+ ret = -EINVAL;
+ goto out;
+ }
+
+ asd = v4l2_async_notifier_add_fwnode_subdev(&vin->notifier, fwnode,
+ sizeof(*asd));
+ if (IS_ERR(asd)) {
+ ret = PTR_ERR(asd);
+ goto out;
}
+ vin->parallel.asd = asd;
+
+ vin_dbg(vin, "Add parallel OF device %pOF\n", to_of_node(fwnode));
+out:
+ fwnode_handle_put(fwnode);
+
return 0;
}
@@ -640,18 +663,16 @@ static int rvin_parallel_init(struct rvin_dev *vin)
v4l2_async_notifier_init(&vin->notifier);
- ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
- vin->dev, &vin->notifier, sizeof(struct rvin_parallel_entity),
- 0, rvin_parallel_parse_v4l2);
+ ret = rvin_parallel_parse_of(vin);
if (ret)
return ret;
/* If using mc, it's fine not to have any input registered. */
- if (!vin->parallel)
+ if (!vin->parallel.asd)
return vin->info->use_mc ? 0 : -ENODEV;
vin_dbg(vin, "Found parallel subdevice %pOF\n",
- to_of_node(vin->parallel->asd.match.fwnode));
+ to_of_node(vin->parallel.asd->match.fwnode));
vin->notifier.ops = &rvin_parallel_notify_ops;
ret = v4l2_async_notifier_register(&vin->v4l2_dev, &vin->notifier);
@@ -751,7 +772,7 @@ static void rvin_group_notify_unbind(struct v4l2_async_notifier *notifier,
mutex_lock(&vin->group->lock);
for (i = 0; i < RVIN_CSI_MAX; i++) {
- if (vin->group->csi[i].fwnode != asd->match.fwnode)
+ if (vin->group->csi[i].asd != asd)
continue;
vin->group->csi[i].subdev = NULL;
vin_dbg(vin, "Unbind CSI-2 %s from slot %u\n", subdev->name, i);
@@ -773,7 +794,7 @@ static int rvin_group_notify_bound(struct v4l2_async_notifier *notifier,
mutex_lock(&vin->group->lock);
for (i = 0; i < RVIN_CSI_MAX; i++) {
- if (vin->group->csi[i].fwnode != asd->match.fwnode)
+ if (vin->group->csi[i].asd != asd)
continue;
vin->group->csi[i].subdev = subdev;
vin_dbg(vin, "Bound CSI-2 %s to slot %u\n", subdev->name, i);
@@ -791,37 +812,48 @@ static const struct v4l2_async_notifier_operations rvin_group_notify_ops = {
.complete = rvin_group_notify_complete,
};
-static int rvin_mc_parse_of_endpoint(struct device *dev,
- struct v4l2_fwnode_endpoint *vep,
- struct v4l2_async_subdev *asd)
+static int rvin_mc_parse_of(struct rvin_dev *vin, unsigned int id)
{
- struct rvin_dev *vin = dev_get_drvdata(dev);
- int ret = 0;
+ struct fwnode_handle *ep, *fwnode;
+ struct v4l2_fwnode_endpoint vep = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY,
+ };
+ struct v4l2_async_subdev *asd;
+ int ret;
- if (vep->base.port != 1 || vep->base.id >= RVIN_CSI_MAX)
- return -EINVAL;
+ ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(vin->dev), 1, id, 0);
+ if (!ep)
+ return 0;
- if (!of_device_is_available(to_of_node(asd->match.fwnode))) {
- vin_dbg(vin, "OF device %pOF disabled, ignoring\n",
- to_of_node(asd->match.fwnode));
- return -ENOTCONN;
+ fwnode = fwnode_graph_get_remote_endpoint(ep);
+ ret = v4l2_fwnode_endpoint_parse(ep, &vep);
+ fwnode_handle_put(ep);
+ if (ret) {
+ vin_err(vin, "Failed to parse %pOF\n", to_of_node(fwnode));
+ ret = -EINVAL;
+ goto out;
}
- mutex_lock(&vin->group->lock);
-
- if (vin->group->csi[vep->base.id].fwnode) {
- vin_dbg(vin, "OF device %pOF already handled\n",
- to_of_node(asd->match.fwnode));
+ if (!of_device_is_available(to_of_node(fwnode))) {
+ vin_dbg(vin, "OF device %pOF disabled, ignoring\n",
+ to_of_node(fwnode));
ret = -ENOTCONN;
goto out;
}
- vin->group->csi[vep->base.id].fwnode = asd->match.fwnode;
+ asd = v4l2_async_notifier_add_fwnode_subdev(&vin->group->notifier,
+ fwnode, sizeof(*asd));
+ if (IS_ERR(asd)) {
+ ret = PTR_ERR(asd);
+ goto out;
+ }
+
+ vin->group->csi[vep.base.id].asd = asd;
vin_dbg(vin, "Add group OF device %pOF to slot %u\n",
- to_of_node(asd->match.fwnode), vep->base.id);
+ to_of_node(fwnode), vep.base.id);
out:
- mutex_unlock(&vin->group->lock);
+ fwnode_handle_put(fwnode);
return ret;
}
@@ -829,7 +861,7 @@ out:
static int rvin_mc_parse_of_graph(struct rvin_dev *vin)
{
unsigned int count = 0, vin_mask = 0;
- unsigned int i;
+ unsigned int i, id;
int ret;
mutex_lock(&vin->group->lock);
@@ -860,12 +892,14 @@ static int rvin_mc_parse_of_graph(struct rvin_dev *vin)
if (!(vin_mask & BIT(i)))
continue;
- ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
- vin->group->vin[i]->dev, &vin->group->notifier,
- sizeof(struct v4l2_async_subdev), 1,
- rvin_mc_parse_of_endpoint);
- if (ret)
- return ret;
+ for (id = 0; id < RVIN_CSI_MAX; id++) {
+ if (vin->group->csi[id].asd)
+ continue;
+
+ ret = rvin_mc_parse_of(vin->group->vin[i], id);
+ if (ret)
+ return ret;
+ }
}
if (list_empty(&vin->group->notifier.asd_list))
@@ -919,6 +953,54 @@ static int rvin_mc_init(struct rvin_dev *vin)
}
/* -----------------------------------------------------------------------------
+ * Suspend / Resume
+ */
+
+static int __maybe_unused rvin_suspend(struct device *dev)
+{
+ struct rvin_dev *vin = dev_get_drvdata(dev);
+
+ if (vin->state != RUNNING)
+ return 0;
+
+ rvin_stop_streaming(vin);
+
+ vin->state = SUSPENDED;
+
+ return 0;
+}
+
+static int __maybe_unused rvin_resume(struct device *dev)
+{
+ struct rvin_dev *vin = dev_get_drvdata(dev);
+
+ if (vin->state != SUSPENDED)
+ return 0;
+
+ /*
+ * Restore group master CHSEL setting.
+ *
+ * This needs to be done by every VIN resuming not only the master
+ * as we don't know if and in which order the master VINs will
+ * be resumed.
+ */
+ if (vin->info->use_mc) {
+ unsigned int master_id = rvin_group_id_to_master(vin->id);
+ struct rvin_dev *master = vin->group->vin[master_id];
+ int ret;
+
+ if (WARN_ON(!master))
+ return -ENODEV;
+
+ ret = rvin_set_channel_routing(master, master->chsel);
+ if (ret)
+ return ret;
+ }
+
+ return rvin_start_streaming(vin);
+}
+
+/* -----------------------------------------------------------------------------
* Platform Device Driver
*/
@@ -1268,22 +1350,6 @@ static const struct of_device_id rvin_of_id_table[] = {
.data = &rcar_info_h1,
},
{
- .compatible = "renesas,vin-r8a7790",
- .data = &rcar_info_gen2,
- },
- {
- .compatible = "renesas,vin-r8a7791",
- .data = &rcar_info_gen2,
- },
- {
- .compatible = "renesas,vin-r8a7793",
- .data = &rcar_info_gen2,
- },
- {
- .compatible = "renesas,vin-r8a7794",
- .data = &rcar_info_gen2,
- },
- {
.compatible = "renesas,rcar-gen2-vin",
.data = &rcar_info_gen2,
},
@@ -1421,9 +1487,12 @@ static int rcar_vin_remove(struct platform_device *pdev)
return 0;
}
+static SIMPLE_DEV_PM_OPS(rvin_pm_ops, rvin_suspend, rvin_resume);
+
static struct platform_driver rcar_vin_driver = {
.driver = {
.name = "rcar-vin",
+ .pm = &rvin_pm_ops,
.of_match_table = rvin_of_id_table,
},
.probe = rcar_vin_probe,
diff --git a/drivers/media/platform/rcar-vin/rcar-csi2.c b/drivers/media/platform/rcar-vin/rcar-csi2.c
index 79f229756805..945d2eb87233 100644
--- a/drivers/media/platform/rcar-vin/rcar-csi2.c
+++ b/drivers/media/platform/rcar-vin/rcar-csi2.c
@@ -876,31 +876,33 @@ static int rcsi2_parse_dt(struct rcar_csi2 *priv)
{
struct v4l2_async_subdev *asd;
struct fwnode_handle *fwnode;
- struct device_node *ep;
- struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 };
+ struct fwnode_handle *ep;
+ struct v4l2_fwnode_endpoint v4l2_ep = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY
+ };
int ret;
- ep = of_graph_get_endpoint_by_regs(priv->dev->of_node, 0, 0);
+ ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0);
if (!ep) {
dev_err(priv->dev, "Not connected to subdevice\n");
return -EINVAL;
}
- ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &v4l2_ep);
+ ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
if (ret) {
dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
- of_node_put(ep);
+ fwnode_handle_put(ep);
return -EINVAL;
}
ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
if (ret) {
- of_node_put(ep);
+ fwnode_handle_put(ep);
return ret;
}
- fwnode = fwnode_graph_get_remote_endpoint(of_fwnode_handle(ep));
- of_node_put(ep);
+ fwnode = fwnode_graph_get_remote_endpoint(ep);
+ fwnode_handle_put(ep);
dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode));
diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c
index 692dea300b0d..48280ddb15b9 100644
--- a/drivers/media/platform/rcar-vin/rcar-dma.c
+++ b/drivers/media/platform/rcar-vin/rcar-dma.c
@@ -133,7 +133,6 @@
#define VNCSI_IFMD_DES1 (1 << 26)
#define VNCSI_IFMD_DES0 (1 << 25)
#define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
-#define VNCSI_IFMD_CSI_CHSEL_MASK 0xf
struct rvin_buffer {
struct vb2_v4l2_buffer vb;
@@ -672,7 +671,7 @@ static int rvin_setup(struct rvin_dev *vin)
case MEDIA_BUS_FMT_UYVY8_2X8:
/* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
if (!vin->is_csi &&
- vin->parallel->mbus_type == V4L2_MBUS_BT656)
+ vin->parallel.mbus_type == V4L2_MBUS_BT656)
vnmc |= VNMC_INF_YUV8_BT656;
else
vnmc |= VNMC_INF_YUV8_BT601;
@@ -685,7 +684,7 @@ static int rvin_setup(struct rvin_dev *vin)
case MEDIA_BUS_FMT_UYVY10_2X10:
/* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
if (!vin->is_csi &&
- vin->parallel->mbus_type == V4L2_MBUS_BT656)
+ vin->parallel.mbus_type == V4L2_MBUS_BT656)
vnmc |= VNMC_INF_YUV10_BT656;
else
vnmc |= VNMC_INF_YUV10_BT601;
@@ -710,21 +709,21 @@ static int rvin_setup(struct rvin_dev *vin)
if (!vin->is_csi) {
/* Hsync Signal Polarity Select */
- if (!(vin->parallel->bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
+ if (!(vin->parallel.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
dmr2 |= VNDMR2_HPS;
/* Vsync Signal Polarity Select */
- if (!(vin->parallel->bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
+ if (!(vin->parallel.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
dmr2 |= VNDMR2_VPS;
/* Data Enable Polarity Select */
- if (vin->parallel->bus.flags & V4L2_MBUS_DATA_ENABLE_LOW)
+ if (vin->parallel.bus.flags & V4L2_MBUS_DATA_ENABLE_LOW)
dmr2 |= VNDMR2_CES;
switch (vin->mbus_code) {
case MEDIA_BUS_FMT_UYVY8_2X8:
- if (vin->parallel->bus.bus_width == 8 &&
- vin->parallel->bus.data_shift == 8)
+ if (vin->parallel.bus.bus_width == 8 &&
+ vin->parallel.bus.data_shift == 8)
dmr2 |= VNDMR2_YDS;
break;
default:
@@ -905,7 +904,7 @@ static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
vin->format.sizeimage / 2;
break;
}
- } else if (list_empty(&vin->buf_list)) {
+ } else if (vin->state != RUNNING || list_empty(&vin->buf_list)) {
vin->buf_hw[slot].buffer = NULL;
vin->buf_hw[slot].type = FULL;
phys_addr = vin->scratch_phys;
@@ -998,12 +997,6 @@ static irqreturn_t rvin_irq(int irq, void *data)
goto done;
}
- /* Nothing to do if capture status is 'STOPPING' */
- if (vin->state == STOPPING) {
- vin_dbg(vin, "IRQ while state stopping\n");
- goto done;
- }
-
/* Prepare for capture and update state */
vnms = rvin_read(vin, VNMS_REG);
slot = (vnms & VNMS_FBS_MASK) >> VNMS_FBS_SHIFT;
@@ -1056,33 +1049,20 @@ done:
return IRQ_RETVAL(handled);
}
-/* Need to hold qlock before calling */
-static void return_all_buffers(struct rvin_dev *vin,
- enum vb2_buffer_state state)
+static void return_unused_buffers(struct rvin_dev *vin,
+ enum vb2_buffer_state state)
{
struct rvin_buffer *buf, *node;
- struct vb2_v4l2_buffer *freed[HW_BUFFER_NUM];
- unsigned int i, n;
-
- for (i = 0; i < HW_BUFFER_NUM; i++) {
- freed[i] = vin->buf_hw[i].buffer;
- vin->buf_hw[i].buffer = NULL;
-
- for (n = 0; n < i; n++) {
- if (freed[i] == freed[n]) {
- freed[i] = NULL;
- break;
- }
- }
+ unsigned long flags;
- if (freed[i])
- vb2_buffer_done(&freed[i]->vb2_buf, state);
- }
+ spin_lock_irqsave(&vin->qlock, flags);
list_for_each_entry_safe(buf, node, &vin->buf_list, list) {
vb2_buffer_done(&buf->vb.vb2_buf, state);
list_del(&buf->list);
}
+
+ spin_unlock_irqrestore(&vin->qlock, flags);
}
static int rvin_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
@@ -1222,7 +1202,7 @@ static int rvin_set_stream(struct rvin_dev *vin, int on)
/* No media controller used, simply pass operation to subdevice. */
if (!vin->info->use_mc) {
- ret = v4l2_subdev_call(vin->parallel->subdev, video, s_stream,
+ ret = v4l2_subdev_call(vin->parallel.subdev, video, s_stream,
on);
return ret == -ENOIOCTLCMD ? 0 : ret;
@@ -1266,61 +1246,81 @@ static int rvin_set_stream(struct rvin_dev *vin, int on)
return ret;
}
-static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
+int rvin_start_streaming(struct rvin_dev *vin)
{
- struct rvin_dev *vin = vb2_get_drv_priv(vq);
unsigned long flags;
int ret;
- /* Allocate scratch buffer. */
- vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,
- &vin->scratch_phys, GFP_KERNEL);
- if (!vin->scratch) {
- spin_lock_irqsave(&vin->qlock, flags);
- return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
- spin_unlock_irqrestore(&vin->qlock, flags);
- vin_err(vin, "Failed to allocate scratch buffer\n");
- return -ENOMEM;
- }
-
ret = rvin_set_stream(vin, 1);
- if (ret) {
- spin_lock_irqsave(&vin->qlock, flags);
- return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
- spin_unlock_irqrestore(&vin->qlock, flags);
- goto out;
- }
+ if (ret)
+ return ret;
spin_lock_irqsave(&vin->qlock, flags);
vin->sequence = 0;
ret = rvin_capture_start(vin);
- if (ret) {
- return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
+ if (ret)
rvin_set_stream(vin, 0);
- }
spin_unlock_irqrestore(&vin->qlock, flags);
-out:
- if (ret)
- dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
- vin->scratch_phys);
return ret;
}
-static void rvin_stop_streaming(struct vb2_queue *vq)
+static int rvin_start_streaming_vq(struct vb2_queue *vq, unsigned int count)
{
struct rvin_dev *vin = vb2_get_drv_priv(vq);
+ int ret = -ENOMEM;
+
+ /* Allocate scratch buffer. */
+ vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,
+ &vin->scratch_phys, GFP_KERNEL);
+ if (!vin->scratch)
+ goto err_scratch;
+
+ ret = rvin_start_streaming(vin);
+ if (ret)
+ goto err_start;
+
+ return 0;
+err_start:
+ dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
+ vin->scratch_phys);
+err_scratch:
+ return_unused_buffers(vin, VB2_BUF_STATE_QUEUED);
+
+ return ret;
+}
+
+void rvin_stop_streaming(struct rvin_dev *vin)
+{
+ unsigned int i, retries;
unsigned long flags;
- int retries = 0;
+ bool buffersFreed;
spin_lock_irqsave(&vin->qlock, flags);
vin->state = STOPPING;
+ /* Wait until only scratch buffer is used, max 3 interrupts. */
+ retries = 0;
+ while (retries++ < RVIN_RETRIES) {
+ buffersFreed = true;
+ for (i = 0; i < HW_BUFFER_NUM; i++)
+ if (vin->buf_hw[i].buffer)
+ buffersFreed = false;
+
+ if (buffersFreed)
+ break;
+
+ spin_unlock_irqrestore(&vin->qlock, flags);
+ msleep(RVIN_TIMEOUT_MS);
+ spin_lock_irqsave(&vin->qlock, flags);
+ }
+
/* Wait for streaming to stop */
+ retries = 0;
while (retries++ < RVIN_RETRIES) {
rvin_capture_stop(vin);
@@ -1336,7 +1336,7 @@ static void rvin_stop_streaming(struct vb2_queue *vq)
spin_lock_irqsave(&vin->qlock, flags);
}
- if (vin->state != STOPPED) {
+ if (!buffersFreed || vin->state != STOPPED) {
/*
* If this happens something have gone horribly wrong.
* Set state to stopped to prevent the interrupt handler
@@ -1346,27 +1346,33 @@ static void rvin_stop_streaming(struct vb2_queue *vq)
vin->state = STOPPED;
}
- /* Release all active buffers */
- return_all_buffers(vin, VB2_BUF_STATE_ERROR);
-
spin_unlock_irqrestore(&vin->qlock, flags);
rvin_set_stream(vin, 0);
/* disable interrupts */
rvin_disable_interrupts(vin);
+}
+
+static void rvin_stop_streaming_vq(struct vb2_queue *vq)
+{
+ struct rvin_dev *vin = vb2_get_drv_priv(vq);
+
+ rvin_stop_streaming(vin);
/* Free scratch buffer. */
dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
vin->scratch_phys);
+
+ return_unused_buffers(vin, VB2_BUF_STATE_ERROR);
}
static const struct vb2_ops rvin_qops = {
.queue_setup = rvin_queue_setup,
.buf_prepare = rvin_buffer_prepare,
.buf_queue = rvin_buffer_queue,
- .start_streaming = rvin_start_streaming,
- .stop_streaming = rvin_stop_streaming,
+ .start_streaming = rvin_start_streaming_vq,
+ .stop_streaming = rvin_stop_streaming_vq,
.wait_prepare = vb2_ops_wait_prepare,
.wait_finish = vb2_ops_wait_finish,
};
@@ -1442,7 +1448,9 @@ error:
*/
int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
{
- u32 ifmd, vnmc;
+ const struct rvin_group_route *route;
+ u32 ifmd = 0;
+ u32 vnmc;
int ret;
ret = pm_runtime_get_sync(vin->dev);
@@ -1455,12 +1463,31 @@ int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
vnmc = rvin_read(vin, VNMC_REG);
rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG);
- ifmd = VNCSI_IFMD_DES1 | VNCSI_IFMD_DES0 | VNCSI_IFMD_CSI_CHSEL(chsel);
+ /*
+ * Set data expansion mode to "pad with 0s" by inspecting the routes
+ * table to find out which bit fields are available in the IFMD
+ * register. IFMD_DES1 controls data expansion mode for CSI20/21,
+ * IFMD_DES0 controls data expansion mode for CSI40/41.
+ */
+ for (route = vin->info->routes; route->mask; route++) {
+ if (route->csi == RVIN_CSI20 || route->csi == RVIN_CSI21)
+ ifmd |= VNCSI_IFMD_DES1;
+ else
+ ifmd |= VNCSI_IFMD_DES0;
+
+ if (ifmd == (VNCSI_IFMD_DES0 | VNCSI_IFMD_DES1))
+ break;
+ }
- rvin_write(vin, ifmd, VNCSI_IFMD_REG);
+ if (ifmd) {
+ ifmd |= VNCSI_IFMD_CSI_CHSEL(chsel);
+ rvin_write(vin, ifmd, VNCSI_IFMD_REG);
+ }
vin_dbg(vin, "Set IFMD 0x%x\n", ifmd);
+ vin->chsel = chsel;
+
/* Restore VNMC. */
rvin_write(vin, vnmc, VNMC_REG);
diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c
index 3e7a3ae2a6b9..e6ea2b7991b8 100644
--- a/drivers/media/platform/rcar-vin/rcar-v4l2.c
+++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c
@@ -205,7 +205,7 @@ static int rvin_reset_format(struct rvin_dev *vin)
{
struct v4l2_subdev_format fmt = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
- .pad = vin->parallel->source_pad,
+ .pad = vin->parallel.source_pad,
};
int ret;
@@ -246,7 +246,7 @@ static int rvin_try_format(struct rvin_dev *vin, u32 which,
struct v4l2_subdev_pad_config *pad_cfg;
struct v4l2_subdev_format format = {
.which = which,
- .pad = vin->parallel->source_pad,
+ .pad = vin->parallel.source_pad,
};
enum v4l2_field field;
u32 width, height;
@@ -632,7 +632,7 @@ static int rvin_enum_dv_timings(struct file *file, void *priv_fh,
if (timings->pad)
return -EINVAL;
- timings->pad = vin->parallel->sink_pad;
+ timings->pad = vin->parallel.sink_pad;
ret = v4l2_subdev_call(sd, pad, enum_dv_timings, timings);
@@ -684,7 +684,7 @@ static int rvin_dv_timings_cap(struct file *file, void *priv_fh,
if (cap->pad)
return -EINVAL;
- cap->pad = vin->parallel->sink_pad;
+ cap->pad = vin->parallel.sink_pad;
ret = v4l2_subdev_call(sd, pad, dv_timings_cap, cap);
@@ -702,7 +702,7 @@ static int rvin_g_edid(struct file *file, void *fh, struct v4l2_edid *edid)
if (edid->pad)
return -EINVAL;
- edid->pad = vin->parallel->sink_pad;
+ edid->pad = vin->parallel.sink_pad;
ret = v4l2_subdev_call(sd, pad, get_edid, edid);
@@ -720,7 +720,7 @@ static int rvin_s_edid(struct file *file, void *fh, struct v4l2_edid *edid)
if (edid->pad)
return -EINVAL;
- edid->pad = vin->parallel->sink_pad;
+ edid->pad = vin->parallel.sink_pad;
ret = v4l2_subdev_call(sd, pad, set_edid, edid);
diff --git a/drivers/media/platform/rcar-vin/rcar-vin.h b/drivers/media/platform/rcar-vin/rcar-vin.h
index 8396e0e45478..0ee9d402f5ac 100644
--- a/drivers/media/platform/rcar-vin/rcar-vin.h
+++ b/drivers/media/platform/rcar-vin/rcar-vin.h
@@ -49,16 +49,18 @@ enum rvin_csi_id {
};
/**
- * STOPPED - No operation in progress
- * STARTING - Capture starting up
- * RUNNING - Operation in progress have buffers
- * STOPPING - Stopping operation
+ * STOPPED - No operation in progress
+ * STARTING - Capture starting up
+ * RUNNING - Operation in progress have buffers
+ * STOPPING - Stopping operation
+ * SUSPENDED - Capture is suspended
*/
enum rvin_dma_state {
STOPPED = 0,
STARTING,
RUNNING,
STOPPING,
+ SUSPENDED,
};
/**
@@ -99,7 +101,7 @@ struct rvin_video_format {
*
*/
struct rvin_parallel_entity {
- struct v4l2_async_subdev asd;
+ struct v4l2_async_subdev *asd;
struct v4l2_subdev *subdev;
enum v4l2_mbus_type mbus_type;
@@ -189,6 +191,7 @@ struct rvin_info {
* @state: keeps track of operation state
*
* @is_csi: flag to mark the VIN as using a CSI-2 subdevice
+ * @chsel Cached value of the current CSI-2 channel selection
*
* @mbus_code: media bus format code
* @format: active V4L2 pixel format
@@ -210,7 +213,7 @@ struct rvin_dev {
struct v4l2_ctrl_handler ctrl_handler;
struct v4l2_async_notifier notifier;
- struct rvin_parallel_entity *parallel;
+ struct rvin_parallel_entity parallel;
struct rvin_group *group;
unsigned int id;
@@ -232,6 +235,7 @@ struct rvin_dev {
enum rvin_dma_state state;
bool is_csi;
+ unsigned int chsel;
u32 mbus_code;
struct v4l2_pix_format format;
@@ -244,7 +248,7 @@ struct rvin_dev {
unsigned int alpha;
};
-#define vin_to_source(vin) ((vin)->parallel->subdev)
+#define vin_to_source(vin) ((vin)->parallel.subdev)
/* Debug */
#define vin_dbg(d, fmt, arg...) dev_dbg(d->dev, fmt, ##arg)
@@ -276,7 +280,7 @@ struct rvin_group {
struct rvin_dev *vin[RCAR_VIN_NUM];
struct {
- struct fwnode_handle *fwnode;
+ struct v4l2_async_subdev *asd;
struct v4l2_subdev *subdev;
} csi[RVIN_CSI_MAX];
};
@@ -297,4 +301,7 @@ void rvin_crop_scale_comp(struct rvin_dev *vin);
int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel);
void rvin_set_alpha(struct rvin_dev *vin, unsigned int alpha);
+int rvin_start_streaming(struct rvin_dev *vin);
+void rvin_stop_streaming(struct rvin_dev *vin);
+
#endif
diff --git a/drivers/media/platform/rockchip/rkisp1/Makefile b/drivers/media/platform/rockchip/rkisp1/Makefile
new file mode 100644
index 000000000000..ab32a77db8f7
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += rockchip-isp1.o
+rockchip-isp1-objs += rkisp1-capture.o \
+ rkisp1-common.o \
+ rkisp1-dev.o \
+ rkisp1-isp.o \
+ rkisp1-resizer.o \
+ rkisp1-stats.o \
+ rkisp1-params.o
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
new file mode 100644
index 000000000000..5f6c9d1623e4
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
@@ -0,0 +1,1431 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Rockchip ISP1 Driver - V4l capture device
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ *
+ * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-fh.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mc.h>
+#include <media/v4l2-subdev.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "rkisp1-common.h"
+
+/*
+ * NOTE: There are two capture video devices in rkisp1, selfpath and mainpath.
+ *
+ * differences between selfpath and mainpath
+ * available mp sink input: isp
+ * available sp sink input : isp, dma(TODO)
+ * available mp sink pad fmts: yuv422, raw
+ * available sp sink pad fmts: yuv422, yuv420......
+ * available mp source fmts: yuv, raw, jpeg(TODO)
+ * available sp source fmts: yuv, rgb
+ */
+
+#define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath"
+#define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath"
+
+#define RKISP1_MIN_BUFFERS_NEEDED 3
+
+enum rkisp1_plane {
+ RKISP1_PLANE_Y = 0,
+ RKISP1_PLANE_CB = 1,
+ RKISP1_PLANE_CR = 2
+};
+
+/*
+ * @fourcc: pixel format
+ * @fmt_type: helper filed for pixel format
+ * @uv_swap: if cb cr swapped, for yuv
+ * @write_format: defines how YCbCr self picture data is written to memory
+ * @output_format: defines sp output format
+ * @mbus: the mbus code on the src resizer pad that matches the pixel format
+ */
+struct rkisp1_capture_fmt_cfg {
+ u32 fourcc;
+ u8 uv_swap;
+ u32 write_format;
+ u32 output_format;
+ u32 mbus;
+};
+
+struct rkisp1_capture_ops {
+ void (*config)(struct rkisp1_capture *cap);
+ void (*stop)(struct rkisp1_capture *cap);
+ void (*enable)(struct rkisp1_capture *cap);
+ void (*disable)(struct rkisp1_capture *cap);
+ void (*set_data_path)(struct rkisp1_capture *cap);
+ bool (*is_stopped)(struct rkisp1_capture *cap);
+};
+
+struct rkisp1_capture_config {
+ const struct rkisp1_capture_fmt_cfg *fmts;
+ int fmt_size;
+ struct {
+ u32 y_size_init;
+ u32 cb_size_init;
+ u32 cr_size_init;
+ u32 y_base_ad_init;
+ u32 cb_base_ad_init;
+ u32 cr_base_ad_init;
+ u32 y_offs_cnt_init;
+ u32 cb_offs_cnt_init;
+ u32 cr_offs_cnt_init;
+ } mi;
+};
+
+/*
+ * The supported pixel formats for mainpath. NOTE, pixel formats with identical 'mbus'
+ * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes
+ */
+static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
+ /* yuv422 */
+ {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUV422P,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV61,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVU422M,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* yuv400 */
+ {
+ .fourcc = V4L2_PIX_FMT_GREY,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* yuv420 */
+ {
+ .fourcc = V4L2_PIX_FMT_NV21,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV21M,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUV420,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVU420,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ },
+ /* raw */
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB8,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGBRG8,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SBGGR8,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
+ .mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SRGGB10,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGRBG10,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGBRG10,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SBGGR10,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SRGGB12,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGRBG12,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGBRG12,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SBGGR12,
+ .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
+ .mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
+ },
+};
+
+/*
+ * The supported pixel formats for selfpath. NOTE, pixel formats with identical 'mbus'
+ * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes
+ */
+static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = {
+ /* yuv422 */
+ {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUV422P,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV61,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVU422M,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* yuv400 */
+ {
+ .fourcc = V4L2_PIX_FMT_GREY,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV400,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* rgb */
+ {
+ .fourcc = V4L2_PIX_FMT_XBGR32,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_RGB565,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565,
+ .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
+ },
+ /* yuv420 */
+ {
+ .fourcc = V4L2_PIX_FMT_NV21,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV21M,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YUV420,
+ .uv_swap = 0,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ }, {
+ .fourcc = V4L2_PIX_FMT_YVU420,
+ .uv_swap = 1,
+ .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
+ .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
+ .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
+ },
+};
+
+static const struct rkisp1_capture_config rkisp1_capture_config_mp = {
+ .fmts = rkisp1_mp_fmts,
+ .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts),
+ .mi = {
+ .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT,
+ .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT,
+ .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT,
+ .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT,
+ .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT,
+ .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT,
+ .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT,
+ .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT,
+ .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT,
+ },
+};
+
+static const struct rkisp1_capture_config rkisp1_capture_config_sp = {
+ .fmts = rkisp1_sp_fmts,
+ .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts),
+ .mi = {
+ .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT,
+ .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT,
+ .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT,
+ .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT,
+ .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT,
+ .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT,
+ .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT,
+ .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT,
+ .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT,
+ },
+};
+
+static inline struct rkisp1_vdev_node *
+rkisp1_vdev_to_node(struct video_device *vdev)
+{
+ return container_of(vdev, struct rkisp1_vdev_node, vdev);
+}
+
+int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ const struct rkisp1_capture_fmt_cfg *fmts = cap->config->fmts;
+ /*
+ * initialize curr_mbus to non existing mbus code 0 to ensure it is
+ * different from fmts[0].mbus
+ */
+ u32 curr_mbus = 0;
+ int i, n = 0;
+
+ for (i = 0; i < cap->config->fmt_size; i++) {
+ if (fmts[i].mbus == curr_mbus)
+ continue;
+
+ curr_mbus = fmts[i].mbus;
+ if (n++ == code->index) {
+ code->code = curr_mbus;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+/* ----------------------------------------------------------------------------
+ * Stream operations for self-picture path (sp) and main-picture path (mp)
+ */
+
+static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap)
+{
+ u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
+
+ mi_ctrl &= ~GENMASK(17, 16);
+ mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64;
+
+ mi_ctrl &= ~GENMASK(19, 18);
+ mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64;
+
+ mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN |
+ RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN;
+
+ rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
+}
+
+static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm,
+ unsigned int component)
+{
+ /*
+ * If packed format, then plane_fmt[0].sizeimage is the sum of all
+ * components, so we need to calculate just the size of Y component.
+ * See rkisp1_fill_pixfmt().
+ */
+ if (!component && pixm->num_planes == 1)
+ return pixm->plane_fmt[0].bytesperline * pixm->height;
+ return pixm->plane_fmt[component].sizeimage;
+}
+
+static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap)
+{
+ u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC);
+
+ mi_imsc |= RKISP1_CIF_MI_FRAME(cap);
+ rkisp1_write(cap->rkisp1, mi_imsc, RKISP1_CIF_MI_IMSC);
+}
+
+static void rkisp1_mp_config(struct rkisp1_capture *cap)
+{
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ struct rkisp1_device *rkisp1 = cap->rkisp1;
+ u32 reg;
+
+ rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
+ cap->config->mi.y_size_init);
+ rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
+ cap->config->mi.cb_size_init);
+ rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR),
+ cap->config->mi.cr_size_init);
+
+ rkisp1_irq_frame_end_enable(cap);
+
+ /* set uv swapping for semiplanar formats */
+ if (cap->pix.info->comp_planes == 2) {
+ reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
+ if (cap->pix.cfg->uv_swap)
+ reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
+ else
+ reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
+ rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
+ }
+
+ rkisp1_mi_config_ctrl(cap);
+
+ reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
+ reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK;
+ reg |= cap->pix.cfg->write_format;
+ rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL);
+
+ reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
+ reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE;
+ rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL);
+}
+
+static void rkisp1_sp_config(struct rkisp1_capture *cap)
+{
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ struct rkisp1_device *rkisp1 = cap->rkisp1;
+ u32 mi_ctrl, reg;
+
+ rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
+ cap->config->mi.y_size_init);
+ rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
+ cap->config->mi.cb_size_init);
+ rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR),
+ cap->config->mi.cr_size_init);
+
+ rkisp1_write(rkisp1, pixm->width, RKISP1_CIF_MI_SP_Y_PIC_WIDTH);
+ rkisp1_write(rkisp1, pixm->height, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT);
+ rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH);
+
+ rkisp1_irq_frame_end_enable(cap);
+
+ /* set uv swapping for semiplanar formats */
+ if (cap->pix.info->comp_planes == 2) {
+ reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
+ if (cap->pix.cfg->uv_swap)
+ reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
+ else
+ reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
+ rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
+ }
+
+ rkisp1_mi_config_ctrl(cap);
+
+ mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
+ mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK;
+ mi_ctrl |= cap->pix.cfg->write_format |
+ RKISP1_MI_CTRL_SP_INPUT_YUV422 |
+ cap->pix.cfg->output_format |
+ RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE;
+ rkisp1_write(rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
+}
+
+static void rkisp1_mp_disable(struct rkisp1_capture *cap)
+{
+ u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
+
+ mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE |
+ RKISP1_CIF_MI_CTRL_RAW_ENABLE);
+ rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
+}
+
+static void rkisp1_sp_disable(struct rkisp1_capture *cap)
+{
+ u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
+
+ mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE;
+ rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
+}
+
+static void rkisp1_mp_enable(struct rkisp1_capture *cap)
+{
+ u32 mi_ctrl;
+
+ rkisp1_mp_disable(cap);
+
+ mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
+ if (v4l2_is_format_bayer(cap->pix.info))
+ mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE;
+ /* YUV */
+ else
+ mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE;
+
+ rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
+}
+
+static void rkisp1_sp_enable(struct rkisp1_capture *cap)
+{
+ u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
+
+ mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE;
+ rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
+}
+
+static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap)
+{
+ if (!cap->is_streaming)
+ return;
+ rkisp1_write(cap->rkisp1,
+ RKISP1_CIF_MI_FRAME(cap), RKISP1_CIF_MI_ICR);
+ cap->ops->disable(cap);
+}
+
+static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap)
+{
+ u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED |
+ RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
+
+ return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en);
+}
+
+static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap)
+{
+ return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) &
+ RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED);
+}
+
+static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap)
+{
+ u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL);
+
+ dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP |
+ RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI;
+ rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
+}
+
+static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap)
+{
+ u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL);
+
+ dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP;
+ rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
+}
+
+static const struct rkisp1_capture_ops rkisp1_capture_ops_mp = {
+ .config = rkisp1_mp_config,
+ .enable = rkisp1_mp_enable,
+ .disable = rkisp1_mp_disable,
+ .stop = rkisp1_mp_sp_stop,
+ .set_data_path = rkisp1_mp_set_data_path,
+ .is_stopped = rkisp1_mp_is_stopped,
+};
+
+static const struct rkisp1_capture_ops rkisp1_capture_ops_sp = {
+ .config = rkisp1_sp_config,
+ .enable = rkisp1_sp_enable,
+ .disable = rkisp1_sp_disable,
+ .stop = rkisp1_mp_sp_stop,
+ .set_data_path = rkisp1_sp_set_data_path,
+ .is_stopped = rkisp1_sp_is_stopped,
+};
+
+/* ----------------------------------------------------------------------------
+ * Frame buffer operations
+ */
+
+static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap)
+{
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy;
+
+ dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
+ rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
+ rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
+
+ /* The driver never access vaddr, no mapping is required */
+ dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev,
+ dummy_buf->size,
+ &dummy_buf->dma_addr,
+ GFP_KERNEL,
+ DMA_ATTR_NO_KERNEL_MAPPING);
+ if (!dummy_buf->vaddr)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap)
+{
+ dma_free_attrs(cap->rkisp1->dev,
+ cap->buf.dummy.size, cap->buf.dummy.vaddr,
+ cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING);
+}
+
+static void rkisp1_set_next_buf(struct rkisp1_capture *cap)
+{
+ cap->buf.curr = cap->buf.next;
+ cap->buf.next = NULL;
+
+ if (!list_empty(&cap->buf.queue)) {
+ u32 *buff_addr;
+
+ cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue);
+ list_del(&cap->buf.next->queue);
+
+ buff_addr = cap->buf.next->buff_addr;
+
+ rkisp1_write(cap->rkisp1,
+ buff_addr[RKISP1_PLANE_Y],
+ cap->config->mi.y_base_ad_init);
+ rkisp1_write(cap->rkisp1,
+ buff_addr[RKISP1_PLANE_CB],
+ cap->config->mi.cb_base_ad_init);
+ rkisp1_write(cap->rkisp1,
+ buff_addr[RKISP1_PLANE_CR],
+ cap->config->mi.cr_base_ad_init);
+ } else {
+ /*
+ * Use the dummy space allocated by dma_alloc_coherent to
+ * throw data if there is no available buffer.
+ */
+ rkisp1_write(cap->rkisp1,
+ cap->buf.dummy.dma_addr,
+ cap->config->mi.y_base_ad_init);
+ rkisp1_write(cap->rkisp1,
+ cap->buf.dummy.dma_addr,
+ cap->config->mi.cb_base_ad_init);
+ rkisp1_write(cap->rkisp1,
+ cap->buf.dummy.dma_addr,
+ cap->config->mi.cr_base_ad_init);
+ }
+
+ /* Set plane offsets */
+ rkisp1_write(cap->rkisp1, 0, cap->config->mi.y_offs_cnt_init);
+ rkisp1_write(cap->rkisp1, 0, cap->config->mi.cb_offs_cnt_init);
+ rkisp1_write(cap->rkisp1, 0, cap->config->mi.cr_offs_cnt_init);
+}
+
+/*
+ * This function is called when a frame end comes. The next frame
+ * is processing and we should set up buffer for next-next frame,
+ * otherwise it will overflow.
+ */
+static void rkisp1_handle_buffer(struct rkisp1_capture *cap)
+{
+ struct rkisp1_isp *isp = &cap->rkisp1->isp;
+ struct rkisp1_buffer *curr_buf;
+
+ spin_lock(&cap->buf.lock);
+ curr_buf = cap->buf.curr;
+
+ if (curr_buf) {
+ curr_buf->vb.sequence = isp->frame_sequence;
+ curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns();
+ curr_buf->vb.field = V4L2_FIELD_NONE;
+ vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
+ } else {
+ cap->rkisp1->debug.frame_drop[cap->id]++;
+ }
+
+ rkisp1_set_next_buf(cap);
+ spin_unlock(&cap->buf.lock);
+}
+
+void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
+{
+ unsigned int i;
+ u32 status;
+
+ status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS);
+ rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR);
+
+ for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) {
+ struct rkisp1_capture *cap = &rkisp1->capture_devs[i];
+
+ if (!(status & RKISP1_CIF_MI_FRAME(cap)))
+ continue;
+ if (!cap->is_stopping) {
+ rkisp1_handle_buffer(cap);
+ continue;
+ }
+ /*
+ * Make sure stream is actually stopped, whose state
+ * can be read from the shadow register, before
+ * wake_up() thread which would immediately free all
+ * frame buffers. stop() takes effect at the next
+ * frame end that sync the configurations to shadow
+ * regs.
+ */
+ if (!cap->ops->is_stopped(cap)) {
+ cap->ops->stop(cap);
+ continue;
+ }
+ cap->is_stopping = false;
+ cap->is_streaming = false;
+ wake_up(&cap->done);
+ }
+}
+
+/* ----------------------------------------------------------------------------
+ * Vb2 operations
+ */
+
+static int rkisp1_vb2_queue_setup(struct vb2_queue *queue,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ struct rkisp1_capture *cap = queue->drv_priv;
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ unsigned int i;
+
+ if (*num_planes) {
+ if (*num_planes != pixm->num_planes)
+ return -EINVAL;
+
+ for (i = 0; i < pixm->num_planes; i++)
+ if (sizes[i] < pixm->plane_fmt[i].sizeimage)
+ return -EINVAL;
+ } else {
+ *num_planes = pixm->num_planes;
+ for (i = 0; i < pixm->num_planes; i++)
+ sizes[i] = pixm->plane_fmt[i].sizeimage;
+ }
+
+ return 0;
+}
+
+static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp1_buffer *ispbuf =
+ container_of(vbuf, struct rkisp1_buffer, vb);
+ struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
+ const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
+ unsigned int i;
+
+ memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
+ for (i = 0; i < pixm->num_planes; i++)
+ ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
+
+ /* Convert to non-MPLANE */
+ if (pixm->num_planes == 1) {
+ ispbuf->buff_addr[RKISP1_PLANE_CB] =
+ ispbuf->buff_addr[RKISP1_PLANE_Y] +
+ rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y);
+ ispbuf->buff_addr[RKISP1_PLANE_CR] =
+ ispbuf->buff_addr[RKISP1_PLANE_CB] +
+ rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB);
+ }
+
+ /*
+ * uv swap can be supported for planar formats by switching
+ * the address of cb and cr
+ */
+ if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap)
+ swap(ispbuf->buff_addr[RKISP1_PLANE_CR],
+ ispbuf->buff_addr[RKISP1_PLANE_CB]);
+
+ spin_lock_irq(&cap->buf.lock);
+ list_add_tail(&ispbuf->queue, &cap->buf.queue);
+ spin_unlock_irq(&cap->buf.lock);
+}
+
+static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+ struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
+ unsigned int i;
+
+ for (i = 0; i < cap->pix.fmt.num_planes; i++) {
+ unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage;
+
+ if (vb2_plane_size(vb, i) < size) {
+ dev_err(cap->rkisp1->dev,
+ "User buffer too small (%ld < %ld)\n",
+ vb2_plane_size(vb, i), size);
+ return -EINVAL;
+ }
+ vb2_set_plane_payload(vb, i, size);
+ }
+
+ return 0;
+}
+
+static void rkisp1_return_all_buffers(struct rkisp1_capture *cap,
+ enum vb2_buffer_state state)
+{
+ struct rkisp1_buffer *buf;
+
+ spin_lock_irq(&cap->buf.lock);
+ if (cap->buf.curr) {
+ vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state);
+ cap->buf.curr = NULL;
+ }
+ if (cap->buf.next) {
+ vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state);
+ cap->buf.next = NULL;
+ }
+ while (!list_empty(&cap->buf.queue)) {
+ buf = list_first_entry(&cap->buf.queue,
+ struct rkisp1_buffer, queue);
+ list_del(&buf->queue);
+ vb2_buffer_done(&buf->vb.vb2_buf, state);
+ }
+ spin_unlock_irq(&cap->buf.lock);
+}
+
+/*
+ * Most of registers inside rockchip ISP1 have shadow register since
+ * they must be not be changed during processing a frame.
+ * Usually, each sub-module updates its shadow register after
+ * processing the last pixel of a frame.
+ */
+static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
+{
+ struct rkisp1_device *rkisp1 = cap->rkisp1;
+ struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
+
+ cap->ops->set_data_path(cap);
+ cap->ops->config(cap);
+
+ /* Setup a buffer for the next frame */
+ spin_lock_irq(&cap->buf.lock);
+ rkisp1_set_next_buf(cap);
+ cap->ops->enable(cap);
+ /* It's safe to config ACTIVE and SHADOW regs for the
+ * first stream. While when the second is starting, do NOT
+ * force update because it also update the first one.
+ *
+ * The latter case would drop one more buf(that is 2) since
+ * there's not buf in shadow when the second FE received. This's
+ * also required because the second FE maybe corrupt especially
+ * when run at 120fps.
+ */
+ if (!other->is_streaming) {
+ /* force cfg update */
+ rkisp1_write(rkisp1,
+ RKISP1_CIF_MI_INIT_SOFT_UPD, RKISP1_CIF_MI_INIT);
+ rkisp1_set_next_buf(cap);
+ }
+ spin_unlock_irq(&cap->buf.lock);
+ cap->is_streaming = true;
+}
+
+static void rkisp1_cap_stream_disable(struct rkisp1_capture *cap)
+{
+ int ret;
+
+ /* Stream should stop in interrupt. If it doesn't, stop it by force. */
+ cap->is_stopping = true;
+ ret = wait_event_timeout(cap->done,
+ !cap->is_streaming,
+ msecs_to_jiffies(1000));
+ if (!ret) {
+ cap->rkisp1->debug.stop_timeout[cap->id]++;
+ cap->ops->stop(cap);
+ cap->is_stopping = false;
+ cap->is_streaming = false;
+ }
+}
+
+/*
+ * rkisp1_pipeline_stream_disable - disable nodes in the pipeline
+ *
+ * Call s_stream(false) in the reverse order from
+ * rkisp1_pipeline_stream_enable() and disable the DMA engine.
+ * Should be called before media_pipeline_stop()
+ */
+static void rkisp1_pipeline_stream_disable(struct rkisp1_capture *cap)
+ __must_hold(&cap->rkisp1->stream_lock)
+{
+ struct rkisp1_device *rkisp1 = cap->rkisp1;
+
+ rkisp1_cap_stream_disable(cap);
+
+ /*
+ * If the other capture is streaming, isp and sensor nodes shouldn't
+ * be disabled, skip them.
+ */
+ if (rkisp1->pipe.streaming_count < 2) {
+ v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream,
+ false);
+ v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false);
+ }
+
+ v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream,
+ false);
+}
+
+/*
+ * rkisp1_pipeline_stream_enable - enable nodes in the pipeline
+ *
+ * Enable the DMA Engine and call s_stream(true) through the pipeline.
+ * Should be called after media_pipeline_start()
+ */
+static int rkisp1_pipeline_stream_enable(struct rkisp1_capture *cap)
+ __must_hold(&cap->rkisp1->stream_lock)
+{
+ struct rkisp1_device *rkisp1 = cap->rkisp1;
+ int ret;
+
+ rkisp1_cap_stream_enable(cap);
+
+ ret = v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video,
+ s_stream, true);
+ if (ret)
+ goto err_disable_cap;
+
+ /*
+ * If the other capture is streaming, isp and sensor nodes are already
+ * enabled, skip them.
+ */
+ if (rkisp1->pipe.streaming_count > 1)
+ return 0;
+
+ ret = v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, true);
+ if (ret)
+ goto err_disable_rsz;
+
+ ret = v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream,
+ true);
+ if (ret)
+ goto err_disable_isp;
+
+ return 0;
+
+err_disable_isp:
+ v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false);
+err_disable_rsz:
+ v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream,
+ false);
+err_disable_cap:
+ rkisp1_cap_stream_disable(cap);
+
+ return ret;
+}
+
+static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue)
+{
+ struct rkisp1_capture *cap = queue->drv_priv;
+ struct rkisp1_vdev_node *node = &cap->vnode;
+ struct rkisp1_device *rkisp1 = cap->rkisp1;
+ int ret;
+
+ mutex_lock(&cap->rkisp1->stream_lock);
+
+ rkisp1_pipeline_stream_disable(cap);
+
+ rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR);
+
+ v4l2_pipeline_pm_put(&node->vdev.entity);
+ ret = pm_runtime_put(rkisp1->dev);
+ if (ret < 0)
+ dev_err(rkisp1->dev, "power down failed error:%d\n", ret);
+
+ rkisp1_dummy_buf_destroy(cap);
+
+ media_pipeline_stop(&node->vdev.entity);
+
+ mutex_unlock(&cap->rkisp1->stream_lock);
+}
+
+static int
+rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count)
+{
+ struct rkisp1_capture *cap = queue->drv_priv;
+ struct media_entity *entity = &cap->vnode.vdev.entity;
+ int ret;
+
+ mutex_lock(&cap->rkisp1->stream_lock);
+
+ ret = media_pipeline_start(entity, &cap->rkisp1->pipe);
+ if (ret) {
+ dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret);
+ goto err_ret_buffers;
+ }
+
+ ret = rkisp1_dummy_buf_create(cap);
+ if (ret)
+ goto err_pipeline_stop;
+
+ ret = pm_runtime_get_sync(cap->rkisp1->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(cap->rkisp1->dev);
+ dev_err(cap->rkisp1->dev, "power up failed %d\n", ret);
+ goto err_destroy_dummy;
+ }
+ ret = v4l2_pipeline_pm_get(entity);
+ if (ret) {
+ dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret);
+ goto err_pipe_pm_put;
+ }
+
+ ret = rkisp1_pipeline_stream_enable(cap);
+ if (ret)
+ goto err_v4l2_pm_put;
+
+ mutex_unlock(&cap->rkisp1->stream_lock);
+
+ return 0;
+
+err_v4l2_pm_put:
+ v4l2_pipeline_pm_put(entity);
+err_pipe_pm_put:
+ pm_runtime_put(cap->rkisp1->dev);
+err_destroy_dummy:
+ rkisp1_dummy_buf_destroy(cap);
+err_pipeline_stop:
+ media_pipeline_stop(entity);
+err_ret_buffers:
+ rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED);
+ mutex_unlock(&cap->rkisp1->stream_lock);
+
+ return ret;
+}
+
+static const struct vb2_ops rkisp1_vb2_ops = {
+ .queue_setup = rkisp1_vb2_queue_setup,
+ .buf_queue = rkisp1_vb2_buf_queue,
+ .buf_prepare = rkisp1_vb2_buf_prepare,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+ .stop_streaming = rkisp1_vb2_stop_streaming,
+ .start_streaming = rkisp1_vb2_start_streaming,
+};
+
+/* ----------------------------------------------------------------------------
+ * IOCTLs operations
+ */
+
+static const struct v4l2_format_info *
+rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm,
+ enum rkisp1_stream_id id)
+{
+ struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0];
+ const struct v4l2_format_info *info;
+ unsigned int i;
+ u32 stride;
+
+ memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt));
+ info = v4l2_format_info(pixm->pixelformat);
+ pixm->num_planes = info->mem_planes;
+ stride = info->bpp[0] * pixm->width;
+ /* Self path supports custom stride but Main path doesn't */
+ if (id == RKISP1_MAINPATH || plane_y->bytesperline < stride)
+ plane_y->bytesperline = stride;
+ plane_y->sizeimage = plane_y->bytesperline * pixm->height;
+
+ /* normalize stride to pixels per line */
+ stride = DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]);
+
+ for (i = 1; i < info->comp_planes; i++) {
+ struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i];
+
+ /* bytesperline for other components derive from Y component */
+ plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) *
+ info->bpp[i];
+ plane->sizeimage = plane->bytesperline *
+ DIV_ROUND_UP(pixm->height, info->vdiv);
+ }
+
+ /*
+ * If pixfmt is packed, then plane_fmt[0] should contain the total size
+ * considering all components. plane_fmt[i] for i > 0 should be ignored
+ * by userspace as mem_planes == 1, but we are keeping information there
+ * for convenience.
+ */
+ if (info->mem_planes == 1)
+ for (i = 1; i < info->comp_planes; i++)
+ plane_y->sizeimage += pixm->plane_fmt[i].sizeimage;
+
+ return info;
+}
+
+static const struct rkisp1_capture_fmt_cfg *
+rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt)
+{
+ unsigned int i;
+
+ for (i = 0; i < cap->config->fmt_size; i++) {
+ if (cap->config->fmts[i].fourcc == pixelfmt)
+ return &cap->config->fmts[i];
+ }
+ return NULL;
+}
+
+static void rkisp1_try_fmt(const struct rkisp1_capture *cap,
+ struct v4l2_pix_format_mplane *pixm,
+ const struct rkisp1_capture_fmt_cfg **fmt_cfg,
+ const struct v4l2_format_info **fmt_info)
+{
+ const struct rkisp1_capture_config *config = cap->config;
+ const struct rkisp1_capture_fmt_cfg *fmt;
+ const struct v4l2_format_info *info;
+ const unsigned int max_widths[] = { RKISP1_RSZ_MP_SRC_MAX_WIDTH,
+ RKISP1_RSZ_SP_SRC_MAX_WIDTH };
+ const unsigned int max_heights[] = { RKISP1_RSZ_MP_SRC_MAX_HEIGHT,
+ RKISP1_RSZ_SP_SRC_MAX_HEIGHT};
+
+ fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat);
+ if (!fmt) {
+ fmt = config->fmts;
+ pixm->pixelformat = fmt->fourcc;
+ }
+
+ pixm->width = clamp_t(u32, pixm->width,
+ RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]);
+ pixm->height = clamp_t(u32, pixm->height,
+ RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]);
+
+ pixm->field = V4L2_FIELD_NONE;
+ pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
+ pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
+
+ info = rkisp1_fill_pixfmt(pixm, cap->id);
+
+ if (fmt_cfg)
+ *fmt_cfg = fmt;
+ if (fmt_info)
+ *fmt_info = info;
+}
+
+static void rkisp1_set_fmt(struct rkisp1_capture *cap,
+ struct v4l2_pix_format_mplane *pixm)
+{
+ rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info);
+ cap->pix.fmt = *pixm;
+
+ /* SP supports custom stride in number of pixels of the Y plane */
+ if (cap->id == RKISP1_SELFPATH)
+ cap->sp_y_stride = pixm->plane_fmt[0].bytesperline /
+ cap->pix.info->bpp[0];
+}
+
+static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct rkisp1_capture *cap = video_drvdata(file);
+
+ rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL);
+
+ return 0;
+}
+
+static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct rkisp1_capture *cap = video_drvdata(file);
+ const struct rkisp1_capture_fmt_cfg *fmt = NULL;
+ unsigned int i, n = 0;
+
+ if (!f->mbus_code) {
+ if (f->index >= cap->config->fmt_size)
+ return -EINVAL;
+
+ fmt = &cap->config->fmts[f->index];
+ f->pixelformat = fmt->fourcc;
+ return 0;
+ }
+
+ for (i = 0; i < cap->config->fmt_size; i++) {
+ if (cap->config->fmts[i].mbus != f->mbus_code)
+ continue;
+
+ if (n++ == f->index) {
+ f->pixelformat = cap->config->fmts[i].fourcc;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int rkisp1_s_fmt_vid_cap_mplane(struct file *file,
+ void *priv, struct v4l2_format *f)
+{
+ struct rkisp1_capture *cap = video_drvdata(file);
+ struct rkisp1_vdev_node *node =
+ rkisp1_vdev_to_node(&cap->vnode.vdev);
+
+ if (vb2_is_busy(&node->buf_queue))
+ return -EBUSY;
+
+ rkisp1_set_fmt(cap, &f->fmt.pix_mp);
+
+ return 0;
+}
+
+static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct rkisp1_capture *cap = video_drvdata(file);
+
+ f->fmt.pix_mp = cap->pix.fmt;
+
+ return 0;
+}
+
+static int
+rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
+{
+ struct rkisp1_capture *cap_dev = video_drvdata(file);
+ struct rkisp1_device *rkisp1 = cap_dev->rkisp1;
+
+ strscpy(cap->driver, rkisp1->dev->driver->name, sizeof(cap->driver));
+ strscpy(cap->card, rkisp1->dev->driver->name, sizeof(cap->card));
+ strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info));
+
+ return 0;
+}
+
+static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = {
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane,
+ .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane,
+ .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane,
+ .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane,
+ .vidioc_querycap = rkisp1_querycap,
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static int rkisp1_capture_link_validate(struct media_link *link)
+{
+ struct video_device *vdev =
+ media_entity_to_video_device(link->sink->entity);
+ struct v4l2_subdev *sd =
+ media_entity_to_v4l2_subdev(link->source->entity);
+ struct rkisp1_capture *cap = video_get_drvdata(vdev);
+ const struct rkisp1_capture_fmt_cfg *fmt =
+ rkisp1_find_fmt_cfg(cap, cap->pix.fmt.pixelformat);
+ struct v4l2_subdev_format sd_fmt;
+ int ret;
+
+ sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ sd_fmt.pad = link->source->index;
+ ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt);
+ if (ret)
+ return ret;
+
+ if (sd_fmt.format.height != cap->pix.fmt.height ||
+ sd_fmt.format.width != cap->pix.fmt.width ||
+ sd_fmt.format.code != fmt->mbus)
+ return -EPIPE;
+
+ return 0;
+}
+
+/* ----------------------------------------------------------------------------
+ * core functions
+ */
+
+static const struct media_entity_operations rkisp1_media_ops = {
+ .link_validate = rkisp1_capture_link_validate,
+};
+
+static const struct v4l2_file_operations rkisp1_fops = {
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release,
+ .unlocked_ioctl = video_ioctl2,
+ .poll = vb2_fop_poll,
+ .mmap = vb2_fop_mmap,
+};
+
+static void rkisp1_unregister_capture(struct rkisp1_capture *cap)
+{
+ media_entity_cleanup(&cap->vnode.vdev.entity);
+ vb2_video_unregister_device(&cap->vnode.vdev);
+}
+
+void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH];
+ struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH];
+
+ rkisp1_unregister_capture(mp);
+ rkisp1_unregister_capture(sp);
+}
+
+static int rkisp1_register_capture(struct rkisp1_capture *cap)
+{
+ const char * const dev_names[] = {RKISP1_MP_DEV_NAME,
+ RKISP1_SP_DEV_NAME};
+ struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev;
+ struct video_device *vdev = &cap->vnode.vdev;
+ struct rkisp1_vdev_node *node;
+ struct vb2_queue *q;
+ int ret;
+
+ strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name));
+ node = rkisp1_vdev_to_node(vdev);
+ mutex_init(&node->vlock);
+
+ vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops;
+ vdev->release = video_device_release_empty;
+ vdev->fops = &rkisp1_fops;
+ vdev->minor = -1;
+ vdev->v4l2_dev = v4l2_dev;
+ vdev->lock = &node->vlock;
+ vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
+ V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
+ vdev->entity.ops = &rkisp1_media_ops;
+ video_set_drvdata(vdev, cap);
+ vdev->vfl_dir = VFL_DIR_RX;
+ node->pad.flags = MEDIA_PAD_FL_SINK;
+
+ q = &node->buf_queue;
+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ q->io_modes = VB2_MMAP | VB2_DMABUF;
+ q->drv_priv = cap;
+ q->ops = &rkisp1_vb2_ops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->buf_struct_size = sizeof(struct rkisp1_buffer);
+ q->min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED;
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->lock = &node->vlock;
+ q->dev = cap->rkisp1->dev;
+ ret = vb2_queue_init(q);
+ if (ret) {
+ dev_err(cap->rkisp1->dev,
+ "vb2 queue init failed (err=%d)\n", ret);
+ return ret;
+ }
+
+ vdev->queue = q;
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ dev_err(cap->rkisp1->dev,
+ "failed to register %s, ret=%d\n", vdev->name, ret);
+ return ret;
+ }
+ v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name,
+ vdev->num);
+
+ ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
+ if (ret) {
+ video_unregister_device(vdev);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void
+rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id)
+{
+ struct rkisp1_capture *cap = &rkisp1->capture_devs[id];
+ struct v4l2_pix_format_mplane pixm;
+
+ memset(cap, 0, sizeof(*cap));
+ cap->id = id;
+ cap->rkisp1 = rkisp1;
+
+ INIT_LIST_HEAD(&cap->buf.queue);
+ init_waitqueue_head(&cap->done);
+ spin_lock_init(&cap->buf.lock);
+ if (cap->id == RKISP1_SELFPATH) {
+ cap->ops = &rkisp1_capture_ops_sp;
+ cap->config = &rkisp1_capture_config_sp;
+ } else {
+ cap->ops = &rkisp1_capture_ops_mp;
+ cap->config = &rkisp1_capture_config_mp;
+ }
+
+ cap->is_streaming = false;
+
+ memset(&pixm, 0, sizeof(pixm));
+ pixm.pixelformat = V4L2_PIX_FMT_YUYV;
+ pixm.width = RKISP1_DEFAULT_WIDTH;
+ pixm.height = RKISP1_DEFAULT_HEIGHT;
+ rkisp1_set_fmt(cap, &pixm);
+}
+
+int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_capture *cap;
+ unsigned int i, j;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) {
+ rkisp1_capture_init(rkisp1, i);
+ cap = &rkisp1->capture_devs[i];
+ cap->rkisp1 = rkisp1;
+ ret = rkisp1_register_capture(cap);
+ if (ret)
+ goto err_unreg_capture_devs;
+ }
+
+ return 0;
+
+err_unreg_capture_devs:
+ for (j = 0; j < i; j++) {
+ cap = &rkisp1->capture_devs[j];
+ rkisp1_unregister_capture(cap);
+ }
+
+ return ret;
+}
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.c
new file mode 100644
index 000000000000..cf889666e166
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Rockchip ISP1 Driver - Common definitions
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ */
+
+#include <media/v4l2-rect.h>
+
+#include "rkisp1-common.h"
+
+static const struct v4l2_rect rkisp1_sd_min_crop = {
+ .width = RKISP1_ISP_MIN_WIDTH,
+ .height = RKISP1_ISP_MIN_HEIGHT,
+ .top = 0,
+ .left = 0,
+};
+
+void rkisp1_sd_adjust_crop_rect(struct v4l2_rect *crop,
+ const struct v4l2_rect *bounds)
+{
+ v4l2_rect_set_min_size(crop, &rkisp1_sd_min_crop);
+ v4l2_rect_map_inside(crop, bounds);
+}
+
+void rkisp1_sd_adjust_crop(struct v4l2_rect *crop,
+ const struct v4l2_mbus_framefmt *bounds)
+{
+ struct v4l2_rect crop_bounds = {
+ .left = 0,
+ .top = 0,
+ .width = bounds->width,
+ .height = bounds->height,
+ };
+
+ rkisp1_sd_adjust_crop_rect(crop, &crop_bounds);
+}
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
new file mode 100644
index 000000000000..038c303a8aed
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-common.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Rockchip ISP1 Driver - Common definitions
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ *
+ * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _RKISP1_COMMON_H
+#define _RKISP1_COMMON_H
+
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/rkisp1-config.h>
+#include <media/media-device.h>
+#include <media/media-entity.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/videobuf2-v4l2.h>
+
+#include "rkisp1-regs.h"
+
+/*
+ * flags on the 'direction' field in struct 'rkisp1_isp_mbus_info' that indicate
+ * on which pad the media bus format is supported
+ */
+#define RKISP1_ISP_SD_SRC BIT(0)
+#define RKISP1_ISP_SD_SINK BIT(1)
+
+/* min and max values for the widths and heights of the entities */
+#define RKISP1_ISP_MAX_WIDTH 4032
+#define RKISP1_ISP_MAX_HEIGHT 3024
+#define RKISP1_ISP_MIN_WIDTH 32
+#define RKISP1_ISP_MIN_HEIGHT 32
+
+#define RKISP1_RSZ_MP_SRC_MAX_WIDTH 4416
+#define RKISP1_RSZ_MP_SRC_MAX_HEIGHT 3312
+#define RKISP1_RSZ_SP_SRC_MAX_WIDTH 1920
+#define RKISP1_RSZ_SP_SRC_MAX_HEIGHT 1920
+#define RKISP1_RSZ_SRC_MIN_WIDTH 32
+#define RKISP1_RSZ_SRC_MIN_HEIGHT 16
+
+/* the default width and height of all the entities */
+#define RKISP1_DEFAULT_WIDTH 800
+#define RKISP1_DEFAULT_HEIGHT 600
+
+#define RKISP1_DRIVER_NAME "rkisp1"
+#define RKISP1_BUS_INFO "platform:" RKISP1_DRIVER_NAME
+
+/* maximum number of clocks */
+#define RKISP1_MAX_BUS_CLK 8
+
+/* a bitmask of the ready stats */
+#define RKISP1_STATS_MEAS_MASK (RKISP1_CIF_ISP_AWB_DONE | \
+ RKISP1_CIF_ISP_AFM_FIN | \
+ RKISP1_CIF_ISP_EXP_END | \
+ RKISP1_CIF_ISP_HIST_MEASURE_RDY)
+
+/* enum for the resizer pads */
+enum rkisp1_rsz_pad {
+ RKISP1_RSZ_PAD_SINK,
+ RKISP1_RSZ_PAD_SRC,
+ RKISP1_RSZ_PAD_MAX
+};
+
+/* enum for the capture id */
+enum rkisp1_stream_id {
+ RKISP1_MAINPATH,
+ RKISP1_SELFPATH,
+};
+
+/* bayer patterns */
+enum rkisp1_fmt_raw_pat_type {
+ RKISP1_RAW_RGGB = 0,
+ RKISP1_RAW_GRBG,
+ RKISP1_RAW_GBRG,
+ RKISP1_RAW_BGGR,
+};
+
+/* enum for the isp pads */
+enum rkisp1_isp_pad {
+ RKISP1_ISP_PAD_SINK_VIDEO,
+ RKISP1_ISP_PAD_SINK_PARAMS,
+ RKISP1_ISP_PAD_SOURCE_VIDEO,
+ RKISP1_ISP_PAD_SOURCE_STATS,
+ RKISP1_ISP_PAD_MAX
+};
+
+/*
+ * struct rkisp1_sensor_async - A container for the v4l2_async_subdev to add to the notifier
+ * of the v4l2-async API
+ *
+ * @asd: async_subdev variable for the sensor
+ * @lanes: number of lanes
+ * @mbus_type: type of bus (currently only CSI2 is supported)
+ * @mbus_flags: media bus (V4L2_MBUS_*) flags
+ * @sd: a pointer to v4l2_subdev struct of the sensor
+ * @pixel_rate_ctrl: pixel rate of the sensor, used to initialize the phy
+ * @dphy: a pointer to the phy
+ */
+struct rkisp1_sensor_async {
+ struct v4l2_async_subdev asd;
+ unsigned int lanes;
+ enum v4l2_mbus_type mbus_type;
+ unsigned int mbus_flags;
+ struct v4l2_subdev *sd;
+ struct v4l2_ctrl *pixel_rate_ctrl;
+ struct phy *dphy;
+};
+
+/*
+ * struct rkisp1_isp - ISP subdev entity
+ *
+ * @sd: v4l2_subdev variable
+ * @rkisp1: pointer to rkisp1_device
+ * @pads: media pads
+ * @pad_cfg: pads configurations
+ * @sink_fmt: input format
+ * @src_fmt: output format
+ * @ops_lock: ops serialization
+ * @is_dphy_errctrl_disabled: if dphy errctrl is disabled (avoid endless interrupt)
+ * @frame_sequence: used to synchronize frame_id between video devices.
+ */
+struct rkisp1_isp {
+ struct v4l2_subdev sd;
+ struct media_pad pads[RKISP1_ISP_PAD_MAX];
+ struct v4l2_subdev_pad_config pad_cfg[RKISP1_ISP_PAD_MAX];
+ const struct rkisp1_isp_mbus_info *sink_fmt;
+ const struct rkisp1_isp_mbus_info *src_fmt;
+ struct mutex ops_lock; /* serialize the subdevice ops */
+ bool is_dphy_errctrl_disabled;
+ __u32 frame_sequence;
+};
+
+/*
+ * struct rkisp1_vdev_node - Container for the video nodes: params, stats, mainpath, selfpath
+ *
+ * @buf_queue: queue of buffers
+ * @vlock: lock of the video node
+ * @vdev: video node
+ * @pad: media pad
+ */
+struct rkisp1_vdev_node {
+ struct vb2_queue buf_queue;
+ struct mutex vlock; /* ioctl serialization mutex */
+ struct video_device vdev;
+ struct media_pad pad;
+};
+
+/*
+ * struct rkisp1_buffer - A container for the vb2 buffers used by the video devices:
+ * params, stats, mainpath, selfpath
+ *
+ * @vb: vb2 buffer
+ * @queue: entry of the buffer in the queue
+ * @buff_addr: dma addresses of each plane, used only by the capture devices: selfpath, mainpath
+ * @vaddr: virtual address for buffers used by params and stats devices
+ */
+struct rkisp1_buffer {
+ struct vb2_v4l2_buffer vb;
+ struct list_head queue;
+ union {
+ u32 buff_addr[VIDEO_MAX_PLANES];
+ void *vaddr;
+ };
+};
+
+/*
+ * struct rkisp1_dummy_buffer - A buffer to write the next frame to in case
+ * there are no vb2 buffers available.
+ *
+ * @vaddr: return value of call to dma_alloc_attrs.
+ * @dma_addr: dma address of the buffer.
+ * @size: size of the buffer.
+ */
+struct rkisp1_dummy_buffer {
+ void *vaddr;
+ dma_addr_t dma_addr;
+ u32 size;
+};
+
+struct rkisp1_device;
+
+/*
+ * struct rkisp1_capture - ISP capture video device
+ *
+ * @vnode: video node
+ * @rkisp1: pointer to rkisp1_device
+ * @id: id of the capture, one of RKISP1_SELFPATH, RKISP1_MAINPATH
+ * @ops: list of callbacks to configure the capture device.
+ * @config: a pointer to the list of registers to configure the capture format.
+ * @is_streaming: device is streaming
+ * @is_stopping: stop_streaming callback was called and the device is in the process of
+ * stopping the streaming.
+ * @done: when stop_streaming callback is called, the device waits for the next irq
+ * handler to stop the streaming by waiting on the 'done' wait queue.
+ * If the irq handler is not called, the stream is stopped by the callback
+ * after timeout.
+ * @sp_y_stride: the selfpath allows to configure a y stride that is longer than the image width.
+ * @buf.lock: lock to protect buf.queue
+ * @buf.queue: queued buffer list
+ * @buf.dummy: dummy space to store dropped data
+ *
+ * rkisp1 uses shadow registers, so it needs two buffers at a time
+ * @buf.curr: the buffer used for current frame
+ * @buf.next: the buffer used for next frame
+ * @pix.cfg: pixel configuration
+ * @pix.info: a pointer to the v4l2_format_info of the pixel format
+ * @pix.fmt: buffer format
+ */
+struct rkisp1_capture {
+ struct rkisp1_vdev_node vnode;
+ struct rkisp1_device *rkisp1;
+ enum rkisp1_stream_id id;
+ const struct rkisp1_capture_ops *ops;
+ const struct rkisp1_capture_config *config;
+ bool is_streaming;
+ bool is_stopping;
+ wait_queue_head_t done;
+ unsigned int sp_y_stride;
+ struct {
+ /* protects queue, curr and next */
+ spinlock_t lock;
+ struct list_head queue;
+ struct rkisp1_dummy_buffer dummy;
+ struct rkisp1_buffer *curr;
+ struct rkisp1_buffer *next;
+ } buf;
+ struct {
+ const struct rkisp1_capture_fmt_cfg *cfg;
+ const struct v4l2_format_info *info;
+ struct v4l2_pix_format_mplane fmt;
+ } pix;
+};
+
+/*
+ * struct rkisp1_stats - ISP Statistics device
+ *
+ * @vnode: video node
+ * @rkisp1: pointer to the rkisp1 device
+ * @lock: locks the buffer list 'stat'
+ * @stat: queue of rkisp1_buffer
+ * @vdev_fmt: v4l2_format of the metadata format
+ */
+struct rkisp1_stats {
+ struct rkisp1_vdev_node vnode;
+ struct rkisp1_device *rkisp1;
+
+ spinlock_t lock; /* locks the buffers list 'stats' */
+ struct list_head stat;
+ struct v4l2_format vdev_fmt;
+};
+
+/*
+ * struct rkisp1_params - ISP input parameters device
+ *
+ * @vnode: video node
+ * @rkisp1: pointer to the rkisp1 device
+ * @config_lock: locks the buffer list 'params'
+ * @params: queue of rkisp1_buffer
+ * @vdev_fmt: v4l2_format of the metadata format
+ * @quantization: the quantization configured on the isp's src pad
+ * @raw_type: the bayer pattern on the isp video sink pad
+ */
+struct rkisp1_params {
+ struct rkisp1_vdev_node vnode;
+ struct rkisp1_device *rkisp1;
+
+ spinlock_t config_lock; /* locks the buffers list 'params' */
+ struct list_head params;
+ struct v4l2_format vdev_fmt;
+
+ enum v4l2_quantization quantization;
+ enum rkisp1_fmt_raw_pat_type raw_type;
+};
+
+/*
+ * struct rkisp1_resizer - Resizer subdev
+ *
+ * @sd: v4l2_subdev variable
+ * @id: id of the resizer, one of RKISP1_SELFPATH, RKISP1_MAINPATH
+ * @rkisp1: pointer to the rkisp1 device
+ * @pads: media pads
+ * @pad_cfg: configurations for the pads
+ * @config: the set of registers to configure the resizer
+ * @pixel_enc: pixel encoding of the resizer
+ * @ops_lock: a lock for the subdev ops
+ */
+struct rkisp1_resizer {
+ struct v4l2_subdev sd;
+ enum rkisp1_stream_id id;
+ struct rkisp1_device *rkisp1;
+ struct media_pad pads[RKISP1_RSZ_PAD_MAX];
+ struct v4l2_subdev_pad_config pad_cfg[RKISP1_RSZ_PAD_MAX];
+ const struct rkisp1_rsz_config *config;
+ enum v4l2_pixel_encoding pixel_enc;
+ struct mutex ops_lock; /* serialize the subdevice ops */
+};
+
+/*
+ * struct rkisp1_debug - Values to be exposed on debugfs.
+ * The parameters are counters of the number of times the
+ * event occurred since the driver was loaded.
+ *
+ * @data_loss: loss of data occurred within a line, processing failure
+ * @outform_size_error: size error is generated in outmux submodule
+ * @img_stabilization_size_error: size error is generated in image stabilization submodule
+ * @inform_size_err: size error is generated in inform submodule
+ * @mipi_error: mipi error occurred
+ * @stats_error: writing to the 'Interrupt clear register' did not clear
+ * it in the register 'Masked interrupt status'
+ * @stop_timeout: upon stream stop, the capture waits 1 second for the isr to stop
+ * the stream. This param is incremented in case of timeout.
+ * @frame_drop: a frame was ready but the buffer queue was empty so the frame
+ * was not sent to userspace
+ */
+struct rkisp1_debug {
+ struct dentry *debugfs_dir;
+ unsigned long data_loss;
+ unsigned long outform_size_error;
+ unsigned long img_stabilization_size_error;
+ unsigned long inform_size_error;
+ unsigned long irq_delay;
+ unsigned long mipi_error;
+ unsigned long stats_error;
+ unsigned long stop_timeout[2];
+ unsigned long frame_drop[2];
+};
+
+/*
+ * struct rkisp1_device - ISP platform device
+ *
+ * @base_addr: base register address
+ * @irq: the irq number
+ * @dev: a pointer to the struct device
+ * @clk_size: number of clocks
+ * @clks: array of clocks
+ * @v4l2_dev: v4l2_device variable
+ * @media_dev: media_device variable
+ * @notifier: a notifier to register on the v4l2-async API to be notified on the sensor
+ * @active_sensor: sensor in-use, set when streaming on
+ * @isp: ISP sub-device
+ * @resizer_devs: resizer sub-devices
+ * @capture_devs: capture devices
+ * @stats: ISP statistics metadata capture device
+ * @params: ISP parameters metadata output device
+ * @pipe: media pipeline
+ * @stream_lock: serializes {start/stop}_streaming callbacks between the capture devices.
+ * @debug: debug params to be exposed on debugfs
+ */
+struct rkisp1_device {
+ void __iomem *base_addr;
+ int irq;
+ struct device *dev;
+ unsigned int clk_size;
+ struct clk_bulk_data clks[RKISP1_MAX_BUS_CLK];
+ struct v4l2_device v4l2_dev;
+ struct media_device media_dev;
+ struct v4l2_async_notifier notifier;
+ struct rkisp1_sensor_async *active_sensor;
+ struct rkisp1_isp isp;
+ struct rkisp1_resizer resizer_devs[2];
+ struct rkisp1_capture capture_devs[2];
+ struct rkisp1_stats stats;
+ struct rkisp1_params params;
+ struct media_pipeline pipe;
+ struct mutex stream_lock; /* serialize {start/stop}_streaming cb between capture devices */
+ struct rkisp1_debug debug;
+};
+
+/*
+ * struct rkisp1_isp_mbus_info - ISP media bus info, Translates media bus code to hardware
+ * format values
+ *
+ * @mbus_code: media bus code
+ * @pixel_enc: pixel encoding
+ * @mipi_dt: mipi data type
+ * @yuv_seq: the order of the Y, Cb, Cr values
+ * @bus_width: bus width
+ * @bayer_pat: bayer pattern
+ * @direction: a bitmask of the flags indicating on which pad the format is supported on
+ */
+struct rkisp1_isp_mbus_info {
+ u32 mbus_code;
+ enum v4l2_pixel_encoding pixel_enc;
+ u32 mipi_dt;
+ u32 yuv_seq;
+ u8 bus_width;
+ enum rkisp1_fmt_raw_pat_type bayer_pat;
+ unsigned int direction;
+};
+
+static inline void
+rkisp1_write(struct rkisp1_device *rkisp1, u32 val, unsigned int addr)
+{
+ writel(val, rkisp1->base_addr + addr);
+}
+
+static inline u32 rkisp1_read(struct rkisp1_device *rkisp1, unsigned int addr)
+{
+ return readl(rkisp1->base_addr + addr);
+}
+
+/*
+ * rkisp1_cap_enum_mbus_codes - A helper function that return the i'th supported mbus code
+ * of the capture entity. This is used to enumerate the supported
+ * mbus codes on the source pad of the resizer.
+ *
+ * @cap: the capture entity
+ * @code: the mbus code, the function reads the code->index and fills the code->code
+ */
+int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap,
+ struct v4l2_subdev_mbus_code_enum *code);
+
+/*
+ * rkisp1_sd_adjust_crop_rect - adjust a rectangle to fit into another rectangle.
+ *
+ * @crop: rectangle to adjust.
+ * @bounds: rectangle used as bounds.
+ */
+void rkisp1_sd_adjust_crop_rect(struct v4l2_rect *crop,
+ const struct v4l2_rect *bounds);
+
+/*
+ * rkisp1_sd_adjust_crop - adjust a rectangle to fit into media bus format
+ *
+ * @crop: rectangle to adjust.
+ * @bounds: media bus format used as bounds.
+ */
+void rkisp1_sd_adjust_crop(struct v4l2_rect *crop,
+ const struct v4l2_mbus_framefmt *bounds);
+
+/*
+ * rkisp1_isp_mbus_info - get the isp info of the media bus code
+ *
+ * @mbus_code: the media bus code
+ */
+const struct rkisp1_isp_mbus_info *rkisp1_isp_mbus_info_get(u32 mbus_code);
+
+/* rkisp1_params_configure - configure the params when stream starts.
+ * This function is called by the isp entity upon stream starts.
+ * The function applies the initial configuration of the parameters.
+ *
+ * @params: pointer to rkisp1_params.
+ * @bayer_pat: the bayer pattern on the isp video sink pad
+ * @quantization: the quantization configured on the isp's src pad
+ */
+void rkisp1_params_configure(struct rkisp1_params *params,
+ enum rkisp1_fmt_raw_pat_type bayer_pat,
+ enum v4l2_quantization quantization);
+
+/* rkisp1_params_disable - disable all parameters.
+ * This function is called by the isp entity upon stream start
+ * when capturing bayer format.
+ *
+ * @params: pointer to rkisp1_params.
+ */
+void rkisp1_params_disable(struct rkisp1_params *params);
+
+/* irq handlers */
+void rkisp1_isp_isr(struct rkisp1_device *rkisp1);
+void rkisp1_mipi_isr(struct rkisp1_device *rkisp1);
+void rkisp1_capture_isr(struct rkisp1_device *rkisp1);
+void rkisp1_stats_isr(struct rkisp1_stats *stats, u32 isp_ris);
+void rkisp1_params_isr(struct rkisp1_device *rkisp1);
+
+/* register/unregisters functions of the entities */
+int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1);
+void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1);
+
+int rkisp1_isp_register(struct rkisp1_device *rkisp1);
+void rkisp1_isp_unregister(struct rkisp1_device *rkisp1);
+
+int rkisp1_resizer_devs_register(struct rkisp1_device *rkisp1);
+void rkisp1_resizer_devs_unregister(struct rkisp1_device *rkisp1);
+
+int rkisp1_stats_register(struct rkisp1_device *rkisp1);
+void rkisp1_stats_unregister(struct rkisp1_device *rkisp1);
+
+int rkisp1_params_register(struct rkisp1_device *rkisp1);
+void rkisp1_params_unregister(struct rkisp1_device *rkisp1);
+
+#endif /* _RKISP1_COMMON_H */
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
new file mode 100644
index 000000000000..68da1eed753d
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
@@ -0,0 +1,577 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Rockchip ISP1 Driver - Base driver
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ *
+ * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-mipi-dphy.h>
+#include <media/v4l2-fwnode.h>
+
+#include "rkisp1-common.h"
+
+/*
+ * ISP Details
+ * -----------
+ *
+ * ISP Comprises with:
+ * MIPI serial camera interface
+ * Image Signal Processing
+ * Many Image Enhancement Blocks
+ * Crop
+ * Resizer
+ * RBG display ready image
+ * Image Rotation
+ *
+ * ISP Block Diagram
+ * -----------------
+ * rkisp1-resizer.c rkisp1-capture.c
+ * |====================| |=======================|
+ * rkisp1-isp.c Main Picture Path
+ * |==========================| |===============================================|
+ * +-----------+ +--+--+--+--+ +--------+ +--------+ +-----------+
+ * | | | | | | | | | | | | |
+ * +--------+ |\ | | | | | | | -->| Crop |->| RSZ |------------->| |
+ * | MIPI |--->| \ | | | | | | | | | | | | | |
+ * +--------+ | | | | |IE|IE|IE|IE| | +--------+ +--------+ | Memory |
+ * |MUX|--->| ISP |->|0 |1 |2 |3 |---+ | Interface |
+ * +--------+ | | | | | | | | | | +--------+ +--------+ +--------+ | |
+ * |Parallel|--->| / | | | | | | | | | | | | | | | |
+ * +--------+ |/ | | | | | | | -->| Crop |->| RSZ |->| RGB |->| |
+ * | | | | | | | | | | | | Rotate | | |
+ * +-----------+ +--+--+--+--+ +--------+ +--------+ +--------+ +-----------+
+ * ^
+ * +--------+ | |===============================================|
+ * | DMA |------------------------------------+ Self Picture Path
+ * +--------+
+ *
+ * rkisp1-stats.c rkisp1-params.c
+ * |===============| |===============|
+ * +---------------+ +---------------+
+ * | | | |
+ * | ISP | | ISP |
+ * | | | |
+ * +---------------+ +---------------+
+ *
+ *
+ * Media Topology
+ * --------------
+ * +----------+ +----------+
+ * | Sensor 2 | | Sensor X |
+ * ------------ ... ------------
+ * | 0 | | 0 |
+ * +----------+ +----------+ +-----------+
+ * \ | | params |
+ * \ | | (output) |
+ * +----------+ \ | +-----------+
+ * | Sensor 1 | v v |
+ * ------------ +------+------+ |
+ * | 0 |----->| 0 | 1 |<---------+
+ * +----------+ |------+------|
+ * | ISP |
+ * |------+------|
+ * +-------------| 2 | 3 |----------+
+ * | +------+------+ |
+ * | | |
+ * v v v
+ * +- ---------+ +-----------+ +-----------+
+ * | 0 | | 0 | | stats |
+ * ------------- ------------- | (capture) |
+ * | Resizer | | Resizer | +-----------+
+ * ------------| ------------|
+ * | 1 | | 1 |
+ * +-----------+ +-----------+
+ * | |
+ * v v
+ * +-----------+ +-----------+
+ * | selfpath | | mainpath |
+ * | (capture) | | (capture) |
+ * +-----------+ +-----------+
+ */
+
+struct rkisp1_match_data {
+ const char * const *clks;
+ unsigned int size;
+};
+
+/* ----------------------------------------------------------------------------
+ * Sensor DT bindings
+ */
+
+static int rkisp1_create_links(struct rkisp1_device *rkisp1)
+{
+ struct media_entity *source, *sink;
+ unsigned int flags, source_pad;
+ struct v4l2_subdev *sd;
+ unsigned int i;
+ int ret;
+
+ /* sensor links */
+ flags = MEDIA_LNK_FL_ENABLED;
+ list_for_each_entry(sd, &rkisp1->v4l2_dev.subdevs, list) {
+ if (sd == &rkisp1->isp.sd ||
+ sd == &rkisp1->resizer_devs[RKISP1_MAINPATH].sd ||
+ sd == &rkisp1->resizer_devs[RKISP1_SELFPATH].sd)
+ continue;
+
+ ret = media_entity_get_fwnode_pad(&sd->entity, sd->fwnode,
+ MEDIA_PAD_FL_SOURCE);
+ if (ret < 0) {
+ dev_err(rkisp1->dev, "failed to find src pad for %s\n",
+ sd->name);
+ return ret;
+ }
+ source_pad = ret;
+
+ ret = media_create_pad_link(&sd->entity, source_pad,
+ &rkisp1->isp.sd.entity,
+ RKISP1_ISP_PAD_SINK_VIDEO,
+ flags);
+ if (ret)
+ return ret;
+
+ flags = 0;
+ }
+
+ flags = MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE;
+
+ /* create ISP->RSZ->CAP links */
+ for (i = 0; i < 2; i++) {
+ source = &rkisp1->isp.sd.entity;
+ sink = &rkisp1->resizer_devs[i].sd.entity;
+ ret = media_create_pad_link(source, RKISP1_ISP_PAD_SOURCE_VIDEO,
+ sink, RKISP1_RSZ_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED);
+ if (ret)
+ return ret;
+
+ source = sink;
+ sink = &rkisp1->capture_devs[i].vnode.vdev.entity;
+ ret = media_create_pad_link(source, RKISP1_RSZ_PAD_SRC,
+ sink, 0, flags);
+ if (ret)
+ return ret;
+ }
+
+ /* params links */
+ source = &rkisp1->params.vnode.vdev.entity;
+ sink = &rkisp1->isp.sd.entity;
+ ret = media_create_pad_link(source, 0, sink,
+ RKISP1_ISP_PAD_SINK_PARAMS, flags);
+ if (ret)
+ return ret;
+
+ /* 3A stats links */
+ source = &rkisp1->isp.sd.entity;
+ sink = &rkisp1->stats.vnode.vdev.entity;
+ return media_create_pad_link(source, RKISP1_ISP_PAD_SOURCE_STATS,
+ sink, 0, flags);
+}
+
+static int rkisp1_subdev_notifier_bound(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *sd,
+ struct v4l2_async_subdev *asd)
+{
+ struct rkisp1_device *rkisp1 =
+ container_of(notifier, struct rkisp1_device, notifier);
+ struct rkisp1_sensor_async *s_asd =
+ container_of(asd, struct rkisp1_sensor_async, asd);
+
+ s_asd->pixel_rate_ctrl = v4l2_ctrl_find(sd->ctrl_handler,
+ V4L2_CID_PIXEL_RATE);
+ s_asd->sd = sd;
+ s_asd->dphy = devm_phy_get(rkisp1->dev, "dphy");
+ if (IS_ERR(s_asd->dphy)) {
+ if (PTR_ERR(s_asd->dphy) != -EPROBE_DEFER)
+ dev_err(rkisp1->dev, "Couldn't get the MIPI D-PHY\n");
+ return PTR_ERR(s_asd->dphy);
+ }
+
+ phy_init(s_asd->dphy);
+
+ return 0;
+}
+
+static void rkisp1_subdev_notifier_unbind(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *sd,
+ struct v4l2_async_subdev *asd)
+{
+ struct rkisp1_sensor_async *s_asd =
+ container_of(asd, struct rkisp1_sensor_async, asd);
+
+ phy_exit(s_asd->dphy);
+}
+
+static int rkisp1_subdev_notifier_complete(struct v4l2_async_notifier *notifier)
+{
+ struct rkisp1_device *rkisp1 =
+ container_of(notifier, struct rkisp1_device, notifier);
+ int ret;
+
+ ret = rkisp1_create_links(rkisp1);
+ if (ret)
+ return ret;
+
+ ret = v4l2_device_register_subdev_nodes(&rkisp1->v4l2_dev);
+ if (ret)
+ return ret;
+
+ dev_dbg(rkisp1->dev, "Async subdev notifier completed\n");
+
+ return 0;
+}
+
+static const struct v4l2_async_notifier_operations rkisp1_subdev_notifier_ops = {
+ .bound = rkisp1_subdev_notifier_bound,
+ .unbind = rkisp1_subdev_notifier_unbind,
+ .complete = rkisp1_subdev_notifier_complete,
+};
+
+static int rkisp1_subdev_notifier(struct rkisp1_device *rkisp1)
+{
+ struct v4l2_async_notifier *ntf = &rkisp1->notifier;
+ unsigned int next_id = 0;
+ int ret;
+
+ v4l2_async_notifier_init(ntf);
+
+ while (1) {
+ struct v4l2_fwnode_endpoint vep = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY
+ };
+ struct rkisp1_sensor_async *rk_asd = NULL;
+ struct fwnode_handle *ep;
+
+ ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(rkisp1->dev),
+ 0, next_id,
+ FWNODE_GRAPH_ENDPOINT_NEXT);
+ if (!ep)
+ break;
+
+ ret = v4l2_fwnode_endpoint_parse(ep, &vep);
+ if (ret)
+ goto err_parse;
+
+ rk_asd = kzalloc(sizeof(*rk_asd), GFP_KERNEL);
+ if (!rk_asd) {
+ ret = -ENOMEM;
+ goto err_parse;
+ }
+
+ rk_asd->mbus_type = vep.bus_type;
+ rk_asd->mbus_flags = vep.bus.mipi_csi2.flags;
+ rk_asd->lanes = vep.bus.mipi_csi2.num_data_lanes;
+
+ ret = v4l2_async_notifier_add_fwnode_remote_subdev(ntf, ep,
+ &rk_asd->asd);
+ if (ret)
+ goto err_parse;
+
+ dev_dbg(rkisp1->dev, "registered ep id %d with %d lanes\n",
+ vep.base.id, rk_asd->lanes);
+
+ next_id = vep.base.id + 1;
+
+ fwnode_handle_put(ep);
+
+ continue;
+err_parse:
+ fwnode_handle_put(ep);
+ kfree(rk_asd);
+ v4l2_async_notifier_cleanup(ntf);
+ return ret;
+ }
+
+ if (next_id == 0)
+ dev_dbg(rkisp1->dev, "no remote subdevice found\n");
+ ntf->ops = &rkisp1_subdev_notifier_ops;
+ ret = v4l2_async_notifier_register(&rkisp1->v4l2_dev, ntf);
+ if (ret) {
+ v4l2_async_notifier_cleanup(ntf);
+ return ret;
+ }
+ return 0;
+}
+
+/* ----------------------------------------------------------------------------
+ * Power
+ */
+
+static int __maybe_unused rkisp1_runtime_suspend(struct device *dev)
+{
+ struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(rkisp1->clk_size, rkisp1->clks);
+ return pinctrl_pm_select_sleep_state(dev);
+}
+
+static int __maybe_unused rkisp1_runtime_resume(struct device *dev)
+{
+ struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
+ int ret;
+
+ ret = pinctrl_pm_select_default_state(dev);
+ if (ret)
+ return ret;
+ ret = clk_bulk_prepare_enable(rkisp1->clk_size, rkisp1->clks);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct dev_pm_ops rkisp1_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(rkisp1_runtime_suspend, rkisp1_runtime_resume, NULL)
+};
+
+/* ----------------------------------------------------------------------------
+ * Core
+ */
+
+static int rkisp1_entities_register(struct rkisp1_device *rkisp1)
+{
+ int ret;
+
+ ret = rkisp1_isp_register(rkisp1);
+ if (ret)
+ return ret;
+
+ ret = rkisp1_resizer_devs_register(rkisp1);
+ if (ret)
+ goto err_unreg_isp_subdev;
+
+ ret = rkisp1_capture_devs_register(rkisp1);
+ if (ret)
+ goto err_unreg_resizer_devs;
+
+ ret = rkisp1_stats_register(rkisp1);
+ if (ret)
+ goto err_unreg_capture_devs;
+
+ ret = rkisp1_params_register(rkisp1);
+ if (ret)
+ goto err_unreg_stats;
+
+ ret = rkisp1_subdev_notifier(rkisp1);
+ if (ret) {
+ dev_err(rkisp1->dev,
+ "Failed to register subdev notifier(%d)\n", ret);
+ goto err_unreg_params;
+ }
+
+ return 0;
+err_unreg_params:
+ rkisp1_params_unregister(rkisp1);
+err_unreg_stats:
+ rkisp1_stats_unregister(rkisp1);
+err_unreg_capture_devs:
+ rkisp1_capture_devs_unregister(rkisp1);
+err_unreg_resizer_devs:
+ rkisp1_resizer_devs_unregister(rkisp1);
+err_unreg_isp_subdev:
+ rkisp1_isp_unregister(rkisp1);
+ return ret;
+}
+
+static irqreturn_t rkisp1_isr(int irq, void *ctx)
+{
+ struct device *dev = ctx;
+ struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
+
+ /*
+ * Call rkisp1_capture_isr() first to handle the frame that
+ * potentially completed using the current frame_sequence number before
+ * it is potentially incremented by rkisp1_isp_isr() in the vertical
+ * sync.
+ */
+ rkisp1_capture_isr(rkisp1);
+ rkisp1_isp_isr(rkisp1);
+ rkisp1_mipi_isr(rkisp1);
+
+ return IRQ_HANDLED;
+}
+
+static const char * const rk3399_isp_clks[] = {
+ "isp",
+ "aclk",
+ "hclk",
+};
+
+static const struct rkisp1_match_data rk3399_isp_clk_data = {
+ .clks = rk3399_isp_clks,
+ .size = ARRAY_SIZE(rk3399_isp_clks),
+};
+
+static const struct of_device_id rkisp1_of_match[] = {
+ {
+ .compatible = "rockchip,rk3399-cif-isp",
+ .data = &rk3399_isp_clk_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rkisp1_of_match);
+
+static void rkisp1_debug_init(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_debug *debug = &rkisp1->debug;
+
+ debug->debugfs_dir = debugfs_create_dir(RKISP1_DRIVER_NAME, NULL);
+ debugfs_create_ulong("data_loss", 0444, debug->debugfs_dir,
+ &debug->data_loss);
+ debugfs_create_ulong("outform_size_err", 0444, debug->debugfs_dir,
+ &debug->outform_size_error);
+ debugfs_create_ulong("img_stabilization_size_error", 0444,
+ debug->debugfs_dir,
+ &debug->img_stabilization_size_error);
+ debugfs_create_ulong("inform_size_error", 0444, debug->debugfs_dir,
+ &debug->inform_size_error);
+ debugfs_create_ulong("irq_delay", 0444, debug->debugfs_dir,
+ &debug->irq_delay);
+ debugfs_create_ulong("mipi_error", 0444, debug->debugfs_dir,
+ &debug->mipi_error);
+ debugfs_create_ulong("stats_error", 0444, debug->debugfs_dir,
+ &debug->stats_error);
+ debugfs_create_ulong("mp_stop_timeout", 0444, debug->debugfs_dir,
+ &debug->stop_timeout[RKISP1_MAINPATH]);
+ debugfs_create_ulong("sp_stop_timeout", 0444, debug->debugfs_dir,
+ &debug->stop_timeout[RKISP1_SELFPATH]);
+ debugfs_create_ulong("mp_frame_drop", 0444, debug->debugfs_dir,
+ &debug->frame_drop[RKISP1_MAINPATH]);
+ debugfs_create_ulong("sp_frame_drop", 0444, debug->debugfs_dir,
+ &debug->frame_drop[RKISP1_SELFPATH]);
+}
+
+static int rkisp1_probe(struct platform_device *pdev)
+{
+ const struct rkisp1_match_data *clk_data;
+ struct device *dev = &pdev->dev;
+ struct rkisp1_device *rkisp1;
+ struct v4l2_device *v4l2_dev;
+ unsigned int i;
+ int ret, irq;
+
+ clk_data = of_device_get_match_data(&pdev->dev);
+ if (!clk_data)
+ return -ENODEV;
+
+ rkisp1 = devm_kzalloc(dev, sizeof(*rkisp1), GFP_KERNEL);
+ if (!rkisp1)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, rkisp1);
+ rkisp1->dev = dev;
+
+ mutex_init(&rkisp1->stream_lock);
+
+ rkisp1->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rkisp1->base_addr))
+ return PTR_ERR(rkisp1->base_addr);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_irq(dev, irq, rkisp1_isr, IRQF_SHARED,
+ dev_driver_string(dev), dev);
+ if (ret) {
+ dev_err(dev, "request irq failed: %d\n", ret);
+ return ret;
+ }
+
+ rkisp1->irq = irq;
+
+ for (i = 0; i < clk_data->size; i++)
+ rkisp1->clks[i].id = clk_data->clks[i];
+ ret = devm_clk_bulk_get(dev, clk_data->size, rkisp1->clks);
+ if (ret)
+ return ret;
+ rkisp1->clk_size = clk_data->size;
+
+ pm_runtime_enable(&pdev->dev);
+
+ strscpy(rkisp1->media_dev.model, RKISP1_DRIVER_NAME,
+ sizeof(rkisp1->media_dev.model));
+ rkisp1->media_dev.dev = &pdev->dev;
+ strscpy(rkisp1->media_dev.bus_info, RKISP1_BUS_INFO,
+ sizeof(rkisp1->media_dev.bus_info));
+ media_device_init(&rkisp1->media_dev);
+
+ v4l2_dev = &rkisp1->v4l2_dev;
+ v4l2_dev->mdev = &rkisp1->media_dev;
+ strscpy(v4l2_dev->name, RKISP1_DRIVER_NAME, sizeof(v4l2_dev->name));
+
+ ret = v4l2_device_register(rkisp1->dev, &rkisp1->v4l2_dev);
+ if (ret)
+ return ret;
+
+ ret = media_device_register(&rkisp1->media_dev);
+ if (ret) {
+ dev_err(dev, "Failed to register media device: %d\n", ret);
+ goto err_unreg_v4l2_dev;
+ }
+
+ ret = rkisp1_entities_register(rkisp1);
+ if (ret)
+ goto err_unreg_media_dev;
+
+ rkisp1_debug_init(rkisp1);
+
+ return 0;
+
+err_unreg_media_dev:
+ media_device_unregister(&rkisp1->media_dev);
+err_unreg_v4l2_dev:
+ v4l2_device_unregister(&rkisp1->v4l2_dev);
+ pm_runtime_disable(&pdev->dev);
+ return ret;
+}
+
+static int rkisp1_remove(struct platform_device *pdev)
+{
+ struct rkisp1_device *rkisp1 = platform_get_drvdata(pdev);
+
+ v4l2_async_notifier_unregister(&rkisp1->notifier);
+ v4l2_async_notifier_cleanup(&rkisp1->notifier);
+
+ rkisp1_params_unregister(rkisp1);
+ rkisp1_stats_unregister(rkisp1);
+ rkisp1_capture_devs_unregister(rkisp1);
+ rkisp1_resizer_devs_unregister(rkisp1);
+ rkisp1_isp_unregister(rkisp1);
+
+ media_device_unregister(&rkisp1->media_dev);
+ v4l2_device_unregister(&rkisp1->v4l2_dev);
+
+ pm_runtime_disable(&pdev->dev);
+
+ debugfs_remove_recursive(rkisp1->debug.debugfs_dir);
+ return 0;
+}
+
+static struct platform_driver rkisp1_drv = {
+ .driver = {
+ .name = RKISP1_DRIVER_NAME,
+ .of_match_table = of_match_ptr(rkisp1_of_match),
+ .pm = &rkisp1_pm_ops,
+ },
+ .probe = rkisp1_probe,
+ .remove = rkisp1_remove,
+};
+
+module_platform_driver(rkisp1_drv);
+MODULE_DESCRIPTION("Rockchip ISP1 platform driver");
+MODULE_LICENSE("Dual MIT/GPL");
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
new file mode 100644
index 000000000000..889982d8ca41
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
@@ -0,0 +1,1160 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Rockchip ISP1 Driver - ISP Subdevice
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ *
+ * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <linux/iopoll.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-mipi-dphy.h>
+#include <linux/pm_runtime.h>
+#include <linux/videodev2.h>
+#include <linux/vmalloc.h>
+#include <media/v4l2-event.h>
+
+#include "rkisp1-common.h"
+
+#define RKISP1_DEF_SINK_PAD_FMT MEDIA_BUS_FMT_SRGGB10_1X10
+#define RKISP1_DEF_SRC_PAD_FMT MEDIA_BUS_FMT_YUYV8_2X8
+
+#define RKISP1_ISP_DEV_NAME RKISP1_DRIVER_NAME "_isp"
+
+/*
+ * NOTE: MIPI controller and input MUX are also configured in this file.
+ * This is because ISP Subdev describes not only ISP submodule (input size,
+ * format, output size, format), but also a virtual route device.
+ */
+
+/*
+ * There are many variables named with format/frame in below code,
+ * please see here for their meaning.
+ * Cropping in the sink pad defines the image region from the sensor.
+ * Cropping in the source pad defines the region for the Image Stabilizer (IS)
+ *
+ * Cropping regions of ISP
+ *
+ * +---------------------------------------------------------+
+ * | Sensor image |
+ * | +---------------------------------------------------+ |
+ * | | CIF_ISP_ACQ (for black level) | |
+ * | | sink pad format | |
+ * | | +--------------------------------------------+ | |
+ * | | | CIF_ISP_OUT | | |
+ * | | | sink pad crop | | |
+ * | | | +---------------------------------+ | | |
+ * | | | | CIF_ISP_IS | | | |
+ * | | | | source pad crop and format | | | |
+ * | | | +---------------------------------+ | | |
+ * | | +--------------------------------------------+ | |
+ * | +---------------------------------------------------+ |
+ * +---------------------------------------------------------+
+ */
+
+static const struct rkisp1_isp_mbus_info rkisp1_isp_formats[] = {
+ {
+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .direction = RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
+ .bayer_pat = RKISP1_RAW_RGGB,
+ .bus_width = 10,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
+ .bayer_pat = RKISP1_RAW_BGGR,
+ .bus_width = 10,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
+ .bayer_pat = RKISP1_RAW_GBRG,
+ .bus_width = 10,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
+ .bayer_pat = RKISP1_RAW_GRBG,
+ .bus_width = 10,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
+ .bayer_pat = RKISP1_RAW_RGGB,
+ .bus_width = 12,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
+ .bayer_pat = RKISP1_RAW_BGGR,
+ .bus_width = 12,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
+ .bayer_pat = RKISP1_RAW_GBRG,
+ .bus_width = 12,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
+ .bayer_pat = RKISP1_RAW_GRBG,
+ .bus_width = 12,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
+ .bayer_pat = RKISP1_RAW_RGGB,
+ .bus_width = 8,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
+ .bayer_pat = RKISP1_RAW_BGGR,
+ .bus_width = 8,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
+ .bayer_pat = RKISP1_RAW_GBRG,
+ .bus_width = 8,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
+ .pixel_enc = V4L2_PIXEL_ENC_BAYER,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
+ .bayer_pat = RKISP1_RAW_GRBG,
+ .bus_width = 8,
+ .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
+ .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCBYCR,
+ .bus_width = 16,
+ .direction = RKISP1_ISP_SD_SINK,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
+ .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCRYCB,
+ .bus_width = 16,
+ .direction = RKISP1_ISP_SD_SINK,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
+ .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CBYCRY,
+ .bus_width = 16,
+ .direction = RKISP1_ISP_SD_SINK,
+ }, {
+ .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16,
+ .pixel_enc = V4L2_PIXEL_ENC_YUV,
+ .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
+ .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CRYCBY,
+ .bus_width = 16,
+ .direction = RKISP1_ISP_SD_SINK,
+ },
+};
+
+/* ----------------------------------------------------------------------------
+ * Helpers
+ */
+
+const struct rkisp1_isp_mbus_info *rkisp1_isp_mbus_info_get(u32 mbus_code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) {
+ const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i];
+
+ if (fmt->mbus_code == mbus_code)
+ return fmt;
+ }
+
+ return NULL;
+}
+
+static struct v4l2_subdev *rkisp1_get_remote_sensor(struct v4l2_subdev *sd)
+{
+ struct media_pad *local, *remote;
+ struct media_entity *sensor_me;
+
+ local = &sd->entity.pads[RKISP1_ISP_PAD_SINK_VIDEO];
+ remote = media_entity_remote_pad(local);
+ if (!remote)
+ return NULL;
+
+ sensor_me = remote->entity;
+ return media_entity_to_v4l2_subdev(sensor_me);
+}
+
+static struct v4l2_mbus_framefmt *
+rkisp1_isp_get_pad_fmt(struct rkisp1_isp *isp,
+ struct v4l2_subdev_pad_config *cfg,
+ unsigned int pad, u32 which)
+{
+ if (which == V4L2_SUBDEV_FORMAT_TRY)
+ return v4l2_subdev_get_try_format(&isp->sd, cfg, pad);
+ else
+ return v4l2_subdev_get_try_format(&isp->sd, isp->pad_cfg, pad);
+}
+
+static struct v4l2_rect *
+rkisp1_isp_get_pad_crop(struct rkisp1_isp *isp,
+ struct v4l2_subdev_pad_config *cfg,
+ unsigned int pad, u32 which)
+{
+ if (which == V4L2_SUBDEV_FORMAT_TRY)
+ return v4l2_subdev_get_try_crop(&isp->sd, cfg, pad);
+ else
+ return v4l2_subdev_get_try_crop(&isp->sd, isp->pad_cfg, pad);
+}
+
+/* ----------------------------------------------------------------------------
+ * Camera Interface registers configurations
+ */
+
+/*
+ * Image Stabilization.
+ * This should only be called when configuring CIF
+ * or at the frame end interrupt
+ */
+static void rkisp1_config_ism(struct rkisp1_device *rkisp1)
+{
+ struct v4l2_rect *src_crop =
+ rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,
+ RKISP1_ISP_PAD_SOURCE_VIDEO,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ u32 val;
+
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_RECENTER);
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DX);
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DY);
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_DISPLACE);
+ rkisp1_write(rkisp1, src_crop->left, RKISP1_CIF_ISP_IS_H_OFFS);
+ rkisp1_write(rkisp1, src_crop->top, RKISP1_CIF_ISP_IS_V_OFFS);
+ rkisp1_write(rkisp1, src_crop->width, RKISP1_CIF_ISP_IS_H_SIZE);
+ rkisp1_write(rkisp1, src_crop->height, RKISP1_CIF_ISP_IS_V_SIZE);
+
+ /* IS(Image Stabilization) is always on, working as output crop */
+ rkisp1_write(rkisp1, 1, RKISP1_CIF_ISP_IS_CTRL);
+ val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
+ val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD;
+ rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
+}
+
+/*
+ * configure ISP blocks with input format, size......
+ */
+static int rkisp1_config_isp(struct rkisp1_device *rkisp1)
+{
+ u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0;
+ const struct rkisp1_isp_mbus_info *src_fmt, *sink_fmt;
+ struct rkisp1_sensor_async *sensor;
+ struct v4l2_mbus_framefmt *sink_frm;
+ struct v4l2_rect *sink_crop;
+
+ sensor = rkisp1->active_sensor;
+ sink_fmt = rkisp1->isp.sink_fmt;
+ src_fmt = rkisp1->isp.src_fmt;
+ sink_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,
+ RKISP1_ISP_PAD_SINK_VIDEO,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ sink_crop = rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,
+ RKISP1_ISP_PAD_SINK_VIDEO,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+
+ if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ acq_mult = 1;
+ if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ if (sensor->mbus_type == V4L2_MBUS_BT656)
+ isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;
+ else
+ isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
+ } else {
+ rkisp1_write(rkisp1, RKISP1_CIF_ISP_DEMOSAIC_TH(0xc),
+ RKISP1_CIF_ISP_DEMOSAIC);
+
+ if (sensor->mbus_type == V4L2_MBUS_BT656)
+ isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;
+ else
+ isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
+ }
+ } else if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_YUV) {
+ acq_mult = 2;
+ if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
+ isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;
+ } else {
+ if (sensor->mbus_type == V4L2_MBUS_BT656)
+ isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656;
+ else
+ isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;
+ }
+
+ irq_mask |= RKISP1_CIF_ISP_DATA_LOSS;
+ }
+
+ /* Set up input acquisition properties */
+ if (sensor->mbus_type == V4L2_MBUS_BT656 ||
+ sensor->mbus_type == V4L2_MBUS_PARALLEL) {
+ if (sensor->mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
+ signal = RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE;
+ }
+
+ if (sensor->mbus_type == V4L2_MBUS_PARALLEL) {
+ if (sensor->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
+ signal |= RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW;
+
+ if (sensor->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
+ signal |= RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW;
+ }
+
+ rkisp1_write(rkisp1, isp_ctrl, RKISP1_CIF_ISP_CTRL);
+ rkisp1_write(rkisp1, signal | sink_fmt->yuv_seq |
+ RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) |
+ RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL,
+ RKISP1_CIF_ISP_ACQ_PROP);
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_NR_FRAMES);
+
+ /* Acquisition Size */
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_H_OFFS);
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_V_OFFS);
+ rkisp1_write(rkisp1,
+ acq_mult * sink_frm->width, RKISP1_CIF_ISP_ACQ_H_SIZE);
+ rkisp1_write(rkisp1, sink_frm->height, RKISP1_CIF_ISP_ACQ_V_SIZE);
+
+ /* ISP Out Area */
+ rkisp1_write(rkisp1, sink_crop->left, RKISP1_CIF_ISP_OUT_H_OFFS);
+ rkisp1_write(rkisp1, sink_crop->top, RKISP1_CIF_ISP_OUT_V_OFFS);
+ rkisp1_write(rkisp1, sink_crop->width, RKISP1_CIF_ISP_OUT_H_SIZE);
+ rkisp1_write(rkisp1, sink_crop->height, RKISP1_CIF_ISP_OUT_V_SIZE);
+
+ irq_mask |= RKISP1_CIF_ISP_FRAME | RKISP1_CIF_ISP_V_START |
+ RKISP1_CIF_ISP_PIC_SIZE_ERROR;
+ rkisp1_write(rkisp1, irq_mask, RKISP1_CIF_ISP_IMSC);
+
+ if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ rkisp1_params_disable(&rkisp1->params);
+ } else {
+ struct v4l2_mbus_framefmt *src_frm;
+
+ src_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,
+ RKISP1_ISP_PAD_SINK_VIDEO,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ rkisp1_params_configure(&rkisp1->params, sink_fmt->bayer_pat,
+ src_frm->quantization);
+ }
+
+ return 0;
+}
+
+static int rkisp1_config_dvp(struct rkisp1_device *rkisp1)
+{
+ const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
+ u32 val, input_sel;
+
+ switch (sink_fmt->bus_width) {
+ case 8:
+ input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
+ break;
+ case 10:
+ input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
+ break;
+ case 12:
+ input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B;
+ break;
+ default:
+ dev_err(rkisp1->dev, "Invalid bus width\n");
+ return -EINVAL;
+ }
+
+ val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ACQ_PROP);
+ rkisp1_write(rkisp1, val | input_sel, RKISP1_CIF_ISP_ACQ_PROP);
+
+ return 0;
+}
+
+static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
+{
+ const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
+ unsigned int lanes = rkisp1->active_sensor->lanes;
+ u32 mipi_ctrl;
+
+ if (lanes < 1 || lanes > 4)
+ return -EINVAL;
+
+ mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
+ RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
+ RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
+ RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA;
+
+ rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
+
+ /* Configure Data Type and Virtual Channel */
+ rkisp1_write(rkisp1,
+ RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
+ RKISP1_CIF_MIPI_DATA_SEL_VC(0),
+ RKISP1_CIF_MIPI_IMG_DATA_SEL);
+
+ /* Clear MIPI interrupts */
+ rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);
+ /*
+ * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for
+ * isp bus may be dead when switch isp.
+ */
+ rkisp1_write(rkisp1,
+ RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI |
+ RKISP1_CIF_MIPI_ERR_DPHY |
+ RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) |
+ RKISP1_CIF_MIPI_ADD_DATA_OVFLW,
+ RKISP1_CIF_MIPI_IMSC);
+
+ dev_dbg(rkisp1->dev, "\n MIPI_CTRL 0x%08x\n"
+ " MIPI_IMG_DATA_SEL 0x%08x\n"
+ " MIPI_STATUS 0x%08x\n"
+ " MIPI_IMSC 0x%08x\n",
+ rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL),
+ rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL),
+ rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS),
+ rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC));
+
+ return 0;
+}
+
+/* Configure MUX */
+static int rkisp1_config_path(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
+ u32 dpcl = rkisp1_read(rkisp1, RKISP1_CIF_VI_DPCL);
+ int ret = 0;
+
+ if (sensor->mbus_type == V4L2_MBUS_BT656 ||
+ sensor->mbus_type == V4L2_MBUS_PARALLEL) {
+ ret = rkisp1_config_dvp(rkisp1);
+ dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL;
+ } else if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
+ ret = rkisp1_config_mipi(rkisp1);
+ dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_MIPI;
+ }
+
+ rkisp1_write(rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
+
+ return ret;
+}
+
+/* Hardware configure Entry */
+static int rkisp1_config_cif(struct rkisp1_device *rkisp1)
+{
+ u32 cif_id;
+ int ret;
+
+ cif_id = rkisp1_read(rkisp1, RKISP1_CIF_VI_ID);
+ dev_dbg(rkisp1->dev, "CIF_ID 0x%08x\n", cif_id);
+
+ ret = rkisp1_config_isp(rkisp1);
+ if (ret)
+ return ret;
+ ret = rkisp1_config_path(rkisp1);
+ if (ret)
+ return ret;
+ rkisp1_config_ism(rkisp1);
+
+ return 0;
+}
+
+static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)
+{
+ u32 val;
+
+ /*
+ * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
+ * Stop ISP(isp) ->wait for ISP isp off
+ */
+ /* stop and clear MI, MIPI, and ISP interrupts */
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_MIPI_IMSC);
+ rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);
+
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IMSC);
+ rkisp1_write(rkisp1, ~0, RKISP1_CIF_ISP_ICR);
+
+ rkisp1_write(rkisp1, 0, RKISP1_CIF_MI_IMSC);
+ rkisp1_write(rkisp1, ~0, RKISP1_CIF_MI_ICR);
+ val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
+ rkisp1_write(rkisp1, val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA),
+ RKISP1_CIF_MIPI_CTRL);
+ /* stop ISP */
+ val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
+ val &= ~(RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE |
+ RKISP1_CIF_ISP_CTRL_ISP_ENABLE);
+ rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
+
+ val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
+ rkisp1_write(rkisp1, val | RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD,
+ RKISP1_CIF_ISP_CTRL);
+
+ readx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS,
+ val, val & RKISP1_CIF_ISP_OFF, 20, 100);
+ rkisp1_write(rkisp1,
+ RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST,
+ RKISP1_CIF_IRCL);
+ rkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL);
+}
+
+static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
+{
+ u32 val = RKISP1_CIF_ICCL_ISP_CLK | RKISP1_CIF_ICCL_CP_CLK |
+ RKISP1_CIF_ICCL_MRSZ_CLK | RKISP1_CIF_ICCL_SRSZ_CLK |
+ RKISP1_CIF_ICCL_JPEG_CLK | RKISP1_CIF_ICCL_MI_CLK |
+ RKISP1_CIF_ICCL_IE_CLK | RKISP1_CIF_ICCL_MIPI_CLK |
+ RKISP1_CIF_ICCL_DCROP_CLK;
+
+ rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
+}
+
+static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
+ u32 val;
+
+ rkisp1_config_clk(rkisp1);
+
+ /* Activate MIPI */
+ if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
+ val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
+ rkisp1_write(rkisp1, val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA,
+ RKISP1_CIF_MIPI_CTRL);
+ }
+ /* Activate ISP */
+ val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
+ val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD |
+ RKISP1_CIF_ISP_CTRL_ISP_ENABLE |
+ RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE;
+ rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
+
+ /*
+ * CIF spec says to wait for sufficient time after enabling
+ * the MIPI interface and before starting the sensor output.
+ */
+ usleep_range(1000, 1200);
+}
+
+/* ----------------------------------------------------------------------------
+ * Subdev pad operations
+ */
+
+static int rkisp1_isp_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ unsigned int i, dir;
+ int pos = 0;
+
+ if (code->pad == RKISP1_ISP_PAD_SINK_VIDEO) {
+ dir = RKISP1_ISP_SD_SINK;
+ } else if (code->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) {
+ dir = RKISP1_ISP_SD_SRC;
+ } else {
+ if (code->index > 0)
+ return -EINVAL;
+ code->code = MEDIA_BUS_FMT_METADATA_FIXED;
+ return 0;
+ }
+
+ if (code->index >= ARRAY_SIZE(rkisp1_isp_formats))
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) {
+ const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i];
+
+ if (fmt->direction & dir)
+ pos++;
+
+ if (code->index == pos - 1) {
+ code->code = fmt->mbus_code;
+ if (fmt->pixel_enc == V4L2_PIXEL_ENC_YUV &&
+ dir == RKISP1_ISP_SD_SRC)
+ code->flags =
+ V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int rkisp1_isp_init_config(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg)
+{
+ struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+ struct v4l2_rect *sink_crop, *src_crop;
+
+ sink_fmt = v4l2_subdev_get_try_format(sd, cfg,
+ RKISP1_ISP_PAD_SINK_VIDEO);
+ sink_fmt->width = RKISP1_DEFAULT_WIDTH;
+ sink_fmt->height = RKISP1_DEFAULT_HEIGHT;
+ sink_fmt->field = V4L2_FIELD_NONE;
+ sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT;
+
+ sink_crop = v4l2_subdev_get_try_crop(sd, cfg,
+ RKISP1_ISP_PAD_SINK_VIDEO);
+ sink_crop->width = RKISP1_DEFAULT_WIDTH;
+ sink_crop->height = RKISP1_DEFAULT_HEIGHT;
+ sink_crop->left = 0;
+ sink_crop->top = 0;
+
+ src_fmt = v4l2_subdev_get_try_format(sd, cfg,
+ RKISP1_ISP_PAD_SOURCE_VIDEO);
+ *src_fmt = *sink_fmt;
+ src_fmt->code = RKISP1_DEF_SRC_PAD_FMT;
+
+ src_crop = v4l2_subdev_get_try_crop(sd, cfg,
+ RKISP1_ISP_PAD_SOURCE_VIDEO);
+ *src_crop = *sink_crop;
+
+ sink_fmt = v4l2_subdev_get_try_format(sd, cfg,
+ RKISP1_ISP_PAD_SINK_PARAMS);
+ src_fmt = v4l2_subdev_get_try_format(sd, cfg,
+ RKISP1_ISP_PAD_SOURCE_STATS);
+ sink_fmt->width = 0;
+ sink_fmt->height = 0;
+ sink_fmt->field = V4L2_FIELD_NONE;
+ sink_fmt->code = MEDIA_BUS_FMT_METADATA_FIXED;
+ *src_fmt = *sink_fmt;
+
+ return 0;
+}
+
+static void rkisp1_isp_set_src_fmt(struct rkisp1_isp *isp,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_mbus_framefmt *format,
+ unsigned int which)
+{
+ const struct rkisp1_isp_mbus_info *mbus_info;
+ struct v4l2_mbus_framefmt *src_fmt;
+ const struct v4l2_rect *src_crop;
+
+ src_fmt = rkisp1_isp_get_pad_fmt(isp, cfg,
+ RKISP1_ISP_PAD_SOURCE_VIDEO, which);
+ src_crop = rkisp1_isp_get_pad_crop(isp, cfg,
+ RKISP1_ISP_PAD_SOURCE_VIDEO, which);
+
+ src_fmt->code = format->code;
+ mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
+ if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SRC)) {
+ src_fmt->code = RKISP1_DEF_SRC_PAD_FMT;
+ mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
+ }
+ if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ isp->src_fmt = mbus_info;
+ src_fmt->width = src_crop->width;
+ src_fmt->height = src_crop->height;
+
+ /*
+ * The CSC API is used to allow userspace to force full
+ * quantization on YUV formats.
+ */
+ if (format->flags & V4L2_MBUS_FRAMEFMT_SET_CSC &&
+ format->quantization == V4L2_QUANTIZATION_FULL_RANGE &&
+ mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
+ src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+ else if (mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
+ src_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
+ else
+ src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+
+ *format = *src_fmt;
+}
+
+static void rkisp1_isp_set_src_crop(struct rkisp1_isp *isp,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_rect *r, unsigned int which)
+{
+ struct v4l2_mbus_framefmt *src_fmt;
+ const struct v4l2_rect *sink_crop;
+ struct v4l2_rect *src_crop;
+
+ src_crop = rkisp1_isp_get_pad_crop(isp, cfg,
+ RKISP1_ISP_PAD_SOURCE_VIDEO,
+ which);
+ sink_crop = rkisp1_isp_get_pad_crop(isp, cfg,
+ RKISP1_ISP_PAD_SINK_VIDEO,
+ which);
+
+ src_crop->left = ALIGN(r->left, 2);
+ src_crop->width = ALIGN(r->width, 2);
+ src_crop->top = r->top;
+ src_crop->height = r->height;
+ rkisp1_sd_adjust_crop_rect(src_crop, sink_crop);
+
+ *r = *src_crop;
+
+ /* Propagate to out format */
+ src_fmt = rkisp1_isp_get_pad_fmt(isp, cfg,
+ RKISP1_ISP_PAD_SOURCE_VIDEO, which);
+ rkisp1_isp_set_src_fmt(isp, cfg, src_fmt, which);
+}
+
+static void rkisp1_isp_set_sink_crop(struct rkisp1_isp *isp,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_rect *r, unsigned int which)
+{
+ struct v4l2_rect *sink_crop, *src_crop;
+ struct v4l2_mbus_framefmt *sink_fmt;
+
+ sink_crop = rkisp1_isp_get_pad_crop(isp, cfg, RKISP1_ISP_PAD_SINK_VIDEO,
+ which);
+ sink_fmt = rkisp1_isp_get_pad_fmt(isp, cfg, RKISP1_ISP_PAD_SINK_VIDEO,
+ which);
+
+ sink_crop->left = ALIGN(r->left, 2);
+ sink_crop->width = ALIGN(r->width, 2);
+ sink_crop->top = r->top;
+ sink_crop->height = r->height;
+ rkisp1_sd_adjust_crop(sink_crop, sink_fmt);
+
+ *r = *sink_crop;
+
+ /* Propagate to out crop */
+ src_crop = rkisp1_isp_get_pad_crop(isp, cfg,
+ RKISP1_ISP_PAD_SOURCE_VIDEO, which);
+ rkisp1_isp_set_src_crop(isp, cfg, src_crop, which);
+}
+
+static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_mbus_framefmt *format,
+ unsigned int which)
+{
+ const struct rkisp1_isp_mbus_info *mbus_info;
+ struct v4l2_mbus_framefmt *sink_fmt;
+ struct v4l2_rect *sink_crop;
+
+ sink_fmt = rkisp1_isp_get_pad_fmt(isp, cfg, RKISP1_ISP_PAD_SINK_VIDEO,
+ which);
+ sink_fmt->code = format->code;
+ mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
+ if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) {
+ sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT;
+ mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
+ }
+ if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ isp->sink_fmt = mbus_info;
+
+ sink_fmt->width = clamp_t(u32, format->width,
+ RKISP1_ISP_MIN_WIDTH,
+ RKISP1_ISP_MAX_WIDTH);
+ sink_fmt->height = clamp_t(u32, format->height,
+ RKISP1_ISP_MIN_HEIGHT,
+ RKISP1_ISP_MAX_HEIGHT);
+
+ *format = *sink_fmt;
+
+ /* Propagate to in crop */
+ sink_crop = rkisp1_isp_get_pad_crop(isp, cfg, RKISP1_ISP_PAD_SINK_VIDEO,
+ which);
+ rkisp1_isp_set_sink_crop(isp, cfg, sink_crop, which);
+}
+
+static int rkisp1_isp_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
+
+ mutex_lock(&isp->ops_lock);
+ fmt->format = *rkisp1_isp_get_pad_fmt(isp, cfg, fmt->pad, fmt->which);
+ mutex_unlock(&isp->ops_lock);
+ return 0;
+}
+
+static int rkisp1_isp_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
+
+ mutex_lock(&isp->ops_lock);
+ if (fmt->pad == RKISP1_ISP_PAD_SINK_VIDEO)
+ rkisp1_isp_set_sink_fmt(isp, cfg, &fmt->format, fmt->which);
+ else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
+ rkisp1_isp_set_src_fmt(isp, cfg, &fmt->format, fmt->which);
+ else
+ fmt->format = *rkisp1_isp_get_pad_fmt(isp, cfg, fmt->pad,
+ fmt->which);
+
+ mutex_unlock(&isp->ops_lock);
+ return 0;
+}
+
+static int rkisp1_isp_get_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
+ int ret = 0;
+
+ if (sel->pad != RKISP1_ISP_PAD_SOURCE_VIDEO &&
+ sel->pad != RKISP1_ISP_PAD_SINK_VIDEO)
+ return -EINVAL;
+
+ mutex_lock(&isp->ops_lock);
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO) {
+ struct v4l2_mbus_framefmt *fmt;
+
+ fmt = rkisp1_isp_get_pad_fmt(isp, cfg, sel->pad,
+ sel->which);
+ sel->r.height = fmt->height;
+ sel->r.width = fmt->width;
+ sel->r.left = 0;
+ sel->r.top = 0;
+ } else {
+ sel->r = *rkisp1_isp_get_pad_crop(isp, cfg,
+ RKISP1_ISP_PAD_SINK_VIDEO,
+ sel->which);
+ }
+ break;
+ case V4L2_SEL_TGT_CROP:
+ sel->r = *rkisp1_isp_get_pad_crop(isp, cfg, sel->pad,
+ sel->which);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ mutex_unlock(&isp->ops_lock);
+ return ret;
+}
+
+static int rkisp1_isp_set_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct rkisp1_device *rkisp1 =
+ container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
+ struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
+ int ret = 0;
+
+ if (sel->target != V4L2_SEL_TGT_CROP)
+ return -EINVAL;
+
+ dev_dbg(rkisp1->dev, "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__,
+ sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height);
+ mutex_lock(&isp->ops_lock);
+ if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO)
+ rkisp1_isp_set_sink_crop(isp, cfg, &sel->r, sel->which);
+ else if (sel->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
+ rkisp1_isp_set_src_crop(isp, cfg, &sel->r, sel->which);
+ else
+ ret = -EINVAL;
+
+ mutex_unlock(&isp->ops_lock);
+ return ret;
+}
+
+static int rkisp1_subdev_link_validate(struct media_link *link)
+{
+ if (link->sink->index == RKISP1_ISP_PAD_SINK_PARAMS)
+ return 0;
+
+ return v4l2_subdev_link_validate(link);
+}
+
+static const struct v4l2_subdev_pad_ops rkisp1_isp_pad_ops = {
+ .enum_mbus_code = rkisp1_isp_enum_mbus_code,
+ .get_selection = rkisp1_isp_get_selection,
+ .set_selection = rkisp1_isp_set_selection,
+ .init_cfg = rkisp1_isp_init_config,
+ .get_fmt = rkisp1_isp_get_fmt,
+ .set_fmt = rkisp1_isp_set_fmt,
+ .link_validate = v4l2_subdev_link_validate_default,
+};
+
+/* ----------------------------------------------------------------------------
+ * Stream operations
+ */
+
+static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
+ struct rkisp1_sensor_async *sensor)
+{
+ struct rkisp1_device *rkisp1 =
+ container_of(isp->sd.v4l2_dev, struct rkisp1_device, v4l2_dev);
+ union phy_configure_opts opts;
+ struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
+ s64 pixel_clock;
+
+ if (!sensor->pixel_rate_ctrl) {
+ dev_warn(rkisp1->dev, "No pixel rate control in sensor subdev\n");
+ return -EPIPE;
+ }
+
+ pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl);
+ if (!pixel_clock) {
+ dev_err(rkisp1->dev, "Invalid pixel rate value\n");
+ return -EINVAL;
+ }
+
+ phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
+ sensor->lanes, cfg);
+ phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
+ phy_configure(sensor->dphy, &opts);
+ phy_power_on(sensor->dphy);
+
+ return 0;
+}
+
+static void rkisp1_mipi_csi2_stop(struct rkisp1_sensor_async *sensor)
+{
+ phy_power_off(sensor->dphy);
+}
+
+static int rkisp1_isp_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct rkisp1_device *rkisp1 =
+ container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
+ struct rkisp1_isp *isp = &rkisp1->isp;
+ struct v4l2_subdev *sensor_sd;
+ int ret = 0;
+
+ if (!enable) {
+ rkisp1_isp_stop(rkisp1);
+ rkisp1_mipi_csi2_stop(rkisp1->active_sensor);
+ return 0;
+ }
+
+ sensor_sd = rkisp1_get_remote_sensor(sd);
+ if (!sensor_sd) {
+ dev_warn(rkisp1->dev, "No link between isp and sensor\n");
+ return -ENODEV;
+ }
+
+ rkisp1->active_sensor = container_of(sensor_sd->asd,
+ struct rkisp1_sensor_async, asd);
+
+ if (rkisp1->active_sensor->mbus_type != V4L2_MBUS_CSI2_DPHY)
+ return -EINVAL;
+
+ rkisp1->isp.frame_sequence = -1;
+ mutex_lock(&isp->ops_lock);
+ ret = rkisp1_config_cif(rkisp1);
+ if (ret)
+ goto mutex_unlock;
+
+ ret = rkisp1_mipi_csi2_start(&rkisp1->isp, rkisp1->active_sensor);
+ if (ret)
+ goto mutex_unlock;
+
+ rkisp1_isp_start(rkisp1);
+
+mutex_unlock:
+ mutex_unlock(&isp->ops_lock);
+ return ret;
+}
+
+static int rkisp1_isp_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
+ struct v4l2_event_subscription *sub)
+{
+ if (sub->type != V4L2_EVENT_FRAME_SYNC)
+ return -EINVAL;
+
+ /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */
+ if (sub->id != 0)
+ return -EINVAL;
+
+ return v4l2_event_subscribe(fh, sub, 0, NULL);
+}
+
+static const struct media_entity_operations rkisp1_isp_media_ops = {
+ .link_validate = rkisp1_subdev_link_validate,
+};
+
+static const struct v4l2_subdev_video_ops rkisp1_isp_video_ops = {
+ .s_stream = rkisp1_isp_s_stream,
+};
+
+static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = {
+ .subscribe_event = rkisp1_isp_subs_evt,
+ .unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+static const struct v4l2_subdev_ops rkisp1_isp_ops = {
+ .core = &rkisp1_isp_core_ops,
+ .video = &rkisp1_isp_video_ops,
+ .pad = &rkisp1_isp_pad_ops,
+};
+
+int rkisp1_isp_register(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_isp *isp = &rkisp1->isp;
+ struct media_pad *pads = isp->pads;
+ struct v4l2_subdev *sd = &isp->sd;
+ int ret;
+
+ v4l2_subdev_init(sd, &rkisp1_isp_ops);
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
+ sd->entity.ops = &rkisp1_isp_media_ops;
+ sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
+ sd->owner = THIS_MODULE;
+ strscpy(sd->name, RKISP1_ISP_DEV_NAME, sizeof(sd->name));
+
+ pads[RKISP1_ISP_PAD_SINK_VIDEO].flags = MEDIA_PAD_FL_SINK |
+ MEDIA_PAD_FL_MUST_CONNECT;
+ pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
+ pads[RKISP1_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE;
+ pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
+
+ isp->sink_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SINK_PAD_FMT);
+ isp->src_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SRC_PAD_FMT);
+
+ mutex_init(&isp->ops_lock);
+ ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX, pads);
+ if (ret)
+ return ret;
+
+ ret = v4l2_device_register_subdev(&rkisp1->v4l2_dev, sd);
+ if (ret) {
+ dev_err(rkisp1->dev, "Failed to register isp subdev\n");
+ goto err_cleanup_media_entity;
+ }
+
+ rkisp1_isp_init_config(sd, rkisp1->isp.pad_cfg);
+ return 0;
+
+err_cleanup_media_entity:
+ media_entity_cleanup(&sd->entity);
+
+ return ret;
+}
+
+void rkisp1_isp_unregister(struct rkisp1_device *rkisp1)
+{
+ struct v4l2_subdev *sd = &rkisp1->isp.sd;
+
+ v4l2_device_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+}
+
+/* ----------------------------------------------------------------------------
+ * Interrupt handlers
+ */
+
+void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
+{
+ u32 val, status;
+
+ status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
+ if (!status)
+ return;
+
+ rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR);
+
+ /*
+ * Disable DPHY errctrl interrupt, because this dphy
+ * erctrl signal is asserted until the next changes
+ * of line state. This time is may be too long and cpu
+ * is hold in this interrupt.
+ */
+ if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) {
+ val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
+ rkisp1_write(rkisp1, val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f),
+ RKISP1_CIF_MIPI_IMSC);
+ rkisp1->isp.is_dphy_errctrl_disabled = true;
+ }
+
+ /*
+ * Enable DPHY errctrl interrupt again, if mipi have receive
+ * the whole frame without any error.
+ */
+ if (status == RKISP1_CIF_MIPI_FRAME_END) {
+ /*
+ * Enable DPHY errctrl interrupt again, if mipi have receive
+ * the whole frame without any error.
+ */
+ if (rkisp1->isp.is_dphy_errctrl_disabled) {
+ val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
+ val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f);
+ rkisp1_write(rkisp1, val, RKISP1_CIF_MIPI_IMSC);
+ rkisp1->isp.is_dphy_errctrl_disabled = false;
+ }
+ } else {
+ rkisp1->debug.mipi_error++;
+ }
+}
+
+static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
+{
+ struct v4l2_event event = {
+ .type = V4L2_EVENT_FRAME_SYNC,
+ };
+ event.u.frame_sync.frame_sequence = isp->frame_sequence;
+
+ v4l2_event_queue(isp->sd.devnode, &event);
+}
+
+void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
+{
+ u32 status, isp_err;
+
+ status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS);
+ if (!status)
+ return;
+
+ rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR);
+
+ /* Vertical sync signal, starting generating new frame */
+ if (status & RKISP1_CIF_ISP_V_START) {
+ rkisp1->isp.frame_sequence++;
+ rkisp1_isp_queue_event_sof(&rkisp1->isp);
+ if (status & RKISP1_CIF_ISP_FRAME) {
+ WARN_ONCE(1, "irq delay is too long, buffers might not be in sync\n");
+ rkisp1->debug.irq_delay++;
+ }
+ }
+ if (status & RKISP1_CIF_ISP_PIC_SIZE_ERROR) {
+ /* Clear pic_size_error */
+ isp_err = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ERR);
+ if (isp_err & RKISP1_CIF_ISP_ERR_INFORM_SIZE)
+ rkisp1->debug.inform_size_error++;
+ if (isp_err & RKISP1_CIF_ISP_ERR_IS_SIZE)
+ rkisp1->debug.img_stabilization_size_error++;
+ if (isp_err & RKISP1_CIF_ISP_ERR_OUTFORM_SIZE)
+ rkisp1->debug.outform_size_error++;
+ rkisp1_write(rkisp1, isp_err, RKISP1_CIF_ISP_ERR_CLR);
+ } else if (status & RKISP1_CIF_ISP_DATA_LOSS) {
+ /* keep track of data_loss in debugfs */
+ rkisp1->debug.data_loss++;
+ }
+
+ if (status & RKISP1_CIF_ISP_FRAME) {
+ u32 isp_ris;
+
+ /* New frame from the sensor received */
+ isp_ris = rkisp1_read(rkisp1, RKISP1_CIF_ISP_RIS);
+ if (isp_ris & RKISP1_STATS_MEAS_MASK)
+ rkisp1_stats_isr(&rkisp1->stats, isp_ris);
+ /*
+ * Then update changed configs. Some of them involve
+ * lot of register writes. Do those only one per frame.
+ * Do the updates in the order of the processing flow.
+ */
+ rkisp1_params_isr(rkisp1);
+ }
+}
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
new file mode 100644
index 000000000000..6af4d551ffb5
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-params.c
@@ -0,0 +1,1572 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Rockchip ISP1 Driver - Params subdevice
+ *
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-vmalloc.h> /* for ISP params */
+
+#include "rkisp1-common.h"
+
+#define RKISP1_PARAMS_DEV_NAME RKISP1_DRIVER_NAME "_params"
+
+#define RKISP1_ISP_PARAMS_REQ_BUFS_MIN 2
+#define RKISP1_ISP_PARAMS_REQ_BUFS_MAX 8
+
+#define RKISP1_ISP_DPCC_LINE_THRESH(n) \
+ (RKISP1_CIF_ISP_DPCC_LINE_THRESH_1 + 0x14 * (n))
+#define RKISP1_ISP_DPCC_LINE_MAD_FAC(n) \
+ (RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_1 + 0x14 * (n))
+#define RKISP1_ISP_DPCC_PG_FAC(n) \
+ (RKISP1_CIF_ISP_DPCC_PG_FAC_1 + 0x14 * (n))
+#define RKISP1_ISP_DPCC_RND_THRESH(n) \
+ (RKISP1_CIF_ISP_DPCC_RND_THRESH_1 + 0x14 * (n))
+#define RKISP1_ISP_DPCC_RG_FAC(n) \
+ (RKISP1_CIF_ISP_DPCC_RG_FAC_1 + 0x14 * (n))
+#define RKISP1_ISP_CC_COEFF(n) \
+ (RKISP1_CIF_ISP_CC_COEFF_0 + (n) * 4)
+
+static inline void
+rkisp1_param_set_bits(struct rkisp1_params *params, u32 reg, u32 bit_mask)
+{
+ u32 val;
+
+ val = rkisp1_read(params->rkisp1, reg);
+ rkisp1_write(params->rkisp1, val | bit_mask, reg);
+}
+
+static inline void
+rkisp1_param_clear_bits(struct rkisp1_params *params, u32 reg, u32 bit_mask)
+{
+ u32 val;
+
+ val = rkisp1_read(params->rkisp1, reg);
+ rkisp1_write(params->rkisp1, val & ~bit_mask, reg);
+}
+
+/* ISP BP interface function */
+static void rkisp1_dpcc_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_dpcc_config *arg)
+{
+ unsigned int i;
+ u32 mode;
+
+ /* avoid to override the old enable value */
+ mode = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_DPCC_MODE);
+ mode &= RKISP1_CIF_ISP_DPCC_ENA;
+ mode |= arg->mode & ~RKISP1_CIF_ISP_DPCC_ENA;
+ rkisp1_write(params->rkisp1, mode, RKISP1_CIF_ISP_DPCC_MODE);
+ rkisp1_write(params->rkisp1, arg->output_mode,
+ RKISP1_CIF_ISP_DPCC_OUTPUT_MODE);
+ rkisp1_write(params->rkisp1, arg->set_use,
+ RKISP1_CIF_ISP_DPCC_SET_USE);
+
+ rkisp1_write(params->rkisp1, arg->methods[0].method,
+ RKISP1_CIF_ISP_DPCC_METHODS_SET_1);
+ rkisp1_write(params->rkisp1, arg->methods[1].method,
+ RKISP1_CIF_ISP_DPCC_METHODS_SET_2);
+ rkisp1_write(params->rkisp1, arg->methods[2].method,
+ RKISP1_CIF_ISP_DPCC_METHODS_SET_3);
+ for (i = 0; i < RKISP1_CIF_ISP_DPCC_METHODS_MAX; i++) {
+ rkisp1_write(params->rkisp1, arg->methods[i].line_thresh,
+ RKISP1_ISP_DPCC_LINE_THRESH(i));
+ rkisp1_write(params->rkisp1, arg->methods[i].line_mad_fac,
+ RKISP1_ISP_DPCC_LINE_MAD_FAC(i));
+ rkisp1_write(params->rkisp1, arg->methods[i].pg_fac,
+ RKISP1_ISP_DPCC_PG_FAC(i));
+ rkisp1_write(params->rkisp1, arg->methods[i].rnd_thresh,
+ RKISP1_ISP_DPCC_RND_THRESH(i));
+ rkisp1_write(params->rkisp1, arg->methods[i].rg_fac,
+ RKISP1_ISP_DPCC_RG_FAC(i));
+ }
+
+ rkisp1_write(params->rkisp1, arg->rnd_offs,
+ RKISP1_CIF_ISP_DPCC_RND_OFFS);
+ rkisp1_write(params->rkisp1, arg->ro_limits,
+ RKISP1_CIF_ISP_DPCC_RO_LIMITS);
+}
+
+/* ISP black level subtraction interface function */
+static void rkisp1_bls_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_bls_config *arg)
+{
+ /* avoid to override the old enable value */
+ u32 new_control;
+
+ new_control = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_BLS_CTRL);
+ new_control &= RKISP1_CIF_ISP_BLS_ENA;
+ /* fixed subtraction values */
+ if (!arg->enable_auto) {
+ const struct rkisp1_cif_isp_bls_fixed_val *pval =
+ &arg->fixed_val;
+
+ switch (params->raw_type) {
+ case RKISP1_RAW_BGGR:
+ rkisp1_write(params->rkisp1,
+ pval->r, RKISP1_CIF_ISP_BLS_D_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->gr, RKISP1_CIF_ISP_BLS_C_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->gb, RKISP1_CIF_ISP_BLS_B_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->b, RKISP1_CIF_ISP_BLS_A_FIXED);
+ break;
+ case RKISP1_RAW_GBRG:
+ rkisp1_write(params->rkisp1,
+ pval->r, RKISP1_CIF_ISP_BLS_C_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->gr, RKISP1_CIF_ISP_BLS_D_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->gb, RKISP1_CIF_ISP_BLS_A_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->b, RKISP1_CIF_ISP_BLS_B_FIXED);
+ break;
+ case RKISP1_RAW_GRBG:
+ rkisp1_write(params->rkisp1,
+ pval->r, RKISP1_CIF_ISP_BLS_B_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->gr, RKISP1_CIF_ISP_BLS_A_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->gb, RKISP1_CIF_ISP_BLS_D_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->b, RKISP1_CIF_ISP_BLS_C_FIXED);
+ break;
+ case RKISP1_RAW_RGGB:
+ rkisp1_write(params->rkisp1,
+ pval->r, RKISP1_CIF_ISP_BLS_A_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->gr, RKISP1_CIF_ISP_BLS_B_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->gb, RKISP1_CIF_ISP_BLS_C_FIXED);
+ rkisp1_write(params->rkisp1,
+ pval->b, RKISP1_CIF_ISP_BLS_D_FIXED);
+ break;
+ default:
+ break;
+ }
+
+ } else {
+ if (arg->en_windows & BIT(1)) {
+ rkisp1_write(params->rkisp1, arg->bls_window2.h_offs,
+ RKISP1_CIF_ISP_BLS_H2_START);
+ rkisp1_write(params->rkisp1, arg->bls_window2.h_size,
+ RKISP1_CIF_ISP_BLS_H2_STOP);
+ rkisp1_write(params->rkisp1, arg->bls_window2.v_offs,
+ RKISP1_CIF_ISP_BLS_V2_START);
+ rkisp1_write(params->rkisp1, arg->bls_window2.v_size,
+ RKISP1_CIF_ISP_BLS_V2_STOP);
+ new_control |= RKISP1_CIF_ISP_BLS_WINDOW_2;
+ }
+
+ if (arg->en_windows & BIT(0)) {
+ rkisp1_write(params->rkisp1, arg->bls_window1.h_offs,
+ RKISP1_CIF_ISP_BLS_H1_START);
+ rkisp1_write(params->rkisp1, arg->bls_window1.h_size,
+ RKISP1_CIF_ISP_BLS_H1_STOP);
+ rkisp1_write(params->rkisp1, arg->bls_window1.v_offs,
+ RKISP1_CIF_ISP_BLS_V1_START);
+ rkisp1_write(params->rkisp1, arg->bls_window1.v_size,
+ RKISP1_CIF_ISP_BLS_V1_STOP);
+ new_control |= RKISP1_CIF_ISP_BLS_WINDOW_1;
+ }
+
+ rkisp1_write(params->rkisp1, arg->bls_samples,
+ RKISP1_CIF_ISP_BLS_SAMPLES);
+
+ new_control |= RKISP1_CIF_ISP_BLS_MODE_MEASURED;
+ }
+ rkisp1_write(params->rkisp1, new_control, RKISP1_CIF_ISP_BLS_CTRL);
+}
+
+/* ISP LS correction interface function */
+static void
+rkisp1_lsc_correct_matrix_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_lsc_config *pconfig)
+{
+ unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel, i, j, data;
+
+ isp_lsc_status = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_STATUS);
+
+ /* RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
+ sram_addr = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
+ RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_0 :
+ RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153;
+ rkisp1_write(params->rkisp1, sram_addr,
+ RKISP1_CIF_ISP_LSC_R_TABLE_ADDR);
+ rkisp1_write(params->rkisp1, sram_addr,
+ RKISP1_CIF_ISP_LSC_GR_TABLE_ADDR);
+ rkisp1_write(params->rkisp1, sram_addr,
+ RKISP1_CIF_ISP_LSC_GB_TABLE_ADDR);
+ rkisp1_write(params->rkisp1, sram_addr,
+ RKISP1_CIF_ISP_LSC_B_TABLE_ADDR);
+
+ /* program data tables (table size is 9 * 17 = 153) */
+ for (i = 0; i < RKISP1_CIF_ISP_LSC_SAMPLES_MAX; i++) {
+ /*
+ * 17 sectors with 2 values in one DWORD = 9
+ * DWORDs (2nd value of last DWORD unused)
+ */
+ for (j = 0; j < RKISP1_CIF_ISP_LSC_SAMPLES_MAX - 1; j += 2) {
+ data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j],
+ pconfig->r_data_tbl[i][j + 1]);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
+
+ data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j],
+ pconfig->gr_data_tbl[i][j + 1]);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
+
+ data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j],
+ pconfig->gb_data_tbl[i][j + 1]);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
+
+ data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j],
+ pconfig->b_data_tbl[i][j + 1]);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
+ }
+ data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i][j], 0);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_R_TABLE_DATA);
+
+ data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i][j], 0);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_GR_TABLE_DATA);
+
+ data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i][j], 0);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_GB_TABLE_DATA);
+
+ data = RKISP1_CIF_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i][j], 0);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_B_TABLE_DATA);
+ }
+ isp_lsc_table_sel = (isp_lsc_status & RKISP1_CIF_ISP_LSC_ACTIVE_TABLE) ?
+ RKISP1_CIF_ISP_LSC_TABLE_0 :
+ RKISP1_CIF_ISP_LSC_TABLE_1;
+ rkisp1_write(params->rkisp1, isp_lsc_table_sel,
+ RKISP1_CIF_ISP_LSC_TABLE_SEL);
+}
+
+static void rkisp1_lsc_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_lsc_config *arg)
+{
+ unsigned int i, data;
+ u32 lsc_ctrl;
+
+ /* To config must be off , store the current status firstly */
+ lsc_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_LSC_CTRL);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_LSC_CTRL,
+ RKISP1_CIF_ISP_LSC_CTRL_ENA);
+ rkisp1_lsc_correct_matrix_config(params, arg);
+
+ for (i = 0; i < RKISP1_CIF_ISP_LSC_SECTORS_TBL_SIZE / 2; i++) {
+ /* program x size tables */
+ data = RKISP1_CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2],
+ arg->x_size_tbl[i * 2 + 1]);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_XSIZE_01 + i * 4);
+
+ /* program x grad tables */
+ data = RKISP1_CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2],
+ arg->x_grad_tbl[i * 2 + 1]);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_XGRAD_01 + i * 4);
+
+ /* program y size tables */
+ data = RKISP1_CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2],
+ arg->y_size_tbl[i * 2 + 1]);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_YSIZE_01 + i * 4);
+
+ /* program y grad tables */
+ data = RKISP1_CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2],
+ arg->y_grad_tbl[i * 2 + 1]);
+ rkisp1_write(params->rkisp1, data,
+ RKISP1_CIF_ISP_LSC_YGRAD_01 + i * 4);
+ }
+
+ /* restore the lsc ctrl status */
+ if (lsc_ctrl & RKISP1_CIF_ISP_LSC_CTRL_ENA) {
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_LSC_CTRL,
+ RKISP1_CIF_ISP_LSC_CTRL_ENA);
+ } else {
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_LSC_CTRL,
+ RKISP1_CIF_ISP_LSC_CTRL_ENA);
+ }
+}
+
+/* ISP Filtering function */
+static void rkisp1_flt_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_flt_config *arg)
+{
+ u32 filt_mode;
+
+ rkisp1_write(params->rkisp1,
+ arg->thresh_bl0, RKISP1_CIF_ISP_FILT_THRESH_BL0);
+ rkisp1_write(params->rkisp1,
+ arg->thresh_bl1, RKISP1_CIF_ISP_FILT_THRESH_BL1);
+ rkisp1_write(params->rkisp1,
+ arg->thresh_sh0, RKISP1_CIF_ISP_FILT_THRESH_SH0);
+ rkisp1_write(params->rkisp1,
+ arg->thresh_sh1, RKISP1_CIF_ISP_FILT_THRESH_SH1);
+ rkisp1_write(params->rkisp1, arg->fac_bl0, RKISP1_CIF_ISP_FILT_FAC_BL0);
+ rkisp1_write(params->rkisp1, arg->fac_bl1, RKISP1_CIF_ISP_FILT_FAC_BL1);
+ rkisp1_write(params->rkisp1, arg->fac_mid, RKISP1_CIF_ISP_FILT_FAC_MID);
+ rkisp1_write(params->rkisp1, arg->fac_sh0, RKISP1_CIF_ISP_FILT_FAC_SH0);
+ rkisp1_write(params->rkisp1, arg->fac_sh1, RKISP1_CIF_ISP_FILT_FAC_SH1);
+ rkisp1_write(params->rkisp1,
+ arg->lum_weight, RKISP1_CIF_ISP_FILT_LUM_WEIGHT);
+
+ rkisp1_write(params->rkisp1,
+ (arg->mode ? RKISP1_CIF_ISP_FLT_MODE_DNR : 0) |
+ RKISP1_CIF_ISP_FLT_CHROMA_V_MODE(arg->chr_v_mode) |
+ RKISP1_CIF_ISP_FLT_CHROMA_H_MODE(arg->chr_h_mode) |
+ RKISP1_CIF_ISP_FLT_GREEN_STAGE1(arg->grn_stage1),
+ RKISP1_CIF_ISP_FILT_MODE);
+
+ /* avoid to override the old enable value */
+ filt_mode = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_FILT_MODE);
+ filt_mode &= RKISP1_CIF_ISP_FLT_ENA;
+ if (arg->mode)
+ filt_mode |= RKISP1_CIF_ISP_FLT_MODE_DNR;
+ filt_mode |= RKISP1_CIF_ISP_FLT_CHROMA_V_MODE(arg->chr_v_mode) |
+ RKISP1_CIF_ISP_FLT_CHROMA_H_MODE(arg->chr_h_mode) |
+ RKISP1_CIF_ISP_FLT_GREEN_STAGE1(arg->grn_stage1);
+ rkisp1_write(params->rkisp1, filt_mode, RKISP1_CIF_ISP_FILT_MODE);
+}
+
+/* ISP demosaic interface function */
+static int rkisp1_bdm_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_bdm_config *arg)
+{
+ u32 bdm_th;
+
+ /* avoid to override the old enable value */
+ bdm_th = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_DEMOSAIC);
+ bdm_th &= RKISP1_CIF_ISP_DEMOSAIC_BYPASS;
+ bdm_th |= arg->demosaic_th & ~RKISP1_CIF_ISP_DEMOSAIC_BYPASS;
+ /* set demosaic threshold */
+ rkisp1_write(params->rkisp1, bdm_th, RKISP1_CIF_ISP_DEMOSAIC);
+ return 0;
+}
+
+/* ISP GAMMA correction interface function */
+static void rkisp1_sdg_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_sdg_config *arg)
+{
+ unsigned int i;
+
+ rkisp1_write(params->rkisp1,
+ arg->xa_pnts.gamma_dx0, RKISP1_CIF_ISP_GAMMA_DX_LO);
+ rkisp1_write(params->rkisp1,
+ arg->xa_pnts.gamma_dx1, RKISP1_CIF_ISP_GAMMA_DX_HI);
+
+ for (i = 0; i < RKISP1_CIF_ISP_DEGAMMA_CURVE_SIZE; i++) {
+ rkisp1_write(params->rkisp1, arg->curve_r.gamma_y[i],
+ RKISP1_CIF_ISP_GAMMA_R_Y0 + i * 4);
+ rkisp1_write(params->rkisp1, arg->curve_g.gamma_y[i],
+ RKISP1_CIF_ISP_GAMMA_G_Y0 + i * 4);
+ rkisp1_write(params->rkisp1, arg->curve_b.gamma_y[i],
+ RKISP1_CIF_ISP_GAMMA_B_Y0 + i * 4);
+ }
+}
+
+/* ISP GAMMA correction interface function */
+static void rkisp1_goc_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_goc_config *arg)
+{
+ unsigned int i;
+
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
+ rkisp1_write(params->rkisp1, arg->mode, RKISP1_CIF_ISP_GAMMA_OUT_MODE);
+
+ for (i = 0; i < RKISP1_CIF_ISP_GAMMA_OUT_MAX_SAMPLES; i++)
+ rkisp1_write(params->rkisp1, arg->gamma_y[i],
+ RKISP1_CIF_ISP_GAMMA_OUT_Y_0 + i * 4);
+}
+
+/* ISP Cross Talk */
+static void rkisp1_ctk_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_ctk_config *arg)
+{
+ unsigned int i, j, k = 0;
+
+ for (i = 0; i < 3; i++)
+ for (j = 0; j < 3; j++)
+ rkisp1_write(params->rkisp1, arg->coeff[i][j],
+ RKISP1_CIF_ISP_CT_COEFF_0 + 4 * k++);
+ for (i = 0; i < 3; i++)
+ rkisp1_write(params->rkisp1, arg->ct_offset[i],
+ RKISP1_CIF_ISP_CT_OFFSET_R + i * 4);
+}
+
+static void rkisp1_ctk_enable(struct rkisp1_params *params, bool en)
+{
+ if (en)
+ return;
+
+ /* Write back the default values. */
+ rkisp1_write(params->rkisp1, 0x80, RKISP1_CIF_ISP_CT_COEFF_0);
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_COEFF_1);
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_COEFF_2);
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_COEFF_3);
+ rkisp1_write(params->rkisp1, 0x80, RKISP1_CIF_ISP_CT_COEFF_4);
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_COEFF_5);
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_COEFF_6);
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_COEFF_7);
+ rkisp1_write(params->rkisp1, 0x80, RKISP1_CIF_ISP_CT_COEFF_8);
+
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_OFFSET_R);
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_OFFSET_G);
+ rkisp1_write(params->rkisp1, 0, RKISP1_CIF_ISP_CT_OFFSET_B);
+}
+
+/* ISP White Balance Mode */
+static void rkisp1_awb_meas_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_awb_meas_config *arg)
+{
+ u32 reg_val = 0;
+ /* based on the mode,configure the awb module */
+ if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_YCBCR) {
+ /* Reference Cb and Cr */
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) |
+ arg->awb_ref_cb, RKISP1_CIF_ISP_AWB_REF);
+ /* Yc Threshold */
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_AWB_MAX_Y_SET(arg->max_y) |
+ RKISP1_CIF_ISP_AWB_MIN_Y_SET(arg->min_y) |
+ RKISP1_CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) |
+ arg->min_c, RKISP1_CIF_ISP_AWB_THRESH);
+ }
+
+ reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
+ if (arg->enable_ymax_cmp)
+ reg_val |= RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
+ else
+ reg_val &= ~RKISP1_CIF_ISP_AWB_YMAX_CMP_EN;
+ rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
+
+ /* window offset */
+ rkisp1_write(params->rkisp1,
+ arg->awb_wnd.v_offs, RKISP1_CIF_ISP_AWB_WND_V_OFFS);
+ rkisp1_write(params->rkisp1,
+ arg->awb_wnd.h_offs, RKISP1_CIF_ISP_AWB_WND_H_OFFS);
+ /* AWB window size */
+ rkisp1_write(params->rkisp1,
+ arg->awb_wnd.v_size, RKISP1_CIF_ISP_AWB_WND_V_SIZE);
+ rkisp1_write(params->rkisp1,
+ arg->awb_wnd.h_size, RKISP1_CIF_ISP_AWB_WND_H_SIZE);
+ /* Number of frames */
+ rkisp1_write(params->rkisp1,
+ arg->frames, RKISP1_CIF_ISP_AWB_FRAMES);
+}
+
+static void
+rkisp1_awb_meas_enable(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_awb_meas_config *arg,
+ bool en)
+{
+ u32 reg_val = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AWB_PROP);
+
+ /* switch off */
+ reg_val &= RKISP1_CIF_ISP_AWB_MODE_MASK_NONE;
+
+ if (en) {
+ if (arg->awb_mode == RKISP1_CIF_ISP_AWB_MODE_RGB)
+ reg_val |= RKISP1_CIF_ISP_AWB_MODE_RGB_EN;
+ else
+ reg_val |= RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN;
+
+ rkisp1_write(params->rkisp1, reg_val, RKISP1_CIF_ISP_AWB_PROP);
+
+ /* Measurements require AWB block be active. */
+ rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
+ } else {
+ rkisp1_write(params->rkisp1,
+ reg_val, RKISP1_CIF_ISP_AWB_PROP);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
+ }
+}
+
+static void
+rkisp1_awb_gain_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_awb_gain_config *arg)
+{
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) |
+ arg->gain_green_b, RKISP1_CIF_ISP_AWB_GAIN_G);
+
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) |
+ arg->gain_blue, RKISP1_CIF_ISP_AWB_GAIN_RB);
+}
+
+static void rkisp1_aec_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_aec_config *arg)
+{
+ unsigned int block_hsize, block_vsize;
+ u32 exp_ctrl;
+
+ /* avoid to override the old enable value */
+ exp_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_EXP_CTRL);
+ exp_ctrl &= RKISP1_CIF_ISP_EXP_ENA;
+ if (arg->autostop)
+ exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP;
+ if (arg->mode == RKISP1_CIF_ISP_EXP_MEASURING_MODE_1)
+ exp_ctrl |= RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1;
+ rkisp1_write(params->rkisp1, exp_ctrl, RKISP1_CIF_ISP_EXP_CTRL);
+
+ rkisp1_write(params->rkisp1,
+ arg->meas_window.h_offs, RKISP1_CIF_ISP_EXP_H_OFFSET);
+ rkisp1_write(params->rkisp1,
+ arg->meas_window.v_offs, RKISP1_CIF_ISP_EXP_V_OFFSET);
+
+ block_hsize = arg->meas_window.h_size /
+ RKISP1_CIF_ISP_EXP_COLUMN_NUM - 1;
+ block_vsize = arg->meas_window.v_size /
+ RKISP1_CIF_ISP_EXP_ROW_NUM - 1;
+
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_EXP_H_SIZE_SET(block_hsize),
+ RKISP1_CIF_ISP_EXP_H_SIZE);
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_EXP_V_SIZE_SET(block_vsize),
+ RKISP1_CIF_ISP_EXP_V_SIZE);
+}
+
+static void rkisp1_cproc_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_cproc_config *arg)
+{
+ struct rkisp1_cif_isp_isp_other_cfg *cur_other_cfg =
+ container_of(arg, struct rkisp1_cif_isp_isp_other_cfg, cproc_config);
+ struct rkisp1_cif_isp_ie_config *cur_ie_config =
+ &cur_other_cfg->ie_config;
+ u32 effect = cur_ie_config->effect;
+ u32 quantization = params->quantization;
+
+ rkisp1_write(params->rkisp1, arg->contrast, RKISP1_CIF_C_PROC_CONTRAST);
+ rkisp1_write(params->rkisp1, arg->hue, RKISP1_CIF_C_PROC_HUE);
+ rkisp1_write(params->rkisp1, arg->sat, RKISP1_CIF_C_PROC_SATURATION);
+ rkisp1_write(params->rkisp1, arg->brightness,
+ RKISP1_CIF_C_PROC_BRIGHTNESS);
+
+ if (quantization != V4L2_QUANTIZATION_FULL_RANGE ||
+ effect != V4L2_COLORFX_NONE) {
+ rkisp1_param_clear_bits(params, RKISP1_CIF_C_PROC_CTRL,
+ RKISP1_CIF_C_PROC_YOUT_FULL |
+ RKISP1_CIF_C_PROC_YIN_FULL |
+ RKISP1_CIF_C_PROC_COUT_FULL);
+ } else {
+ rkisp1_param_set_bits(params, RKISP1_CIF_C_PROC_CTRL,
+ RKISP1_CIF_C_PROC_YOUT_FULL |
+ RKISP1_CIF_C_PROC_YIN_FULL |
+ RKISP1_CIF_C_PROC_COUT_FULL);
+ }
+}
+
+static void rkisp1_hst_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_hst_config *arg)
+{
+ unsigned int block_hsize, block_vsize;
+ static const u32 hist_weight_regs[] = {
+ RKISP1_CIF_ISP_HIST_WEIGHT_00TO30,
+ RKISP1_CIF_ISP_HIST_WEIGHT_40TO21,
+ RKISP1_CIF_ISP_HIST_WEIGHT_31TO12,
+ RKISP1_CIF_ISP_HIST_WEIGHT_22TO03,
+ RKISP1_CIF_ISP_HIST_WEIGHT_13TO43,
+ RKISP1_CIF_ISP_HIST_WEIGHT_04TO34,
+ RKISP1_CIF_ISP_HIST_WEIGHT_44,
+ };
+ const u8 *weight;
+ unsigned int i;
+ u32 hist_prop;
+
+ /* avoid to override the old enable value */
+ hist_prop = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_HIST_PROP);
+ hist_prop &= RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
+ hist_prop |= RKISP1_CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider);
+ rkisp1_write(params->rkisp1, hist_prop, RKISP1_CIF_ISP_HIST_PROP);
+ rkisp1_write(params->rkisp1,
+ arg->meas_window.h_offs,
+ RKISP1_CIF_ISP_HIST_H_OFFS);
+ rkisp1_write(params->rkisp1,
+ arg->meas_window.v_offs,
+ RKISP1_CIF_ISP_HIST_V_OFFS);
+
+ block_hsize = arg->meas_window.h_size /
+ RKISP1_CIF_ISP_HIST_COLUMN_NUM - 1;
+ block_vsize = arg->meas_window.v_size / RKISP1_CIF_ISP_HIST_ROW_NUM - 1;
+
+ rkisp1_write(params->rkisp1, block_hsize, RKISP1_CIF_ISP_HIST_H_SIZE);
+ rkisp1_write(params->rkisp1, block_vsize, RKISP1_CIF_ISP_HIST_V_SIZE);
+
+ weight = arg->hist_weight;
+ for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4)
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_HIST_WEIGHT_SET(weight[0],
+ weight[1],
+ weight[2],
+ weight[3]),
+ hist_weight_regs[i]);
+}
+
+static void
+rkisp1_hst_enable(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_hst_config *arg, bool en)
+{
+ if (en) {
+ u32 hist_prop = rkisp1_read(params->rkisp1,
+ RKISP1_CIF_ISP_HIST_PROP);
+
+ hist_prop &= ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK;
+ hist_prop |= arg->mode;
+ rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
+ hist_prop);
+ } else {
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_HIST_PROP,
+ RKISP1_CIF_ISP_HIST_PROP_MODE_MASK);
+ }
+}
+
+static void rkisp1_afm_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_afc_config *arg)
+{
+ size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win),
+ arg->num_afm_win);
+ u32 afm_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_ISP_AFM_CTRL);
+ unsigned int i;
+
+ /* Switch off to configure. */
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
+ RKISP1_CIF_ISP_AFM_ENA);
+
+ for (i = 0; i < num_of_win; i++) {
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) |
+ RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs),
+ RKISP1_CIF_ISP_AFM_LT_A + i * 8);
+ rkisp1_write(params->rkisp1,
+ RKISP1_CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size +
+ arg->afm_win[i].h_offs) |
+ RKISP1_CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size +
+ arg->afm_win[i].v_offs),
+ RKISP1_CIF_ISP_AFM_RB_A + i * 8);
+ }
+ rkisp1_write(params->rkisp1, arg->thres, RKISP1_CIF_ISP_AFM_THRES);
+ rkisp1_write(params->rkisp1, arg->var_shift,
+ RKISP1_CIF_ISP_AFM_VAR_SHIFT);
+ /* restore afm status */
+ rkisp1_write(params->rkisp1, afm_ctrl, RKISP1_CIF_ISP_AFM_CTRL);
+}
+
+static void rkisp1_ie_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_ie_config *arg)
+{
+ u32 eff_ctrl;
+
+ eff_ctrl = rkisp1_read(params->rkisp1, RKISP1_CIF_IMG_EFF_CTRL);
+ eff_ctrl &= ~RKISP1_CIF_IMG_EFF_CTRL_MODE_MASK;
+
+ if (params->quantization == V4L2_QUANTIZATION_FULL_RANGE)
+ eff_ctrl |= RKISP1_CIF_IMG_EFF_CTRL_YCBCR_FULL;
+
+ switch (arg->effect) {
+ case V4L2_COLORFX_SEPIA:
+ eff_ctrl |= RKISP1_CIF_IMG_EFF_CTRL_MODE_SEPIA;
+ break;
+ case V4L2_COLORFX_SET_CBCR:
+ rkisp1_write(params->rkisp1, arg->eff_tint,
+ RKISP1_CIF_IMG_EFF_TINT);
+ eff_ctrl |= RKISP1_CIF_IMG_EFF_CTRL_MODE_SEPIA;
+ break;
+ /*
+ * Color selection is similar to water color(AQUA):
+ * grayscale + selected color w threshold
+ */
+ case V4L2_COLORFX_AQUA:
+ eff_ctrl |= RKISP1_CIF_IMG_EFF_CTRL_MODE_COLOR_SEL;
+ rkisp1_write(params->rkisp1, arg->color_sel,
+ RKISP1_CIF_IMG_EFF_COLOR_SEL);
+ break;
+ case V4L2_COLORFX_EMBOSS:
+ eff_ctrl |= RKISP1_CIF_IMG_EFF_CTRL_MODE_EMBOSS;
+ rkisp1_write(params->rkisp1, arg->eff_mat_1,
+ RKISP1_CIF_IMG_EFF_MAT_1);
+ rkisp1_write(params->rkisp1, arg->eff_mat_2,
+ RKISP1_CIF_IMG_EFF_MAT_2);
+ rkisp1_write(params->rkisp1, arg->eff_mat_3,
+ RKISP1_CIF_IMG_EFF_MAT_3);
+ break;
+ case V4L2_COLORFX_SKETCH:
+ eff_ctrl |= RKISP1_CIF_IMG_EFF_CTRL_MODE_SKETCH;
+ rkisp1_write(params->rkisp1, arg->eff_mat_3,
+ RKISP1_CIF_IMG_EFF_MAT_3);
+ rkisp1_write(params->rkisp1, arg->eff_mat_4,
+ RKISP1_CIF_IMG_EFF_MAT_4);
+ rkisp1_write(params->rkisp1, arg->eff_mat_5,
+ RKISP1_CIF_IMG_EFF_MAT_5);
+ break;
+ case V4L2_COLORFX_BW:
+ eff_ctrl |= RKISP1_CIF_IMG_EFF_CTRL_MODE_BLACKWHITE;
+ break;
+ case V4L2_COLORFX_NEGATIVE:
+ eff_ctrl |= RKISP1_CIF_IMG_EFF_CTRL_MODE_NEGATIVE;
+ break;
+ default:
+ break;
+ }
+
+ rkisp1_write(params->rkisp1, eff_ctrl, RKISP1_CIF_IMG_EFF_CTRL);
+}
+
+static void rkisp1_ie_enable(struct rkisp1_params *params, bool en)
+{
+ if (en) {
+ rkisp1_param_set_bits(params, RKISP1_CIF_ICCL,
+ RKISP1_CIF_ICCL_IE_CLK);
+ rkisp1_write(params->rkisp1, RKISP1_CIF_IMG_EFF_CTRL_ENABLE,
+ RKISP1_CIF_IMG_EFF_CTRL);
+ rkisp1_param_set_bits(params, RKISP1_CIF_IMG_EFF_CTRL,
+ RKISP1_CIF_IMG_EFF_CTRL_CFG_UPD);
+ } else {
+ rkisp1_param_clear_bits(params, RKISP1_CIF_IMG_EFF_CTRL,
+ RKISP1_CIF_IMG_EFF_CTRL_ENABLE);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ICCL,
+ RKISP1_CIF_ICCL_IE_CLK);
+ }
+}
+
+static void rkisp1_csm_config(struct rkisp1_params *params, bool full_range)
+{
+ static const u16 full_range_coeff[] = {
+ 0x0026, 0x004b, 0x000f,
+ 0x01ea, 0x01d6, 0x0040,
+ 0x0040, 0x01ca, 0x01f6
+ };
+ static const u16 limited_range_coeff[] = {
+ 0x0021, 0x0040, 0x000d,
+ 0x01ed, 0x01db, 0x0038,
+ 0x0038, 0x01d1, 0x01f7,
+ };
+ unsigned int i;
+
+ if (full_range) {
+ for (i = 0; i < ARRAY_SIZE(full_range_coeff); i++)
+ rkisp1_write(params->rkisp1, full_range_coeff[i],
+ RKISP1_CIF_ISP_CC_COEFF_0 + i * 4);
+
+ rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
+ RKISP1_CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA);
+ } else {
+ for (i = 0; i < ARRAY_SIZE(limited_range_coeff); i++)
+ rkisp1_write(params->rkisp1, limited_range_coeff[i],
+ RKISP1_CIF_ISP_CC_COEFF_0 + i * 4);
+
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
+ RKISP1_CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA);
+ }
+}
+
+/* ISP De-noise Pre-Filter(DPF) function */
+static void rkisp1_dpf_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_dpf_config *arg)
+{
+ unsigned int isp_dpf_mode, spatial_coeff, i;
+
+ switch (arg->gain.mode) {
+ case RKISP1_CIF_ISP_DPF_GAIN_USAGE_NF_GAINS:
+ isp_dpf_mode = RKISP1_CIF_ISP_DPF_MODE_USE_NF_GAIN |
+ RKISP1_CIF_ISP_DPF_MODE_AWB_GAIN_COMP;
+ break;
+ case RKISP1_CIF_ISP_DPF_GAIN_USAGE_LSC_GAINS:
+ isp_dpf_mode = RKISP1_CIF_ISP_DPF_MODE_LSC_GAIN_COMP;
+ break;
+ case RKISP1_CIF_ISP_DPF_GAIN_USAGE_NF_LSC_GAINS:
+ isp_dpf_mode = RKISP1_CIF_ISP_DPF_MODE_USE_NF_GAIN |
+ RKISP1_CIF_ISP_DPF_MODE_AWB_GAIN_COMP |
+ RKISP1_CIF_ISP_DPF_MODE_LSC_GAIN_COMP;
+ break;
+ case RKISP1_CIF_ISP_DPF_GAIN_USAGE_AWB_GAINS:
+ isp_dpf_mode = RKISP1_CIF_ISP_DPF_MODE_AWB_GAIN_COMP;
+ break;
+ case RKISP1_CIF_ISP_DPF_GAIN_USAGE_AWB_LSC_GAINS:
+ isp_dpf_mode = RKISP1_CIF_ISP_DPF_MODE_LSC_GAIN_COMP |
+ RKISP1_CIF_ISP_DPF_MODE_AWB_GAIN_COMP;
+ break;
+ case RKISP1_CIF_ISP_DPF_GAIN_USAGE_DISABLED:
+ default:
+ isp_dpf_mode = 0;
+ break;
+ }
+
+ if (arg->nll.scale_mode == RKISP1_CIF_ISP_NLL_SCALE_LOGARITHMIC)
+ isp_dpf_mode |= RKISP1_CIF_ISP_DPF_MODE_NLL_SEGMENTATION;
+ if (arg->rb_flt.fltsize == RKISP1_CIF_ISP_DPF_RB_FILTERSIZE_9x9)
+ isp_dpf_mode |= RKISP1_CIF_ISP_DPF_MODE_RB_FLTSIZE_9x9;
+ if (!arg->rb_flt.r_enable)
+ isp_dpf_mode |= RKISP1_CIF_ISP_DPF_MODE_R_FLT_DIS;
+ if (!arg->rb_flt.b_enable)
+ isp_dpf_mode |= RKISP1_CIF_ISP_DPF_MODE_B_FLT_DIS;
+ if (!arg->g_flt.gb_enable)
+ isp_dpf_mode |= RKISP1_CIF_ISP_DPF_MODE_GB_FLT_DIS;
+ if (!arg->g_flt.gr_enable)
+ isp_dpf_mode |= RKISP1_CIF_ISP_DPF_MODE_GR_FLT_DIS;
+
+ rkisp1_param_set_bits(params, RKISP1_CIF_ISP_DPF_MODE,
+ isp_dpf_mode);
+ rkisp1_write(params->rkisp1, arg->gain.nf_b_gain,
+ RKISP1_CIF_ISP_DPF_NF_GAIN_B);
+ rkisp1_write(params->rkisp1, arg->gain.nf_r_gain,
+ RKISP1_CIF_ISP_DPF_NF_GAIN_R);
+ rkisp1_write(params->rkisp1, arg->gain.nf_gb_gain,
+ RKISP1_CIF_ISP_DPF_NF_GAIN_GB);
+ rkisp1_write(params->rkisp1, arg->gain.nf_gr_gain,
+ RKISP1_CIF_ISP_DPF_NF_GAIN_GR);
+
+ for (i = 0; i < RKISP1_CIF_ISP_DPF_MAX_NLF_COEFFS; i++) {
+ rkisp1_write(params->rkisp1, arg->nll.coeff[i],
+ RKISP1_CIF_ISP_DPF_NULL_COEFF_0 + i * 4);
+ }
+
+ spatial_coeff = arg->g_flt.spatial_coeff[0] |
+ (arg->g_flt.spatial_coeff[1] << 8) |
+ (arg->g_flt.spatial_coeff[2] << 16) |
+ (arg->g_flt.spatial_coeff[3] << 24);
+ rkisp1_write(params->rkisp1, spatial_coeff,
+ RKISP1_CIF_ISP_DPF_S_WEIGHT_G_1_4);
+
+ spatial_coeff = arg->g_flt.spatial_coeff[4] |
+ (arg->g_flt.spatial_coeff[5] << 8);
+ rkisp1_write(params->rkisp1, spatial_coeff,
+ RKISP1_CIF_ISP_DPF_S_WEIGHT_G_5_6);
+
+ spatial_coeff = arg->rb_flt.spatial_coeff[0] |
+ (arg->rb_flt.spatial_coeff[1] << 8) |
+ (arg->rb_flt.spatial_coeff[2] << 16) |
+ (arg->rb_flt.spatial_coeff[3] << 24);
+ rkisp1_write(params->rkisp1, spatial_coeff,
+ RKISP1_CIF_ISP_DPF_S_WEIGHT_RB_1_4);
+
+ spatial_coeff = arg->rb_flt.spatial_coeff[4] |
+ (arg->rb_flt.spatial_coeff[5] << 8);
+ rkisp1_write(params->rkisp1, spatial_coeff,
+ RKISP1_CIF_ISP_DPF_S_WEIGHT_RB_5_6);
+}
+
+static void
+rkisp1_dpf_strength_config(struct rkisp1_params *params,
+ const struct rkisp1_cif_isp_dpf_strength_config *arg)
+{
+ rkisp1_write(params->rkisp1, arg->b, RKISP1_CIF_ISP_DPF_STRENGTH_B);
+ rkisp1_write(params->rkisp1, arg->g, RKISP1_CIF_ISP_DPF_STRENGTH_G);
+ rkisp1_write(params->rkisp1, arg->r, RKISP1_CIF_ISP_DPF_STRENGTH_R);
+}
+
+static void
+rkisp1_isp_isr_other_config(struct rkisp1_params *params,
+ const struct rkisp1_params_cfg *new_params)
+{
+ unsigned int module_en_update, module_cfg_update, module_ens;
+
+ module_en_update = new_params->module_en_update;
+ module_cfg_update = new_params->module_cfg_update;
+ module_ens = new_params->module_ens;
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_DPCC) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_DPCC)) {
+ /*update dpc config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_DPCC)
+ rkisp1_dpcc_config(params,
+ &new_params->others.dpcc_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_DPCC) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_DPCC)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_DPCC_MODE,
+ RKISP1_CIF_ISP_DPCC_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_DPCC_MODE,
+ RKISP1_CIF_ISP_DPCC_ENA);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_BLS) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_BLS)) {
+ /* update bls config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_BLS)
+ rkisp1_bls_config(params,
+ &new_params->others.bls_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_BLS) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_BLS)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_BLS_CTRL,
+ RKISP1_CIF_ISP_BLS_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_BLS_CTRL,
+ RKISP1_CIF_ISP_BLS_ENA);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_SDG) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_SDG)) {
+ /* update sdg config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_SDG)
+ rkisp1_sdg_config(params,
+ &new_params->others.sdg_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_SDG) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_SDG)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_LSC) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_LSC)) {
+ /* update lsc config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_LSC)
+ rkisp1_lsc_config(params,
+ &new_params->others.lsc_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_LSC) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_LSC)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_LSC_CTRL,
+ RKISP1_CIF_ISP_LSC_CTRL_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_LSC_CTRL,
+ RKISP1_CIF_ISP_LSC_CTRL_ENA);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN)) {
+ /* update awb gains */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN)
+ rkisp1_awb_gain_config(params,
+ &new_params->others.awb_gain_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_AWB_GAIN) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_AWB_GAIN)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_BDM) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_BDM)) {
+ /* update bdm config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_BDM)
+ rkisp1_bdm_config(params,
+ &new_params->others.bdm_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_BDM) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_BDM)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_DEMOSAIC,
+ RKISP1_CIF_ISP_DEMOSAIC_BYPASS);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_DEMOSAIC,
+ RKISP1_CIF_ISP_DEMOSAIC_BYPASS);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_FLT) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_FLT)) {
+ /* update filter config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_FLT)
+ rkisp1_flt_config(params,
+ &new_params->others.flt_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_FLT) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_FLT)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_FILT_MODE,
+ RKISP1_CIF_ISP_FLT_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_FILT_MODE,
+ RKISP1_CIF_ISP_FLT_ENA);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_CTK) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_CTK)) {
+ /* update ctk config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_CTK)
+ rkisp1_ctk_config(params,
+ &new_params->others.ctk_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_CTK)
+ rkisp1_ctk_enable(params,
+ !!(module_ens & RKISP1_CIF_ISP_MODULE_CTK));
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_GOC) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_GOC)) {
+ /* update goc config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_GOC)
+ rkisp1_goc_config(params,
+ &new_params->others.goc_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_GOC) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_GOC)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_CPROC) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_CPROC)) {
+ /* update cproc config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_CPROC) {
+ rkisp1_cproc_config(params,
+ &new_params->others.cproc_config);
+ }
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_CPROC) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_CPROC)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_C_PROC_CTRL,
+ RKISP1_CIF_C_PROC_CTR_ENABLE);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_C_PROC_CTRL,
+ RKISP1_CIF_C_PROC_CTR_ENABLE);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_IE) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_IE)) {
+ /* update ie config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_IE)
+ rkisp1_ie_config(params,
+ &new_params->others.ie_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_IE)
+ rkisp1_ie_enable(params,
+ !!(module_ens & RKISP1_CIF_ISP_MODULE_IE));
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_DPF) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_DPF)) {
+ /* update dpf config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_DPF)
+ rkisp1_dpf_config(params,
+ &new_params->others.dpf_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_DPF) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_DPF)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_DPF_MODE,
+ RKISP1_CIF_ISP_DPF_MODE_EN);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_DPF_MODE,
+ RKISP1_CIF_ISP_DPF_MODE_EN);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_DPF_STRENGTH) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_DPF_STRENGTH)) {
+ /* update dpf strength config */
+ rkisp1_dpf_strength_config(params,
+ &new_params->others.dpf_strength_config);
+ }
+}
+
+static void rkisp1_isp_isr_meas_config(struct rkisp1_params *params,
+ struct rkisp1_params_cfg *new_params)
+{
+ unsigned int module_en_update, module_cfg_update, module_ens;
+
+ module_en_update = new_params->module_en_update;
+ module_cfg_update = new_params->module_cfg_update;
+ module_ens = new_params->module_ens;
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_AWB) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB)) {
+ /* update awb config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AWB)
+ rkisp1_awb_meas_config(params,
+ &new_params->meas.awb_meas_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_AWB)
+ rkisp1_awb_meas_enable(params,
+ &new_params->meas.awb_meas_config,
+ !!(module_ens & RKISP1_CIF_ISP_MODULE_AWB));
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_AFC) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_AFC)) {
+ /* update afc config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AFC)
+ rkisp1_afm_config(params,
+ &new_params->meas.afc_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_AFC) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_AFC)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_AFM_CTRL,
+ RKISP1_CIF_ISP_AFM_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_AFM_CTRL,
+ RKISP1_CIF_ISP_AFM_ENA);
+ }
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_HST) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_HST)) {
+ /* update hst config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_HST)
+ rkisp1_hst_config(params,
+ &new_params->meas.hst_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_HST)
+ rkisp1_hst_enable(params,
+ &new_params->meas.hst_config,
+ !!(module_ens & RKISP1_CIF_ISP_MODULE_HST));
+ }
+
+ if ((module_en_update & RKISP1_CIF_ISP_MODULE_AEC) ||
+ (module_cfg_update & RKISP1_CIF_ISP_MODULE_AEC)) {
+ /* update aec config */
+ if (module_cfg_update & RKISP1_CIF_ISP_MODULE_AEC)
+ rkisp1_aec_config(params,
+ &new_params->meas.aec_config);
+
+ if (module_en_update & RKISP1_CIF_ISP_MODULE_AEC) {
+ if (module_ens & RKISP1_CIF_ISP_MODULE_AEC)
+ rkisp1_param_set_bits(params,
+ RKISP1_CIF_ISP_EXP_CTRL,
+ RKISP1_CIF_ISP_EXP_ENA);
+ else
+ rkisp1_param_clear_bits(params,
+ RKISP1_CIF_ISP_EXP_CTRL,
+ RKISP1_CIF_ISP_EXP_ENA);
+ }
+ }
+}
+
+static void rkisp1_params_apply_params_cfg(struct rkisp1_params *params,
+ unsigned int frame_sequence)
+{
+ struct rkisp1_params_cfg *new_params;
+ struct rkisp1_buffer *cur_buf = NULL;
+
+ if (list_empty(&params->params))
+ return;
+
+ cur_buf = list_first_entry(&params->params,
+ struct rkisp1_buffer, queue);
+
+ new_params = (struct rkisp1_params_cfg *)(cur_buf->vaddr);
+
+ rkisp1_isp_isr_other_config(params, new_params);
+ rkisp1_isp_isr_meas_config(params, new_params);
+
+ /* update shadow register immediately */
+ rkisp1_param_set_bits(params, RKISP1_CIF_ISP_CTRL, RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD);
+
+ list_del(&cur_buf->queue);
+
+ cur_buf->vb.sequence = frame_sequence;
+ vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
+}
+
+void rkisp1_params_isr(struct rkisp1_device *rkisp1)
+{
+ /*
+ * This isr is called when the ISR finishes processing a frame (RKISP1_CIF_ISP_FRAME).
+ * Configurations performed here will be applied on the next frame.
+ * Since frame_sequence is updated on the vertical sync signal, we should use
+ * frame_sequence + 1 here to indicate to userspace on which frame these parameters
+ * are being applied.
+ */
+ unsigned int frame_sequence = rkisp1->isp.frame_sequence + 1;
+ struct rkisp1_params *params = &rkisp1->params;
+
+ spin_lock(&params->config_lock);
+ rkisp1_params_apply_params_cfg(params, frame_sequence);
+
+ spin_unlock(&params->config_lock);
+}
+
+static const struct rkisp1_cif_isp_awb_meas_config rkisp1_awb_params_default_config = {
+ {
+ 0, 0, RKISP1_DEFAULT_WIDTH, RKISP1_DEFAULT_HEIGHT
+ },
+ RKISP1_CIF_ISP_AWB_MODE_YCBCR, 200, 30, 20, 20, 0, 128, 128
+};
+
+static const struct rkisp1_cif_isp_aec_config rkisp1_aec_params_default_config = {
+ RKISP1_CIF_ISP_EXP_MEASURING_MODE_0,
+ RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP_0,
+ {
+ RKISP1_DEFAULT_WIDTH >> 2, RKISP1_DEFAULT_HEIGHT >> 2,
+ RKISP1_DEFAULT_WIDTH >> 1, RKISP1_DEFAULT_HEIGHT >> 1
+ }
+};
+
+static const struct rkisp1_cif_isp_hst_config rkisp1_hst_params_default_config = {
+ RKISP1_CIF_ISP_HISTOGRAM_MODE_RGB_COMBINED,
+ 3,
+ {
+ RKISP1_DEFAULT_WIDTH >> 2, RKISP1_DEFAULT_HEIGHT >> 2,
+ RKISP1_DEFAULT_WIDTH >> 1, RKISP1_DEFAULT_HEIGHT >> 1
+ },
+ {
+ 0, /* To be filled in with 0x01 at runtime. */
+ }
+};
+
+static const struct rkisp1_cif_isp_afc_config rkisp1_afc_params_default_config = {
+ 1,
+ {
+ {
+ 300, 225, 200, 150
+ }
+ },
+ 4,
+ 14
+};
+
+static void rkisp1_params_config_parameter(struct rkisp1_params *params)
+{
+ struct rkisp1_cif_isp_hst_config hst = rkisp1_hst_params_default_config;
+
+ rkisp1_awb_meas_config(params, &rkisp1_awb_params_default_config);
+ rkisp1_awb_meas_enable(params, &rkisp1_awb_params_default_config,
+ true);
+
+ rkisp1_aec_config(params, &rkisp1_aec_params_default_config);
+ rkisp1_param_set_bits(params, RKISP1_CIF_ISP_EXP_CTRL,
+ RKISP1_CIF_ISP_EXP_ENA);
+
+ rkisp1_afm_config(params, &rkisp1_afc_params_default_config);
+ rkisp1_param_set_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
+ RKISP1_CIF_ISP_AFM_ENA);
+
+ memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight));
+ rkisp1_hst_config(params, &hst);
+ rkisp1_param_set_bits(params, RKISP1_CIF_ISP_HIST_PROP,
+ ~RKISP1_CIF_ISP_HIST_PROP_MODE_MASK |
+ rkisp1_hst_params_default_config.mode);
+
+ /* set the range */
+ if (params->quantization == V4L2_QUANTIZATION_FULL_RANGE)
+ rkisp1_csm_config(params, true);
+ else
+ rkisp1_csm_config(params, false);
+
+ spin_lock_irq(&params->config_lock);
+
+ /* apply the first buffer if there is one already */
+ rkisp1_params_apply_params_cfg(params, 0);
+
+ spin_unlock_irq(&params->config_lock);
+}
+
+void rkisp1_params_configure(struct rkisp1_params *params,
+ enum rkisp1_fmt_raw_pat_type bayer_pat,
+ enum v4l2_quantization quantization)
+{
+ params->quantization = quantization;
+ params->raw_type = bayer_pat;
+ rkisp1_params_config_parameter(params);
+}
+
+/* Not called when the camera active, thus not isr protection. */
+void rkisp1_params_disable(struct rkisp1_params *params)
+{
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_DPCC_MODE,
+ RKISP1_CIF_ISP_DPCC_ENA);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_LSC_CTRL,
+ RKISP1_CIF_ISP_LSC_CTRL_ENA);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_BLS_CTRL,
+ RKISP1_CIF_ISP_BLS_ENA);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_DEMOSAIC,
+ RKISP1_CIF_ISP_DEMOSAIC_BYPASS);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_FILT_MODE,
+ RKISP1_CIF_ISP_FLT_ENA);
+ rkisp1_awb_meas_enable(params, NULL, false);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_CTRL,
+ RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_EXP_CTRL,
+ RKISP1_CIF_ISP_EXP_ENA);
+ rkisp1_ctk_enable(params, false);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_C_PROC_CTRL,
+ RKISP1_CIF_C_PROC_CTR_ENABLE);
+ rkisp1_hst_enable(params, NULL, false);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_AFM_CTRL,
+ RKISP1_CIF_ISP_AFM_ENA);
+ rkisp1_ie_enable(params, false);
+ rkisp1_param_clear_bits(params, RKISP1_CIF_ISP_DPF_MODE,
+ RKISP1_CIF_ISP_DPF_MODE_EN);
+}
+
+static int rkisp1_params_enum_fmt_meta_out(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct video_device *video = video_devdata(file);
+ struct rkisp1_params *params = video_get_drvdata(video);
+
+ if (f->index > 0 || f->type != video->queue->type)
+ return -EINVAL;
+
+ f->pixelformat = params->vdev_fmt.fmt.meta.dataformat;
+
+ return 0;
+}
+
+static int rkisp1_params_g_fmt_meta_out(struct file *file, void *fh,
+ struct v4l2_format *f)
+{
+ struct video_device *video = video_devdata(file);
+ struct rkisp1_params *params = video_get_drvdata(video);
+ struct v4l2_meta_format *meta = &f->fmt.meta;
+
+ if (f->type != video->queue->type)
+ return -EINVAL;
+
+ memset(meta, 0, sizeof(*meta));
+ meta->dataformat = params->vdev_fmt.fmt.meta.dataformat;
+ meta->buffersize = params->vdev_fmt.fmt.meta.buffersize;
+
+ return 0;
+}
+
+static int rkisp1_params_querycap(struct file *file,
+ void *priv, struct v4l2_capability *cap)
+{
+ struct video_device *vdev = video_devdata(file);
+
+ strscpy(cap->driver, RKISP1_DRIVER_NAME, sizeof(cap->driver));
+ strscpy(cap->card, vdev->name, sizeof(cap->card));
+ strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info));
+
+ return 0;
+}
+
+/* ISP params video device IOCTLs */
+static const struct v4l2_ioctl_ops rkisp1_params_ioctl = {
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_enum_fmt_meta_out = rkisp1_params_enum_fmt_meta_out,
+ .vidioc_g_fmt_meta_out = rkisp1_params_g_fmt_meta_out,
+ .vidioc_s_fmt_meta_out = rkisp1_params_g_fmt_meta_out,
+ .vidioc_try_fmt_meta_out = rkisp1_params_g_fmt_meta_out,
+ .vidioc_querycap = rkisp1_params_querycap,
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static int rkisp1_params_vb2_queue_setup(struct vb2_queue *vq,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ *num_buffers = clamp_t(u32, *num_buffers,
+ RKISP1_ISP_PARAMS_REQ_BUFS_MIN,
+ RKISP1_ISP_PARAMS_REQ_BUFS_MAX);
+
+ *num_planes = 1;
+
+ sizes[0] = sizeof(struct rkisp1_params_cfg);
+
+ return 0;
+}
+
+static void rkisp1_params_vb2_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp1_buffer *params_buf =
+ container_of(vbuf, struct rkisp1_buffer, vb);
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct rkisp1_params *params = vq->drv_priv;
+
+ params_buf->vaddr = vb2_plane_vaddr(vb, 0);
+ spin_lock_irq(&params->config_lock);
+ list_add_tail(&params_buf->queue, &params->params);
+ spin_unlock_irq(&params->config_lock);
+}
+
+static int rkisp1_params_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+ if (vb2_plane_size(vb, 0) < sizeof(struct rkisp1_params_cfg))
+ return -EINVAL;
+
+ vb2_set_plane_payload(vb, 0, sizeof(struct rkisp1_params_cfg));
+
+ return 0;
+}
+
+static void rkisp1_params_vb2_stop_streaming(struct vb2_queue *vq)
+{
+ struct rkisp1_params *params = vq->drv_priv;
+ struct rkisp1_buffer *buf;
+ LIST_HEAD(tmp_list);
+
+ /*
+ * we first move the buffers into a local list 'tmp_list'
+ * and then we can iterate it and call vb2_buffer_done
+ * without holding the lock
+ */
+ spin_lock_irq(&params->config_lock);
+ list_splice_init(&params->params, &tmp_list);
+ spin_unlock_irq(&params->config_lock);
+
+ list_for_each_entry(buf, &tmp_list, queue)
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+}
+
+static const struct vb2_ops rkisp1_params_vb2_ops = {
+ .queue_setup = rkisp1_params_vb2_queue_setup,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+ .buf_queue = rkisp1_params_vb2_buf_queue,
+ .buf_prepare = rkisp1_params_vb2_buf_prepare,
+ .stop_streaming = rkisp1_params_vb2_stop_streaming,
+
+};
+
+static const struct v4l2_file_operations rkisp1_params_fops = {
+ .mmap = vb2_fop_mmap,
+ .unlocked_ioctl = video_ioctl2,
+ .poll = vb2_fop_poll,
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release
+};
+
+static int rkisp1_params_init_vb2_queue(struct vb2_queue *q,
+ struct rkisp1_params *params)
+{
+ struct rkisp1_vdev_node *node;
+
+ node = container_of(q, struct rkisp1_vdev_node, buf_queue);
+
+ q->type = V4L2_BUF_TYPE_META_OUTPUT;
+ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
+ q->drv_priv = params;
+ q->ops = &rkisp1_params_vb2_ops;
+ q->mem_ops = &vb2_vmalloc_memops;
+ q->buf_struct_size = sizeof(struct rkisp1_buffer);
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->lock = &node->vlock;
+
+ return vb2_queue_init(q);
+}
+
+static void rkisp1_init_params(struct rkisp1_params *params)
+{
+ params->vdev_fmt.fmt.meta.dataformat =
+ V4L2_META_FMT_RK_ISP1_PARAMS;
+ params->vdev_fmt.fmt.meta.buffersize =
+ sizeof(struct rkisp1_params_cfg);
+}
+
+int rkisp1_params_register(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_params *params = &rkisp1->params;
+ struct rkisp1_vdev_node *node = &params->vnode;
+ struct video_device *vdev = &node->vdev;
+ int ret;
+
+ params->rkisp1 = rkisp1;
+ mutex_init(&node->vlock);
+ INIT_LIST_HEAD(&params->params);
+ spin_lock_init(&params->config_lock);
+
+ strscpy(vdev->name, RKISP1_PARAMS_DEV_NAME, sizeof(vdev->name));
+
+ video_set_drvdata(vdev, params);
+ vdev->ioctl_ops = &rkisp1_params_ioctl;
+ vdev->fops = &rkisp1_params_fops;
+ vdev->release = video_device_release_empty;
+ /*
+ * Provide a mutex to v4l2 core. It will be used
+ * to protect all fops and v4l2 ioctls.
+ */
+ vdev->lock = &node->vlock;
+ vdev->v4l2_dev = &rkisp1->v4l2_dev;
+ vdev->queue = &node->buf_queue;
+ vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_META_OUTPUT;
+ vdev->vfl_dir = VFL_DIR_TX;
+ rkisp1_params_init_vb2_queue(vdev->queue, params);
+ rkisp1_init_params(params);
+ video_set_drvdata(vdev, params);
+
+ node->pad.flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
+ if (ret)
+ return ret;
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ dev_err(rkisp1->dev,
+ "failed to register %s, ret=%d\n", vdev->name, ret);
+ goto err_cleanup_media_entity;
+ }
+ return 0;
+err_cleanup_media_entity:
+ media_entity_cleanup(&vdev->entity);
+ return ret;
+}
+
+void rkisp1_params_unregister(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_params *params = &rkisp1->params;
+ struct rkisp1_vdev_node *node = &params->vnode;
+ struct video_device *vdev = &node->vdev;
+
+ vb2_video_unregister_device(vdev);
+ media_entity_cleanup(&vdev->entity);
+}
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
new file mode 100644
index 000000000000..8a8d960a679c
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
@@ -0,0 +1,1262 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Rockchip ISP1 Driver - Registers header
+ *
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _RKISP1_REGS_H
+#define _RKISP1_REGS_H
+
+/* ISP_CTRL */
+#define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
+#define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
+#define RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656 BIT(1)
+#define RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601 (2 << 1)
+#define RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601 (3 << 1)
+#define RKISP1_CIF_ISP_CTRL_ISP_MODE_DATA_MODE (4 << 1)
+#define RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656 (5 << 1)
+#define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656 (6 << 1)
+#define RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE BIT(4)
+#define RKISP1_CIF_ISP_CTRL_ISP_GAMMA_IN_ENA BIT(6)
+#define RKISP1_CIF_ISP_CTRL_ISP_AWB_ENA BIT(7)
+#define RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT BIT(8)
+#define RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD BIT(9)
+#define RKISP1_CIF_ISP_CTRL_ISP_GEN_CFG_UPD BIT(10)
+#define RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA BIT(11)
+#define RKISP1_CIF_ISP_CTRL_ISP_FLASH_MODE_ENA BIT(12)
+#define RKISP1_CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA BIT(13)
+#define RKISP1_CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA BIT(14)
+
+/* ISP_ACQ_PROP */
+#define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
+#define RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW BIT(1)
+#define RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW BIT(2)
+#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
+#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_GRBG BIT(3)
+#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_GBRG (2 << 3)
+#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_BGGR (3 << 3)
+#define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(pat) ((pat) << 3)
+#define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
+#define RKISP1_CIF_ISP_ACQ_PROP_YCRYCB BIT(7)
+#define RKISP1_CIF_ISP_ACQ_PROP_CBYCRY (2 << 7)
+#define RKISP1_CIF_ISP_ACQ_PROP_CRYCBY (3 << 7)
+#define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
+#define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_EVEN BIT(9)
+#define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ODD (2 << 9)
+#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
+#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO BIT(12)
+#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_MSB (2 << 12)
+#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO (3 << 12)
+#define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_MSB (4 << 12)
+
+/* VI_DPCL */
+#define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
+#define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
+#define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
+#define RKISP1_CIF_VI_DPCL_CHAN_MODE_MP BIT(2)
+#define RKISP1_CIF_VI_DPCL_CHAN_MODE_SP (2 << 2)
+#define RKISP1_CIF_VI_DPCL_CHAN_MODE_MPSP (3 << 2)
+#define RKISP1_CIF_VI_DPCL_DMA_SW_SPMUX (0 << 4)
+#define RKISP1_CIF_VI_DPCL_DMA_SW_SI BIT(4)
+#define RKISP1_CIF_VI_DPCL_DMA_SW_IE (2 << 4)
+#define RKISP1_CIF_VI_DPCL_DMA_SW_JPEG (3 << 4)
+#define RKISP1_CIF_VI_DPCL_DMA_SW_ISP (4 << 4)
+#define RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL (0 << 8)
+#define RKISP1_CIF_VI_DPCL_IF_SEL_SMIA BIT(8)
+#define RKISP1_CIF_VI_DPCL_IF_SEL_MIPI (2 << 8)
+#define RKISP1_CIF_VI_DPCL_DMA_IE_MUX_DMA BIT(10)
+#define RKISP1_CIF_VI_DPCL_DMA_SP_MUX_DMA BIT(11)
+
+/* ISP_IMSC - ISP_MIS - ISP_RIS - ISP_ICR - ISP_ISR */
+#define RKISP1_CIF_ISP_OFF BIT(0)
+#define RKISP1_CIF_ISP_FRAME BIT(1)
+#define RKISP1_CIF_ISP_DATA_LOSS BIT(2)
+#define RKISP1_CIF_ISP_PIC_SIZE_ERROR BIT(3)
+#define RKISP1_CIF_ISP_AWB_DONE BIT(4)
+#define RKISP1_CIF_ISP_FRAME_IN BIT(5)
+#define RKISP1_CIF_ISP_V_START BIT(6)
+#define RKISP1_CIF_ISP_H_START BIT(7)
+#define RKISP1_CIF_ISP_FLASH_ON BIT(8)
+#define RKISP1_CIF_ISP_FLASH_OFF BIT(9)
+#define RKISP1_CIF_ISP_SHUTTER_ON BIT(10)
+#define RKISP1_CIF_ISP_SHUTTER_OFF BIT(11)
+#define RKISP1_CIF_ISP_AFM_SUM_OF BIT(12)
+#define RKISP1_CIF_ISP_AFM_LUM_OF BIT(13)
+#define RKISP1_CIF_ISP_AFM_FIN BIT(14)
+#define RKISP1_CIF_ISP_HIST_MEASURE_RDY BIT(15)
+#define RKISP1_CIF_ISP_FLASH_CAP BIT(17)
+#define RKISP1_CIF_ISP_EXP_END BIT(18)
+#define RKISP1_CIF_ISP_VSM_END BIT(19)
+
+/* ISP_ERR */
+#define RKISP1_CIF_ISP_ERR_INFORM_SIZE BIT(0)
+#define RKISP1_CIF_ISP_ERR_IS_SIZE BIT(1)
+#define RKISP1_CIF_ISP_ERR_OUTFORM_SIZE BIT(2)
+
+/* MI_CTRL */
+#define RKISP1_CIF_MI_CTRL_MP_ENABLE BIT(0)
+#define RKISP1_CIF_MI_CTRL_SP_ENABLE (2 << 0)
+#define RKISP1_CIF_MI_CTRL_JPEG_ENABLE (4 << 0)
+#define RKISP1_CIF_MI_CTRL_RAW_ENABLE (8 << 0)
+#define RKISP1_CIF_MI_CTRL_HFLIP BIT(4)
+#define RKISP1_CIF_MI_CTRL_VFLIP BIT(5)
+#define RKISP1_CIF_MI_CTRL_ROT BIT(6)
+#define RKISP1_CIF_MI_BYTE_SWAP BIT(7)
+#define RKISP1_CIF_MI_SP_Y_FULL_YUV2RGB BIT(8)
+#define RKISP1_CIF_MI_SP_CBCR_FULL_YUV2RGB BIT(9)
+#define RKISP1_CIF_MI_SP_422NONCOSITEED BIT(10)
+#define RKISP1_CIF_MI_MP_PINGPONG_ENABLE BIT(11)
+#define RKISP1_CIF_MI_SP_PINGPONG_ENABLE BIT(12)
+#define RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE BIT(13)
+#define RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE BIT(14)
+#define RKISP1_CIF_MI_LAST_PIXEL_SIG_ENABLE BIT(15)
+#define RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_16 (0 << 16)
+#define RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_32 BIT(16)
+#define RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64 (2 << 16)
+#define RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_16 (0 << 18)
+#define RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_32 BIT(18)
+#define RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64 (2 << 18)
+#define RKISP1_CIF_MI_CTRL_INIT_BASE_EN BIT(20)
+#define RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN BIT(21)
+#define RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8 (0 << 22)
+#define RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA BIT(22)
+#define RKISP1_MI_CTRL_MP_WRITE_YUVINT (2 << 22)
+#define RKISP1_MI_CTRL_MP_WRITE_RAW12 (2 << 22)
+#define RKISP1_MI_CTRL_SP_WRITE_PLA (0 << 24)
+#define RKISP1_MI_CTRL_SP_WRITE_SPLA BIT(24)
+#define RKISP1_MI_CTRL_SP_WRITE_INT (2 << 24)
+#define RKISP1_MI_CTRL_SP_INPUT_YUV400 (0 << 26)
+#define RKISP1_MI_CTRL_SP_INPUT_YUV420 BIT(26)
+#define RKISP1_MI_CTRL_SP_INPUT_YUV422 (2 << 26)
+#define RKISP1_MI_CTRL_SP_INPUT_YUV444 (3 << 26)
+#define RKISP1_MI_CTRL_SP_OUTPUT_YUV400 (0 << 28)
+#define RKISP1_MI_CTRL_SP_OUTPUT_YUV420 BIT(28)
+#define RKISP1_MI_CTRL_SP_OUTPUT_YUV422 (2 << 28)
+#define RKISP1_MI_CTRL_SP_OUTPUT_YUV444 (3 << 28)
+#define RKISP1_MI_CTRL_SP_OUTPUT_RGB565 (4 << 28)
+#define RKISP1_MI_CTRL_SP_OUTPUT_RGB666 (5 << 28)
+#define RKISP1_MI_CTRL_SP_OUTPUT_RGB888 (6 << 28)
+
+#define RKISP1_MI_CTRL_MP_FMT_MASK GENMASK(23, 22)
+#define RKISP1_MI_CTRL_SP_FMT_MASK GENMASK(30, 24)
+
+/* MI_INIT */
+#define RKISP1_CIF_MI_INIT_SKIP BIT(2)
+#define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4)
+
+/* MI_CTRL_SHD */
+#define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
+#define RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED BIT(1)
+#define RKISP1_CIF_MI_CTRL_SHD_JPEG_IN_ENABLED BIT(2)
+#define RKISP1_CIF_MI_CTRL_SHD_RAW_IN_ENABLED BIT(3)
+#define RKISP1_CIF_MI_CTRL_SHD_MP_OUT_ENABLED BIT(16)
+#define RKISP1_CIF_MI_CTRL_SHD_SP_OUT_ENABLED BIT(17)
+#define RKISP1_CIF_MI_CTRL_SHD_JPEG_OUT_ENABLED BIT(18)
+#define RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED BIT(19)
+
+/* RSZ_CTRL */
+#define RKISP1_CIF_RSZ_CTRL_SCALE_HY_ENABLE BIT(0)
+#define RKISP1_CIF_RSZ_CTRL_SCALE_HC_ENABLE BIT(1)
+#define RKISP1_CIF_RSZ_CTRL_SCALE_VY_ENABLE BIT(2)
+#define RKISP1_CIF_RSZ_CTRL_SCALE_VC_ENABLE BIT(3)
+#define RKISP1_CIF_RSZ_CTRL_SCALE_HY_UP BIT(4)
+#define RKISP1_CIF_RSZ_CTRL_SCALE_HC_UP BIT(5)
+#define RKISP1_CIF_RSZ_CTRL_SCALE_VY_UP BIT(6)
+#define RKISP1_CIF_RSZ_CTRL_SCALE_VC_UP BIT(7)
+#define RKISP1_CIF_RSZ_CTRL_CFG_UPD BIT(8)
+#define RKISP1_CIF_RSZ_CTRL_CFG_UPD_AUTO BIT(9)
+#define RKISP1_CIF_RSZ_SCALER_FACTOR BIT(16)
+
+/* MI_IMSC - MI_MIS - MI_RIS - MI_ICR - MI_ISR */
+#define RKISP1_CIF_MI_FRAME(stream) BIT((stream)->id)
+#define RKISP1_CIF_MI_MBLK_LINE BIT(2)
+#define RKISP1_CIF_MI_FILL_MP_Y BIT(3)
+#define RKISP1_CIF_MI_WRAP_MP_Y BIT(4)
+#define RKISP1_CIF_MI_WRAP_MP_CB BIT(5)
+#define RKISP1_CIF_MI_WRAP_MP_CR BIT(6)
+#define RKISP1_CIF_MI_WRAP_SP_Y BIT(7)
+#define RKISP1_CIF_MI_WRAP_SP_CB BIT(8)
+#define RKISP1_CIF_MI_WRAP_SP_CR BIT(9)
+#define RKISP1_CIF_MI_DMA_READY BIT(11)
+
+/* MI_STATUS */
+#define RKISP1_CIF_MI_STATUS_MP_Y_FIFO_FULL BIT(0)
+#define RKISP1_CIF_MI_STATUS_SP_Y_FIFO_FULL BIT(4)
+
+/* MI_DMA_CTRL */
+#define RKISP1_CIF_MI_DMA_CTRL_BURST_LEN_LUM_16 (0 << 0)
+#define RKISP1_CIF_MI_DMA_CTRL_BURST_LEN_LUM_32 BIT(0)
+#define RKISP1_CIF_MI_DMA_CTRL_BURST_LEN_LUM_64 (2 << 0)
+#define RKISP1_CIF_MI_DMA_CTRL_BURST_LEN_CHROM_16 (0 << 2)
+#define RKISP1_CIF_MI_DMA_CTRL_BURST_LEN_CHROM_32 BIT(2)
+#define RKISP1_CIF_MI_DMA_CTRL_BURST_LEN_CHROM_64 (2 << 2)
+#define RKISP1_CIF_MI_DMA_CTRL_READ_FMT_PLANAR (0 << 4)
+#define RKISP1_CIF_MI_DMA_CTRL_READ_FMT_SPLANAR BIT(4)
+#define RKISP1_CIF_MI_DMA_CTRL_FMT_YUV400 (0 << 6)
+#define RKISP1_CIF_MI_DMA_CTRL_FMT_YUV420 BIT(6)
+#define RKISP1_CIF_MI_DMA_CTRL_READ_FMT_PACKED (2 << 4)
+#define RKISP1_CIF_MI_DMA_CTRL_FMT_YUV422 (2 << 6)
+#define RKISP1_CIF_MI_DMA_CTRL_FMT_YUV444 (3 << 6)
+#define RKISP1_CIF_MI_DMA_CTRL_BYTE_SWAP BIT(8)
+#define RKISP1_CIF_MI_DMA_CTRL_CONTINUOUS_ENA BIT(9)
+#define RKISP1_CIF_MI_DMA_CTRL_RGB_BAYER_NO (0 << 12)
+#define RKISP1_CIF_MI_DMA_CTRL_RGB_BAYER_8BIT BIT(12)
+#define RKISP1_CIF_MI_DMA_CTRL_RGB_BAYER_16BIT (2 << 12)
+/* MI_DMA_START */
+#define RKISP1_CIF_MI_DMA_START_ENABLE BIT(0)
+/* MI_XTD_FORMAT_CTRL */
+#define RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP BIT(0)
+#define RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1)
+#define RKISP1_CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2)
+
+/* CCL */
+#define RKISP1_CIF_CCL_CIF_CLK_DIS BIT(2)
+/* ICCL */
+#define RKISP1_CIF_ICCL_ISP_CLK BIT(0)
+#define RKISP1_CIF_ICCL_CP_CLK BIT(1)
+#define RKISP1_CIF_ICCL_RES_2 BIT(2)
+#define RKISP1_CIF_ICCL_MRSZ_CLK BIT(3)
+#define RKISP1_CIF_ICCL_SRSZ_CLK BIT(4)
+#define RKISP1_CIF_ICCL_JPEG_CLK BIT(5)
+#define RKISP1_CIF_ICCL_MI_CLK BIT(6)
+#define RKISP1_CIF_ICCL_RES_7 BIT(7)
+#define RKISP1_CIF_ICCL_IE_CLK BIT(8)
+#define RKISP1_CIF_ICCL_SIMP_CLK BIT(9)
+#define RKISP1_CIF_ICCL_SMIA_CLK BIT(10)
+#define RKISP1_CIF_ICCL_MIPI_CLK BIT(11)
+#define RKISP1_CIF_ICCL_DCROP_CLK BIT(12)
+/* IRCL */
+#define RKISP1_CIF_IRCL_ISP_SW_RST BIT(0)
+#define RKISP1_CIF_IRCL_CP_SW_RST BIT(1)
+#define RKISP1_CIF_IRCL_YCS_SW_RST BIT(2)
+#define RKISP1_CIF_IRCL_MRSZ_SW_RST BIT(3)
+#define RKISP1_CIF_IRCL_SRSZ_SW_RST BIT(4)
+#define RKISP1_CIF_IRCL_JPEG_SW_RST BIT(5)
+#define RKISP1_CIF_IRCL_MI_SW_RST BIT(6)
+#define RKISP1_CIF_IRCL_CIF_SW_RST BIT(7)
+#define RKISP1_CIF_IRCL_IE_SW_RST BIT(8)
+#define RKISP1_CIF_IRCL_SI_SW_RST BIT(9)
+#define RKISP1_CIF_IRCL_MIPI_SW_RST BIT(11)
+
+/* C_PROC_CTR */
+#define RKISP1_CIF_C_PROC_CTR_ENABLE BIT(0)
+#define RKISP1_CIF_C_PROC_YOUT_FULL BIT(1)
+#define RKISP1_CIF_C_PROC_YIN_FULL BIT(2)
+#define RKISP1_CIF_C_PROC_COUT_FULL BIT(3)
+#define RKISP1_CIF_C_PROC_CTRL_RESERVED 0xFFFFFFFE
+#define RKISP1_CIF_C_PROC_CONTRAST_RESERVED 0xFFFFFF00
+#define RKISP1_CIF_C_PROC_BRIGHTNESS_RESERVED 0xFFFFFF00
+#define RKISP1_CIF_C_PROC_HUE_RESERVED 0xFFFFFF00
+#define RKISP1_CIF_C_PROC_SATURATION_RESERVED 0xFFFFFF00
+#define RKISP1_CIF_C_PROC_MACC_RESERVED 0xE000E000
+#define RKISP1_CIF_C_PROC_TONE_RESERVED 0xF000
+/* DUAL_CROP_CTRL */
+#define RKISP1_CIF_DUAL_CROP_MP_MODE_BYPASS (0 << 0)
+#define RKISP1_CIF_DUAL_CROP_MP_MODE_YUV BIT(0)
+#define RKISP1_CIF_DUAL_CROP_MP_MODE_RAW (2 << 0)
+#define RKISP1_CIF_DUAL_CROP_SP_MODE_BYPASS (0 << 2)
+#define RKISP1_CIF_DUAL_CROP_SP_MODE_YUV BIT(2)
+#define RKISP1_CIF_DUAL_CROP_SP_MODE_RAW (2 << 2)
+#define RKISP1_CIF_DUAL_CROP_CFG_UPD_PERMANENT BIT(4)
+#define RKISP1_CIF_DUAL_CROP_CFG_UPD BIT(5)
+#define RKISP1_CIF_DUAL_CROP_GEN_CFG_UPD BIT(6)
+
+/* IMG_EFF_CTRL */
+#define RKISP1_CIF_IMG_EFF_CTRL_ENABLE BIT(0)
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_BLACKWHITE (0 << 1)
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_NEGATIVE BIT(1)
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_SEPIA (2 << 1)
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_COLOR_SEL (3 << 1)
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_EMBOSS (4 << 1)
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_SKETCH (5 << 1)
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_SHARPEN (6 << 1)
+#define RKISP1_CIF_IMG_EFF_CTRL_CFG_UPD BIT(4)
+#define RKISP1_CIF_IMG_EFF_CTRL_YCBCR_FULL BIT(5)
+
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_BLACKWHITE_SHIFT 0
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_NEGATIVE_SHIFT 1
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_SEPIA_SHIFT 2
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_COLOR_SEL_SHIFT 3
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT 4
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_SKETCH_SHIFT 5
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_SHARPEN_SHIFT 6
+#define RKISP1_CIF_IMG_EFF_CTRL_MODE_MASK 0xE
+
+/* IMG_EFF_COLOR_SEL */
+#define RKISP1_CIF_IMG_EFF_COLOR_RGB 0
+#define RKISP1_CIF_IMG_EFF_COLOR_B BIT(0)
+#define RKISP1_CIF_IMG_EFF_COLOR_G (2 << 0)
+#define RKISP1_CIF_IMG_EFF_COLOR_GB (3 << 0)
+#define RKISP1_CIF_IMG_EFF_COLOR_R (4 << 0)
+#define RKISP1_CIF_IMG_EFF_COLOR_RB (5 << 0)
+#define RKISP1_CIF_IMG_EFF_COLOR_RG (6 << 0)
+#define RKISP1_CIF_IMG_EFF_COLOR_RGB2 (7 << 0)
+
+/* MIPI_CTRL */
+#define RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA BIT(0)
+#define RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(a) (((a) & 0xF) << 8)
+#define RKISP1_CIF_MIPI_CTRL_NUM_LANES(a) (((a) & 0x3) << 12)
+#define RKISP1_CIF_MIPI_CTRL_ERR_SOT_HS_SKIP BIT(16)
+#define RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP BIT(17)
+#define RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA BIT(18)
+
+/* MIPI_DATA_SEL */
+#define RKISP1_CIF_MIPI_DATA_SEL_VC(a) (((a) & 0x3) << 6)
+#define RKISP1_CIF_MIPI_DATA_SEL_DT(a) (((a) & 0x3F) << 0)
+/* MIPI DATA_TYPE */
+#define RKISP1_CIF_CSI2_DT_YUV420_8b 0x18
+#define RKISP1_CIF_CSI2_DT_YUV420_10b 0x19
+#define RKISP1_CIF_CSI2_DT_YUV422_8b 0x1E
+#define RKISP1_CIF_CSI2_DT_YUV422_10b 0x1F
+#define RKISP1_CIF_CSI2_DT_RGB565 0x22
+#define RKISP1_CIF_CSI2_DT_RGB666 0x23
+#define RKISP1_CIF_CSI2_DT_RGB888 0x24
+#define RKISP1_CIF_CSI2_DT_RAW8 0x2A
+#define RKISP1_CIF_CSI2_DT_RAW10 0x2B
+#define RKISP1_CIF_CSI2_DT_RAW12 0x2C
+
+/* MIPI_IMSC, MIPI_RIS, MIPI_MIS, MIPI_ICR, MIPI_ISR */
+#define RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(a) (((a) & 0xF) << 0)
+#define RKISP1_CIF_MIPI_ERR_SOT(a) (((a) & 0xF) << 4)
+#define RKISP1_CIF_MIPI_ERR_SOT_SYNC(a) (((a) & 0xF) << 8)
+#define RKISP1_CIF_MIPI_ERR_EOT_SYNC(a) (((a) & 0xF) << 12)
+#define RKISP1_CIF_MIPI_ERR_CTRL(a) (((a) & 0xF) << 16)
+#define RKISP1_CIF_MIPI_ERR_PROTOCOL BIT(20)
+#define RKISP1_CIF_MIPI_ERR_ECC1 BIT(21)
+#define RKISP1_CIF_MIPI_ERR_ECC2 BIT(22)
+#define RKISP1_CIF_MIPI_ERR_CS BIT(23)
+#define RKISP1_CIF_MIPI_FRAME_END BIT(24)
+#define RKISP1_CIF_MIPI_ADD_DATA_OVFLW BIT(25)
+#define RKISP1_CIF_MIPI_ADD_DATA_WATER_MARK BIT(26)
+
+#define RKISP1_CIF_MIPI_ERR_CSI (RKISP1_CIF_MIPI_ERR_PROTOCOL | \
+ RKISP1_CIF_MIPI_ERR_ECC1 | \
+ RKISP1_CIF_MIPI_ERR_ECC2 | \
+ RKISP1_CIF_MIPI_ERR_CS)
+
+#define RKISP1_CIF_MIPI_ERR_DPHY (RKISP1_CIF_MIPI_ERR_SOT(3) | \
+ RKISP1_CIF_MIPI_ERR_SOT_SYNC(3) | \
+ RKISP1_CIF_MIPI_ERR_EOT_SYNC(3) | \
+ RKISP1_CIF_MIPI_ERR_CTRL(3))
+
+/* SUPER_IMPOSE */
+#define RKISP1_CIF_SUPER_IMP_CTRL_NORMAL_MODE BIT(0)
+#define RKISP1_CIF_SUPER_IMP_CTRL_REF_IMG_MEM BIT(1)
+#define RKISP1_CIF_SUPER_IMP_CTRL_TRANSP_DIS BIT(2)
+
+/* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_DIS (0 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_RGB BIT(0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_RED (2 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_GREEN (3 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_BLUE (4 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_LUM (5 << 0)
+#define RKISP1_CIF_ISP_HIST_PROP_MODE_MASK 0x7
+#define RKISP1_CIF_ISP_HIST_PREDIV_SET(x) (((x) & 0x7F) << 3)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3) \
+ (((v0) & 0x1F) | (((v1) & 0x1F) << 8) |\
+ (((v2) & 0x1F) << 16) | \
+ (((v3) & 0x1F) << 24))
+
+#define RKISP1_CIF_ISP_HIST_WINDOW_OFFSET_RESERVED 0xFFFFF000
+#define RKISP1_CIF_ISP_HIST_WINDOW_SIZE_RESERVED 0xFFFFF800
+#define RKISP1_CIF_ISP_HIST_WEIGHT_RESERVED 0xE0E0E0E0
+#define RKISP1_CIF_ISP_MAX_HIST_PREDIVIDER 0x0000007F
+#define RKISP1_CIF_ISP_HIST_ROW_NUM 5
+#define RKISP1_CIF_ISP_HIST_COLUMN_NUM 5
+
+/* AUTO FOCUS MEASUREMENT: ISP_AFM_CTRL */
+#define RKISP1_ISP_AFM_CTRL_ENABLE BIT(0)
+
+/* SHUTTER CONTROL */
+#define RKISP1_CIF_ISP_SH_CTRL_SH_ENA BIT(0)
+#define RKISP1_CIF_ISP_SH_CTRL_REP_EN BIT(1)
+#define RKISP1_CIF_ISP_SH_CTRL_SRC_SH_TRIG BIT(2)
+#define RKISP1_CIF_ISP_SH_CTRL_EDGE_POS BIT(3)
+#define RKISP1_CIF_ISP_SH_CTRL_POL_LOW BIT(4)
+
+/* FLASH MODULE */
+/* ISP_FLASH_CMD */
+#define RKISP1_CIFFLASH_CMD_PRELIGHT_ON BIT(0)
+#define RKISP1_CIFFLASH_CMD_FLASH_ON BIT(1)
+#define RKISP1_CIFFLASH_CMD_PRE_FLASH_ON BIT(2)
+/* ISP_FLASH_CONFIG */
+#define RKISP1_CIFFLASH_CONFIG_PRELIGHT_END BIT(0)
+#define RKISP1_CIFFLASH_CONFIG_VSYNC_POS BIT(1)
+#define RKISP1_CIFFLASH_CONFIG_PRELIGHT_LOW BIT(2)
+#define RKISP1_CIFFLASH_CONFIG_SRC_FL_TRIG BIT(3)
+#define RKISP1_CIFFLASH_CONFIG_DELAY(a) (((a) & 0xF) << 4)
+
+/* Demosaic: ISP_DEMOSAIC */
+#define RKISP1_CIF_ISP_DEMOSAIC_BYPASS BIT(10)
+#define RKISP1_CIF_ISP_DEMOSAIC_TH(x) ((x) & 0xFF)
+
+/* AWB */
+/* ISP_AWB_PROP */
+#define RKISP1_CIF_ISP_AWB_YMAX_CMP_EN BIT(2)
+#define RKISP1_CIF_ISP_AWB_YMAX_READ(x) (((x) >> 2) & 1)
+#define RKISP1_CIF_ISP_AWB_MODE_RGB_EN ((1 << 31) | (0x2 << 0))
+#define RKISP1_CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0))
+#define RKISP1_CIF_ISP_AWB_MODE_MASK_NONE 0xFFFFFFFC
+#define RKISP1_CIF_ISP_AWB_MODE_READ(x) ((x) & 3)
+/* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G */
+#define RKISP1_CIF_ISP_AWB_GAIN_R_SET(x) (((x) & 0x3FF) << 16)
+#define RKISP1_CIF_ISP_AWB_GAIN_R_READ(x) (((x) >> 16) & 0x3FF)
+#define RKISP1_CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FFF)
+#define RKISP1_CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FFF)
+/* ISP_AWB_REF */
+#define RKISP1_CIF_ISP_AWB_REF_CR_SET(x) (((x) & 0xFF) << 8)
+#define RKISP1_CIF_ISP_AWB_REF_CR_READ(x) (((x) >> 8) & 0xFF)
+#define RKISP1_CIF_ISP_AWB_REF_CB_READ(x) ((x) & 0xFF)
+/* ISP_AWB_THRESH */
+#define RKISP1_CIF_ISP_AWB_MAX_CS_SET(x) (((x) & 0xFF) << 8)
+#define RKISP1_CIF_ISP_AWB_MAX_CS_READ(x) (((x) >> 8) & 0xFF)
+#define RKISP1_CIF_ISP_AWB_MIN_C_READ(x) ((x) & 0xFF)
+#define RKISP1_CIF_ISP_AWB_MIN_Y_SET(x) (((x) & 0xFF) << 16)
+#define RKISP1_CIF_ISP_AWB_MIN_Y_READ(x) (((x) >> 16) & 0xFF)
+#define RKISP1_CIF_ISP_AWB_MAX_Y_SET(x) (((x) & 0xFF) << 24)
+#define RKISP1_CIF_ISP_AWB_MAX_Y_READ(x) (((x) >> 24) & 0xFF)
+/* ISP_AWB_MEAN */
+#define RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(x) ((x) & 0xFF)
+#define RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(x) (((x) >> 8) & 0xFF)
+#define RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(x) (((x) >> 16) & 0xFF)
+/* ISP_AWB_WHITE_CNT */
+#define RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(x) ((x) & 0x3FFFFFF)
+
+#define RKISP1_CIF_ISP_AWB_GAINS_MAX_VAL 0x000003FF
+#define RKISP1_CIF_ISP_AWB_WINDOW_OFFSET_MAX 0x00000FFF
+#define RKISP1_CIF_ISP_AWB_WINDOW_MAX_SIZE 0x00001FFF
+#define RKISP1_CIF_ISP_AWB_CBCR_MAX_REF 0x000000FF
+#define RKISP1_CIF_ISP_AWB_THRES_MAX_YC 0x000000FF
+
+/* AE */
+/* ISP_EXP_CTRL */
+#define RKISP1_CIF_ISP_EXP_ENA BIT(0)
+#define RKISP1_CIF_ISP_EXP_CTRL_AUTOSTOP BIT(1)
+/*
+ *'1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)
+ *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
+ */
+#define RKISP1_CIF_ISP_EXP_CTRL_MEASMODE_1 BIT(31)
+
+/* ISP_EXP_H_SIZE */
+#define RKISP1_CIF_ISP_EXP_H_SIZE_SET(x) ((x) & 0x7FF)
+#define RKISP1_CIF_ISP_EXP_HEIGHT_MASK 0x000007FF
+/* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
+#define RKISP1_CIF_ISP_EXP_V_SIZE_SET(x) ((x) & 0x7FE)
+
+/* ISP_EXP_H_OFFSET */
+#define RKISP1_CIF_ISP_EXP_H_OFFSET_SET(x) ((x) & 0x1FFF)
+#define RKISP1_CIF_ISP_EXP_MAX_HOFFS 2424
+/* ISP_EXP_V_OFFSET */
+#define RKISP1_CIF_ISP_EXP_V_OFFSET_SET(x) ((x) & 0x1FFF)
+#define RKISP1_CIF_ISP_EXP_MAX_VOFFS 1806
+
+#define RKISP1_CIF_ISP_EXP_ROW_NUM 5
+#define RKISP1_CIF_ISP_EXP_COLUMN_NUM 5
+#define RKISP1_CIF_ISP_EXP_NUM_LUMA_REGS \
+ (RKISP1_CIF_ISP_EXP_ROW_NUM * RKISP1_CIF_ISP_EXP_COLUMN_NUM)
+#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE 516
+#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE 35
+#define RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE 390
+#define RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE 28
+#define RKISP1_CIF_ISP_EXP_MAX_HSIZE \
+ (RKISP1_CIF_ISP_EXP_BLOCK_MAX_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
+#define RKISP1_CIF_ISP_EXP_MIN_HSIZE \
+ (RKISP1_CIF_ISP_EXP_BLOCK_MIN_HSIZE * RKISP1_CIF_ISP_EXP_COLUMN_NUM + 1)
+#define RKISP1_CIF_ISP_EXP_MAX_VSIZE \
+ (RKISP1_CIF_ISP_EXP_BLOCK_MAX_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
+#define RKISP1_CIF_ISP_EXP_MIN_VSIZE \
+ (RKISP1_CIF_ISP_EXP_BLOCK_MIN_VSIZE * RKISP1_CIF_ISP_EXP_ROW_NUM + 1)
+
+/* LSC: ISP_LSC_CTRL */
+#define RKISP1_CIF_ISP_LSC_CTRL_ENA BIT(0)
+#define RKISP1_CIF_ISP_LSC_SECT_SIZE_RESERVED 0xFC00FC00
+#define RKISP1_CIF_ISP_LSC_GRAD_RESERVED 0xF000F000
+#define RKISP1_CIF_ISP_LSC_SAMPLE_RESERVED 0xF000F000
+#define RKISP1_CIF_ISP_LSC_TABLE_DATA(v0, v1) \
+ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
+#define RKISP1_CIF_ISP_LSC_SECT_SIZE(v0, v1) \
+ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
+#define RKISP1_CIF_ISP_LSC_GRAD_SIZE(v0, v1) \
+ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
+
+/* LSC: ISP_LSC_TABLE_SEL */
+#define RKISP1_CIF_ISP_LSC_TABLE_0 0
+#define RKISP1_CIF_ISP_LSC_TABLE_1 1
+
+/* LSC: ISP_LSC_STATUS */
+#define RKISP1_CIF_ISP_LSC_ACTIVE_TABLE BIT(1)
+#define RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_0 0
+#define RKISP1_CIF_ISP_LSC_TABLE_ADDRESS_153 153
+
+/* FLT */
+/* ISP_FILT_MODE */
+#define RKISP1_CIF_ISP_FLT_ENA BIT(0)
+
+/*
+ * 0: green filter static mode (active filter factor = FILT_FAC_MID)
+ * 1: dynamic noise reduction/sharpen Default
+ */
+#define RKISP1_CIF_ISP_FLT_MODE_DNR BIT(1)
+#define RKISP1_CIF_ISP_FLT_MODE_MAX 1
+#define RKISP1_CIF_ISP_FLT_CHROMA_V_MODE(x) (((x) & 0x3) << 4)
+#define RKISP1_CIF_ISP_FLT_CHROMA_H_MODE(x) (((x) & 0x3) << 6)
+#define RKISP1_CIF_ISP_FLT_CHROMA_MODE_MAX 3
+#define RKISP1_CIF_ISP_FLT_GREEN_STAGE1(x) (((x) & 0xF) << 8)
+#define RKISP1_CIF_ISP_FLT_GREEN_STAGE1_MAX 8
+#define RKISP1_CIF_ISP_FLT_THREAD_RESERVED 0xFFFFFC00
+#define RKISP1_CIF_ISP_FLT_FAC_RESERVED 0xFFFFFFC0
+#define RKISP1_CIF_ISP_FLT_LUM_WEIGHT_RESERVED 0xFFF80000
+
+#define RKISP1_CIF_ISP_CTK_COEFF_RESERVED 0xFFFFF800
+#define RKISP1_CIF_ISP_XTALK_OFFSET_RESERVED 0xFFFFF000
+
+/* GOC */
+#define RKISP1_CIF_ISP_GAMMA_OUT_MODE_EQU BIT(0)
+#define RKISP1_CIF_ISP_GOC_MODE_MAX 1
+#define RKISP1_CIF_ISP_GOC_RESERVED 0xFFFFF800
+/* ISP_CTRL BIT 11*/
+#define RKISP1_CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA_READ(x) (((x) >> 11) & 1)
+
+/* DPCC */
+/* ISP_DPCC_MODE */
+#define RKISP1_CIF_ISP_DPCC_ENA BIT(0)
+#define RKISP1_CIF_ISP_DPCC_MODE_MAX 0x07
+#define RKISP1_CIF_ISP_DPCC_OUTPUTMODE_MAX 0x0F
+#define RKISP1_CIF_ISP_DPCC_SETUSE_MAX 0x0F
+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RESERVED 0xFFFFE000
+#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_RESERVED 0xFFFF0000
+#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_RESERVED 0xFFFFC0C0
+#define RKISP1_CIF_ISP_DPCC_PG_FAC_RESERVED 0xFFFFC0C0
+#define RKISP1_CIF_ISP_DPCC_RND_THRESH_RESERVED 0xFFFF0000
+#define RKISP1_CIF_ISP_DPCC_RG_FAC_RESERVED 0xFFFFC0C0
+#define RKISP1_CIF_ISP_DPCC_RO_LIMIT_RESERVED 0xFFFFF000
+#define RKISP1_CIF_ISP_DPCC_RND_OFFS_RESERVED 0xFFFFF000
+
+/* BLS */
+/* ISP_BLS_CTRL */
+#define RKISP1_CIF_ISP_BLS_ENA BIT(0)
+#define RKISP1_CIF_ISP_BLS_MODE_MEASURED BIT(1)
+#define RKISP1_CIF_ISP_BLS_MODE_FIXED 0
+#define RKISP1_CIF_ISP_BLS_WINDOW_1 BIT(2)
+#define RKISP1_CIF_ISP_BLS_WINDOW_2 (2 << 2)
+
+/* GAMMA-IN */
+#define RKISP1_CIFISP_DEGAMMA_X_RESERVED \
+ ((1 << 31) | (1 << 27) | (1 << 23) | (1 << 19) |\
+ (1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
+#define RKISP1_CIFISP_DEGAMMA_Y_RESERVED 0xFFFFF000
+
+/* AFM */
+#define RKISP1_CIF_ISP_AFM_ENA BIT(0)
+#define RKISP1_CIF_ISP_AFM_THRES_RESERVED 0xFFFF0000
+#define RKISP1_CIF_ISP_AFM_VAR_SHIFT_RESERVED 0xFFF8FFF8
+#define RKISP1_CIF_ISP_AFM_WINDOW_X_RESERVED 0xE000
+#define RKISP1_CIF_ISP_AFM_WINDOW_Y_RESERVED 0xF000
+#define RKISP1_CIF_ISP_AFM_WINDOW_X_MIN 0x5
+#define RKISP1_CIF_ISP_AFM_WINDOW_Y_MIN 0x2
+#define RKISP1_CIF_ISP_AFM_WINDOW_X(x) (((x) & 0x1FFF) << 16)
+#define RKISP1_CIF_ISP_AFM_WINDOW_Y(x) ((x) & 0x1FFF)
+
+/* DPF */
+#define RKISP1_CIF_ISP_DPF_MODE_EN BIT(0)
+#define RKISP1_CIF_ISP_DPF_MODE_B_FLT_DIS BIT(1)
+#define RKISP1_CIF_ISP_DPF_MODE_GB_FLT_DIS BIT(2)
+#define RKISP1_CIF_ISP_DPF_MODE_GR_FLT_DIS BIT(3)
+#define RKISP1_CIF_ISP_DPF_MODE_R_FLT_DIS BIT(4)
+#define RKISP1_CIF_ISP_DPF_MODE_RB_FLTSIZE_9x9 BIT(5)
+#define RKISP1_CIF_ISP_DPF_MODE_NLL_SEGMENTATION BIT(6)
+#define RKISP1_CIF_ISP_DPF_MODE_AWB_GAIN_COMP BIT(7)
+#define RKISP1_CIF_ISP_DPF_MODE_LSC_GAIN_COMP BIT(8)
+#define RKISP1_CIF_ISP_DPF_MODE_USE_NF_GAIN BIT(9)
+#define RKISP1_CIF_ISP_DPF_NF_GAIN_RESERVED 0xFFFFF000
+#define RKISP1_CIF_ISP_DPF_SPATIAL_COEFF_MAX 0x1F
+#define RKISP1_CIF_ISP_DPF_NLL_COEFF_N_MAX 0x3FF
+
+/* =================================================================== */
+/* CIF Registers */
+/* =================================================================== */
+#define RKISP1_CIF_CTRL_BASE 0x00000000
+#define RKISP1_CIF_CCL (RKISP1_CIF_CTRL_BASE + 0x00000000)
+#define RKISP1_CIF_VI_ID (RKISP1_CIF_CTRL_BASE + 0x00000008)
+#define RKISP1_CIF_ICCL (RKISP1_CIF_CTRL_BASE + 0x00000010)
+#define RKISP1_CIF_IRCL (RKISP1_CIF_CTRL_BASE + 0x00000014)
+#define RKISP1_CIF_VI_DPCL (RKISP1_CIF_CTRL_BASE + 0x00000018)
+
+#define RKISP1_CIF_IMG_EFF_BASE 0x00000200
+#define RKISP1_CIF_IMG_EFF_CTRL (RKISP1_CIF_IMG_EFF_BASE + 0x00000000)
+#define RKISP1_CIF_IMG_EFF_COLOR_SEL (RKISP1_CIF_IMG_EFF_BASE + 0x00000004)
+#define RKISP1_CIF_IMG_EFF_MAT_1 (RKISP1_CIF_IMG_EFF_BASE + 0x00000008)
+#define RKISP1_CIF_IMG_EFF_MAT_2 (RKISP1_CIF_IMG_EFF_BASE + 0x0000000C)
+#define RKISP1_CIF_IMG_EFF_MAT_3 (RKISP1_CIF_IMG_EFF_BASE + 0x00000010)
+#define RKISP1_CIF_IMG_EFF_MAT_4 (RKISP1_CIF_IMG_EFF_BASE + 0x00000014)
+#define RKISP1_CIF_IMG_EFF_MAT_5 (RKISP1_CIF_IMG_EFF_BASE + 0x00000018)
+#define RKISP1_CIF_IMG_EFF_TINT (RKISP1_CIF_IMG_EFF_BASE + 0x0000001C)
+#define RKISP1_CIF_IMG_EFF_CTRL_SHD (RKISP1_CIF_IMG_EFF_BASE + 0x00000020)
+#define RKISP1_CIF_IMG_EFF_SHARPEN (RKISP1_CIF_IMG_EFF_BASE + 0x00000024)
+
+#define RKISP1_CIF_SUPER_IMP_BASE 0x00000300
+#define RKISP1_CIF_SUPER_IMP_CTRL (RKISP1_CIF_SUPER_IMP_BASE + 0x00000000)
+#define RKISP1_CIF_SUPER_IMP_OFFSET_X (RKISP1_CIF_SUPER_IMP_BASE + 0x00000004)
+#define RKISP1_CIF_SUPER_IMP_OFFSET_Y (RKISP1_CIF_SUPER_IMP_BASE + 0x00000008)
+#define RKISP1_CIF_SUPER_IMP_COLOR_Y (RKISP1_CIF_SUPER_IMP_BASE + 0x0000000C)
+#define RKISP1_CIF_SUPER_IMP_COLOR_CB (RKISP1_CIF_SUPER_IMP_BASE + 0x00000010)
+#define RKISP1_CIF_SUPER_IMP_COLOR_CR (RKISP1_CIF_SUPER_IMP_BASE + 0x00000014)
+
+#define RKISP1_CIF_ISP_BASE 0x00000400
+#define RKISP1_CIF_ISP_CTRL (RKISP1_CIF_ISP_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_ACQ_PROP (RKISP1_CIF_ISP_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_ACQ_H_OFFS (RKISP1_CIF_ISP_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_ACQ_V_OFFS (RKISP1_CIF_ISP_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_ACQ_H_SIZE (RKISP1_CIF_ISP_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_ACQ_V_SIZE (RKISP1_CIF_ISP_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_ACQ_NR_FRAMES (RKISP1_CIF_ISP_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_GAMMA_DX_LO (RKISP1_CIF_ISP_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_GAMMA_DX_HI (RKISP1_CIF_ISP_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_GAMMA_R_Y0 (RKISP1_CIF_ISP_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_GAMMA_R_Y1 (RKISP1_CIF_ISP_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_GAMMA_R_Y2 (RKISP1_CIF_ISP_BASE + 0x0000002C)
+#define RKISP1_CIF_ISP_GAMMA_R_Y3 (RKISP1_CIF_ISP_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_GAMMA_R_Y4 (RKISP1_CIF_ISP_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_GAMMA_R_Y5 (RKISP1_CIF_ISP_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_GAMMA_R_Y6 (RKISP1_CIF_ISP_BASE + 0x0000003C)
+#define RKISP1_CIF_ISP_GAMMA_R_Y7 (RKISP1_CIF_ISP_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_GAMMA_R_Y8 (RKISP1_CIF_ISP_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_GAMMA_R_Y9 (RKISP1_CIF_ISP_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_GAMMA_R_Y10 (RKISP1_CIF_ISP_BASE + 0x0000004C)
+#define RKISP1_CIF_ISP_GAMMA_R_Y11 (RKISP1_CIF_ISP_BASE + 0x00000050)
+#define RKISP1_CIF_ISP_GAMMA_R_Y12 (RKISP1_CIF_ISP_BASE + 0x00000054)
+#define RKISP1_CIF_ISP_GAMMA_R_Y13 (RKISP1_CIF_ISP_BASE + 0x00000058)
+#define RKISP1_CIF_ISP_GAMMA_R_Y14 (RKISP1_CIF_ISP_BASE + 0x0000005C)
+#define RKISP1_CIF_ISP_GAMMA_R_Y15 (RKISP1_CIF_ISP_BASE + 0x00000060)
+#define RKISP1_CIF_ISP_GAMMA_R_Y16 (RKISP1_CIF_ISP_BASE + 0x00000064)
+#define RKISP1_CIF_ISP_GAMMA_G_Y0 (RKISP1_CIF_ISP_BASE + 0x00000068)
+#define RKISP1_CIF_ISP_GAMMA_G_Y1 (RKISP1_CIF_ISP_BASE + 0x0000006C)
+#define RKISP1_CIF_ISP_GAMMA_G_Y2 (RKISP1_CIF_ISP_BASE + 0x00000070)
+#define RKISP1_CIF_ISP_GAMMA_G_Y3 (RKISP1_CIF_ISP_BASE + 0x00000074)
+#define RKISP1_CIF_ISP_GAMMA_G_Y4 (RKISP1_CIF_ISP_BASE + 0x00000078)
+#define RKISP1_CIF_ISP_GAMMA_G_Y5 (RKISP1_CIF_ISP_BASE + 0x0000007C)
+#define RKISP1_CIF_ISP_GAMMA_G_Y6 (RKISP1_CIF_ISP_BASE + 0x00000080)
+#define RKISP1_CIF_ISP_GAMMA_G_Y7 (RKISP1_CIF_ISP_BASE + 0x00000084)
+#define RKISP1_CIF_ISP_GAMMA_G_Y8 (RKISP1_CIF_ISP_BASE + 0x00000088)
+#define RKISP1_CIF_ISP_GAMMA_G_Y9 (RKISP1_CIF_ISP_BASE + 0x0000008C)
+#define RKISP1_CIF_ISP_GAMMA_G_Y10 (RKISP1_CIF_ISP_BASE + 0x00000090)
+#define RKISP1_CIF_ISP_GAMMA_G_Y11 (RKISP1_CIF_ISP_BASE + 0x00000094)
+#define RKISP1_CIF_ISP_GAMMA_G_Y12 (RKISP1_CIF_ISP_BASE + 0x00000098)
+#define RKISP1_CIF_ISP_GAMMA_G_Y13 (RKISP1_CIF_ISP_BASE + 0x0000009C)
+#define RKISP1_CIF_ISP_GAMMA_G_Y14 (RKISP1_CIF_ISP_BASE + 0x000000A0)
+#define RKISP1_CIF_ISP_GAMMA_G_Y15 (RKISP1_CIF_ISP_BASE + 0x000000A4)
+#define RKISP1_CIF_ISP_GAMMA_G_Y16 (RKISP1_CIF_ISP_BASE + 0x000000A8)
+#define RKISP1_CIF_ISP_GAMMA_B_Y0 (RKISP1_CIF_ISP_BASE + 0x000000AC)
+#define RKISP1_CIF_ISP_GAMMA_B_Y1 (RKISP1_CIF_ISP_BASE + 0x000000B0)
+#define RKISP1_CIF_ISP_GAMMA_B_Y2 (RKISP1_CIF_ISP_BASE + 0x000000B4)
+#define RKISP1_CIF_ISP_GAMMA_B_Y3 (RKISP1_CIF_ISP_BASE + 0x000000B8)
+#define RKISP1_CIF_ISP_GAMMA_B_Y4 (RKISP1_CIF_ISP_BASE + 0x000000BC)
+#define RKISP1_CIF_ISP_GAMMA_B_Y5 (RKISP1_CIF_ISP_BASE + 0x000000C0)
+#define RKISP1_CIF_ISP_GAMMA_B_Y6 (RKISP1_CIF_ISP_BASE + 0x000000C4)
+#define RKISP1_CIF_ISP_GAMMA_B_Y7 (RKISP1_CIF_ISP_BASE + 0x000000C8)
+#define RKISP1_CIF_ISP_GAMMA_B_Y8 (RKISP1_CIF_ISP_BASE + 0x000000CC)
+#define RKISP1_CIF_ISP_GAMMA_B_Y9 (RKISP1_CIF_ISP_BASE + 0x000000D0)
+#define RKISP1_CIF_ISP_GAMMA_B_Y10 (RKISP1_CIF_ISP_BASE + 0x000000D4)
+#define RKISP1_CIF_ISP_GAMMA_B_Y11 (RKISP1_CIF_ISP_BASE + 0x000000D8)
+#define RKISP1_CIF_ISP_GAMMA_B_Y12 (RKISP1_CIF_ISP_BASE + 0x000000DC)
+#define RKISP1_CIF_ISP_GAMMA_B_Y13 (RKISP1_CIF_ISP_BASE + 0x000000E0)
+#define RKISP1_CIF_ISP_GAMMA_B_Y14 (RKISP1_CIF_ISP_BASE + 0x000000E4)
+#define RKISP1_CIF_ISP_GAMMA_B_Y15 (RKISP1_CIF_ISP_BASE + 0x000000E8)
+#define RKISP1_CIF_ISP_GAMMA_B_Y16 (RKISP1_CIF_ISP_BASE + 0x000000EC)
+#define RKISP1_CIF_ISP_AWB_PROP (RKISP1_CIF_ISP_BASE + 0x00000110)
+#define RKISP1_CIF_ISP_AWB_WND_H_OFFS (RKISP1_CIF_ISP_BASE + 0x00000114)
+#define RKISP1_CIF_ISP_AWB_WND_V_OFFS (RKISP1_CIF_ISP_BASE + 0x00000118)
+#define RKISP1_CIF_ISP_AWB_WND_H_SIZE (RKISP1_CIF_ISP_BASE + 0x0000011C)
+#define RKISP1_CIF_ISP_AWB_WND_V_SIZE (RKISP1_CIF_ISP_BASE + 0x00000120)
+#define RKISP1_CIF_ISP_AWB_FRAMES (RKISP1_CIF_ISP_BASE + 0x00000124)
+#define RKISP1_CIF_ISP_AWB_REF (RKISP1_CIF_ISP_BASE + 0x00000128)
+#define RKISP1_CIF_ISP_AWB_THRESH (RKISP1_CIF_ISP_BASE + 0x0000012C)
+#define RKISP1_CIF_ISP_AWB_GAIN_G (RKISP1_CIF_ISP_BASE + 0x00000138)
+#define RKISP1_CIF_ISP_AWB_GAIN_RB (RKISP1_CIF_ISP_BASE + 0x0000013C)
+#define RKISP1_CIF_ISP_AWB_WHITE_CNT (RKISP1_CIF_ISP_BASE + 0x00000140)
+#define RKISP1_CIF_ISP_AWB_MEAN (RKISP1_CIF_ISP_BASE + 0x00000144)
+#define RKISP1_CIF_ISP_CC_COEFF_0 (RKISP1_CIF_ISP_BASE + 0x00000170)
+#define RKISP1_CIF_ISP_CC_COEFF_1 (RKISP1_CIF_ISP_BASE + 0x00000174)
+#define RKISP1_CIF_ISP_CC_COEFF_2 (RKISP1_CIF_ISP_BASE + 0x00000178)
+#define RKISP1_CIF_ISP_CC_COEFF_3 (RKISP1_CIF_ISP_BASE + 0x0000017C)
+#define RKISP1_CIF_ISP_CC_COEFF_4 (RKISP1_CIF_ISP_BASE + 0x00000180)
+#define RKISP1_CIF_ISP_CC_COEFF_5 (RKISP1_CIF_ISP_BASE + 0x00000184)
+#define RKISP1_CIF_ISP_CC_COEFF_6 (RKISP1_CIF_ISP_BASE + 0x00000188)
+#define RKISP1_CIF_ISP_CC_COEFF_7 (RKISP1_CIF_ISP_BASE + 0x0000018C)
+#define RKISP1_CIF_ISP_CC_COEFF_8 (RKISP1_CIF_ISP_BASE + 0x00000190)
+#define RKISP1_CIF_ISP_OUT_H_OFFS (RKISP1_CIF_ISP_BASE + 0x00000194)
+#define RKISP1_CIF_ISP_OUT_V_OFFS (RKISP1_CIF_ISP_BASE + 0x00000198)
+#define RKISP1_CIF_ISP_OUT_H_SIZE (RKISP1_CIF_ISP_BASE + 0x0000019C)
+#define RKISP1_CIF_ISP_OUT_V_SIZE (RKISP1_CIF_ISP_BASE + 0x000001A0)
+#define RKISP1_CIF_ISP_DEMOSAIC (RKISP1_CIF_ISP_BASE + 0x000001A4)
+#define RKISP1_CIF_ISP_FLAGS_SHD (RKISP1_CIF_ISP_BASE + 0x000001A8)
+#define RKISP1_CIF_ISP_OUT_H_OFFS_SHD (RKISP1_CIF_ISP_BASE + 0x000001AC)
+#define RKISP1_CIF_ISP_OUT_V_OFFS_SHD (RKISP1_CIF_ISP_BASE + 0x000001B0)
+#define RKISP1_CIF_ISP_OUT_H_SIZE_SHD (RKISP1_CIF_ISP_BASE + 0x000001B4)
+#define RKISP1_CIF_ISP_OUT_V_SIZE_SHD (RKISP1_CIF_ISP_BASE + 0x000001B8)
+#define RKISP1_CIF_ISP_IMSC (RKISP1_CIF_ISP_BASE + 0x000001BC)
+#define RKISP1_CIF_ISP_RIS (RKISP1_CIF_ISP_BASE + 0x000001C0)
+#define RKISP1_CIF_ISP_MIS (RKISP1_CIF_ISP_BASE + 0x000001C4)
+#define RKISP1_CIF_ISP_ICR (RKISP1_CIF_ISP_BASE + 0x000001C8)
+#define RKISP1_CIF_ISP_ISR (RKISP1_CIF_ISP_BASE + 0x000001CC)
+#define RKISP1_CIF_ISP_CT_COEFF_0 (RKISP1_CIF_ISP_BASE + 0x000001D0)
+#define RKISP1_CIF_ISP_CT_COEFF_1 (RKISP1_CIF_ISP_BASE + 0x000001D4)
+#define RKISP1_CIF_ISP_CT_COEFF_2 (RKISP1_CIF_ISP_BASE + 0x000001D8)
+#define RKISP1_CIF_ISP_CT_COEFF_3 (RKISP1_CIF_ISP_BASE + 0x000001DC)
+#define RKISP1_CIF_ISP_CT_COEFF_4 (RKISP1_CIF_ISP_BASE + 0x000001E0)
+#define RKISP1_CIF_ISP_CT_COEFF_5 (RKISP1_CIF_ISP_BASE + 0x000001E4)
+#define RKISP1_CIF_ISP_CT_COEFF_6 (RKISP1_CIF_ISP_BASE + 0x000001E8)
+#define RKISP1_CIF_ISP_CT_COEFF_7 (RKISP1_CIF_ISP_BASE + 0x000001EC)
+#define RKISP1_CIF_ISP_CT_COEFF_8 (RKISP1_CIF_ISP_BASE + 0x000001F0)
+#define RKISP1_CIF_ISP_GAMMA_OUT_MODE (RKISP1_CIF_ISP_BASE + 0x000001F4)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_0 (RKISP1_CIF_ISP_BASE + 0x000001F8)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_1 (RKISP1_CIF_ISP_BASE + 0x000001FC)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_2 (RKISP1_CIF_ISP_BASE + 0x00000200)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_3 (RKISP1_CIF_ISP_BASE + 0x00000204)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_4 (RKISP1_CIF_ISP_BASE + 0x00000208)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_5 (RKISP1_CIF_ISP_BASE + 0x0000020C)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_6 (RKISP1_CIF_ISP_BASE + 0x00000210)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_7 (RKISP1_CIF_ISP_BASE + 0x00000214)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_8 (RKISP1_CIF_ISP_BASE + 0x00000218)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_9 (RKISP1_CIF_ISP_BASE + 0x0000021C)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_10 (RKISP1_CIF_ISP_BASE + 0x00000220)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_11 (RKISP1_CIF_ISP_BASE + 0x00000224)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_12 (RKISP1_CIF_ISP_BASE + 0x00000228)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_13 (RKISP1_CIF_ISP_BASE + 0x0000022C)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_14 (RKISP1_CIF_ISP_BASE + 0x00000230)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_15 (RKISP1_CIF_ISP_BASE + 0x00000234)
+#define RKISP1_CIF_ISP_GAMMA_OUT_Y_16 (RKISP1_CIF_ISP_BASE + 0x00000238)
+#define RKISP1_CIF_ISP_ERR (RKISP1_CIF_ISP_BASE + 0x0000023C)
+#define RKISP1_CIF_ISP_ERR_CLR (RKISP1_CIF_ISP_BASE + 0x00000240)
+#define RKISP1_CIF_ISP_FRAME_COUNT (RKISP1_CIF_ISP_BASE + 0x00000244)
+#define RKISP1_CIF_ISP_CT_OFFSET_R (RKISP1_CIF_ISP_BASE + 0x00000248)
+#define RKISP1_CIF_ISP_CT_OFFSET_G (RKISP1_CIF_ISP_BASE + 0x0000024C)
+#define RKISP1_CIF_ISP_CT_OFFSET_B (RKISP1_CIF_ISP_BASE + 0x00000250)
+
+#define RKISP1_CIF_ISP_FLASH_BASE 0x00000660
+#define RKISP1_CIF_ISP_FLASH_CMD (RKISP1_CIF_ISP_FLASH_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_FLASH_CONFIG (RKISP1_CIF_ISP_FLASH_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_FLASH_PREDIV (RKISP1_CIF_ISP_FLASH_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_FLASH_DELAY (RKISP1_CIF_ISP_FLASH_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_FLASH_TIME (RKISP1_CIF_ISP_FLASH_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_FLASH_MAXP (RKISP1_CIF_ISP_FLASH_BASE + 0x00000014)
+
+#define RKISP1_CIF_ISP_SH_BASE 0x00000680
+#define RKISP1_CIF_ISP_SH_CTRL (RKISP1_CIF_ISP_SH_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_SH_PREDIV (RKISP1_CIF_ISP_SH_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_SH_DELAY (RKISP1_CIF_ISP_SH_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_SH_TIME (RKISP1_CIF_ISP_SH_BASE + 0x0000000C)
+
+#define RKISP1_CIF_C_PROC_BASE 0x00000800
+#define RKISP1_CIF_C_PROC_CTRL (RKISP1_CIF_C_PROC_BASE + 0x00000000)
+#define RKISP1_CIF_C_PROC_CONTRAST (RKISP1_CIF_C_PROC_BASE + 0x00000004)
+#define RKISP1_CIF_C_PROC_BRIGHTNESS (RKISP1_CIF_C_PROC_BASE + 0x00000008)
+#define RKISP1_CIF_C_PROC_SATURATION (RKISP1_CIF_C_PROC_BASE + 0x0000000C)
+#define RKISP1_CIF_C_PROC_HUE (RKISP1_CIF_C_PROC_BASE + 0x00000010)
+
+#define RKISP1_CIF_DUAL_CROP_BASE 0x00000880
+#define RKISP1_CIF_DUAL_CROP_CTRL (RKISP1_CIF_DUAL_CROP_BASE + 0x00000000)
+#define RKISP1_CIF_DUAL_CROP_M_H_OFFS (RKISP1_CIF_DUAL_CROP_BASE + 0x00000004)
+#define RKISP1_CIF_DUAL_CROP_M_V_OFFS (RKISP1_CIF_DUAL_CROP_BASE + 0x00000008)
+#define RKISP1_CIF_DUAL_CROP_M_H_SIZE (RKISP1_CIF_DUAL_CROP_BASE + 0x0000000C)
+#define RKISP1_CIF_DUAL_CROP_M_V_SIZE (RKISP1_CIF_DUAL_CROP_BASE + 0x00000010)
+#define RKISP1_CIF_DUAL_CROP_S_H_OFFS (RKISP1_CIF_DUAL_CROP_BASE + 0x00000014)
+#define RKISP1_CIF_DUAL_CROP_S_V_OFFS (RKISP1_CIF_DUAL_CROP_BASE + 0x00000018)
+#define RKISP1_CIF_DUAL_CROP_S_H_SIZE (RKISP1_CIF_DUAL_CROP_BASE + 0x0000001C)
+#define RKISP1_CIF_DUAL_CROP_S_V_SIZE (RKISP1_CIF_DUAL_CROP_BASE + 0x00000020)
+#define RKISP1_CIF_DUAL_CROP_M_H_OFFS_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x00000024)
+#define RKISP1_CIF_DUAL_CROP_M_V_OFFS_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x00000028)
+#define RKISP1_CIF_DUAL_CROP_M_H_SIZE_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x0000002C)
+#define RKISP1_CIF_DUAL_CROP_M_V_SIZE_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x00000030)
+#define RKISP1_CIF_DUAL_CROP_S_H_OFFS_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x00000034)
+#define RKISP1_CIF_DUAL_CROP_S_V_OFFS_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x00000038)
+#define RKISP1_CIF_DUAL_CROP_S_H_SIZE_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x0000003C)
+#define RKISP1_CIF_DUAL_CROP_S_V_SIZE_SHD (RKISP1_CIF_DUAL_CROP_BASE + 0x00000040)
+
+#define RKISP1_CIF_MRSZ_BASE 0x00000C00
+#define RKISP1_CIF_MRSZ_CTRL (RKISP1_CIF_MRSZ_BASE + 0x00000000)
+#define RKISP1_CIF_MRSZ_SCALE_HY (RKISP1_CIF_MRSZ_BASE + 0x00000004)
+#define RKISP1_CIF_MRSZ_SCALE_HCB (RKISP1_CIF_MRSZ_BASE + 0x00000008)
+#define RKISP1_CIF_MRSZ_SCALE_HCR (RKISP1_CIF_MRSZ_BASE + 0x0000000C)
+#define RKISP1_CIF_MRSZ_SCALE_VY (RKISP1_CIF_MRSZ_BASE + 0x00000010)
+#define RKISP1_CIF_MRSZ_SCALE_VC (RKISP1_CIF_MRSZ_BASE + 0x00000014)
+#define RKISP1_CIF_MRSZ_PHASE_HY (RKISP1_CIF_MRSZ_BASE + 0x00000018)
+#define RKISP1_CIF_MRSZ_PHASE_HC (RKISP1_CIF_MRSZ_BASE + 0x0000001C)
+#define RKISP1_CIF_MRSZ_PHASE_VY (RKISP1_CIF_MRSZ_BASE + 0x00000020)
+#define RKISP1_CIF_MRSZ_PHASE_VC (RKISP1_CIF_MRSZ_BASE + 0x00000024)
+#define RKISP1_CIF_MRSZ_SCALE_LUT_ADDR (RKISP1_CIF_MRSZ_BASE + 0x00000028)
+#define RKISP1_CIF_MRSZ_SCALE_LUT (RKISP1_CIF_MRSZ_BASE + 0x0000002C)
+#define RKISP1_CIF_MRSZ_CTRL_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000030)
+#define RKISP1_CIF_MRSZ_SCALE_HY_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000034)
+#define RKISP1_CIF_MRSZ_SCALE_HCB_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000038)
+#define RKISP1_CIF_MRSZ_SCALE_HCR_SHD (RKISP1_CIF_MRSZ_BASE + 0x0000003C)
+#define RKISP1_CIF_MRSZ_SCALE_VY_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000040)
+#define RKISP1_CIF_MRSZ_SCALE_VC_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000044)
+#define RKISP1_CIF_MRSZ_PHASE_HY_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000048)
+#define RKISP1_CIF_MRSZ_PHASE_HC_SHD (RKISP1_CIF_MRSZ_BASE + 0x0000004C)
+#define RKISP1_CIF_MRSZ_PHASE_VY_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000050)
+#define RKISP1_CIF_MRSZ_PHASE_VC_SHD (RKISP1_CIF_MRSZ_BASE + 0x00000054)
+
+#define RKISP1_CIF_SRSZ_BASE 0x00001000
+#define RKISP1_CIF_SRSZ_CTRL (RKISP1_CIF_SRSZ_BASE + 0x00000000)
+#define RKISP1_CIF_SRSZ_SCALE_HY (RKISP1_CIF_SRSZ_BASE + 0x00000004)
+#define RKISP1_CIF_SRSZ_SCALE_HCB (RKISP1_CIF_SRSZ_BASE + 0x00000008)
+#define RKISP1_CIF_SRSZ_SCALE_HCR (RKISP1_CIF_SRSZ_BASE + 0x0000000C)
+#define RKISP1_CIF_SRSZ_SCALE_VY (RKISP1_CIF_SRSZ_BASE + 0x00000010)
+#define RKISP1_CIF_SRSZ_SCALE_VC (RKISP1_CIF_SRSZ_BASE + 0x00000014)
+#define RKISP1_CIF_SRSZ_PHASE_HY (RKISP1_CIF_SRSZ_BASE + 0x00000018)
+#define RKISP1_CIF_SRSZ_PHASE_HC (RKISP1_CIF_SRSZ_BASE + 0x0000001C)
+#define RKISP1_CIF_SRSZ_PHASE_VY (RKISP1_CIF_SRSZ_BASE + 0x00000020)
+#define RKISP1_CIF_SRSZ_PHASE_VC (RKISP1_CIF_SRSZ_BASE + 0x00000024)
+#define RKISP1_CIF_SRSZ_SCALE_LUT_ADDR (RKISP1_CIF_SRSZ_BASE + 0x00000028)
+#define RKISP1_CIF_SRSZ_SCALE_LUT (RKISP1_CIF_SRSZ_BASE + 0x0000002C)
+#define RKISP1_CIF_SRSZ_CTRL_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000030)
+#define RKISP1_CIF_SRSZ_SCALE_HY_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000034)
+#define RKISP1_CIF_SRSZ_SCALE_HCB_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000038)
+#define RKISP1_CIF_SRSZ_SCALE_HCR_SHD (RKISP1_CIF_SRSZ_BASE + 0x0000003C)
+#define RKISP1_CIF_SRSZ_SCALE_VY_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000040)
+#define RKISP1_CIF_SRSZ_SCALE_VC_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000044)
+#define RKISP1_CIF_SRSZ_PHASE_HY_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000048)
+#define RKISP1_CIF_SRSZ_PHASE_HC_SHD (RKISP1_CIF_SRSZ_BASE + 0x0000004C)
+#define RKISP1_CIF_SRSZ_PHASE_VY_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000050)
+#define RKISP1_CIF_SRSZ_PHASE_VC_SHD (RKISP1_CIF_SRSZ_BASE + 0x00000054)
+
+#define RKISP1_CIF_MI_BASE 0x00001400
+#define RKISP1_CIF_MI_CTRL (RKISP1_CIF_MI_BASE + 0x00000000)
+#define RKISP1_CIF_MI_INIT (RKISP1_CIF_MI_BASE + 0x00000004)
+#define RKISP1_CIF_MI_MP_Y_BASE_AD_INIT (RKISP1_CIF_MI_BASE + 0x00000008)
+#define RKISP1_CIF_MI_MP_Y_SIZE_INIT (RKISP1_CIF_MI_BASE + 0x0000000C)
+#define RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT (RKISP1_CIF_MI_BASE + 0x00000010)
+#define RKISP1_CIF_MI_MP_Y_OFFS_CNT_START (RKISP1_CIF_MI_BASE + 0x00000014)
+#define RKISP1_CIF_MI_MP_Y_IRQ_OFFS_INIT (RKISP1_CIF_MI_BASE + 0x00000018)
+#define RKISP1_CIF_MI_MP_CB_BASE_AD_INIT (RKISP1_CIF_MI_BASE + 0x0000001C)
+#define RKISP1_CIF_MI_MP_CB_SIZE_INIT (RKISP1_CIF_MI_BASE + 0x00000020)
+#define RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT (RKISP1_CIF_MI_BASE + 0x00000024)
+#define RKISP1_CIF_MI_MP_CB_OFFS_CNT_START (RKISP1_CIF_MI_BASE + 0x00000028)
+#define RKISP1_CIF_MI_MP_CR_BASE_AD_INIT (RKISP1_CIF_MI_BASE + 0x0000002C)
+#define RKISP1_CIF_MI_MP_CR_SIZE_INIT (RKISP1_CIF_MI_BASE + 0x00000030)
+#define RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT (RKISP1_CIF_MI_BASE + 0x00000034)
+#define RKISP1_CIF_MI_MP_CR_OFFS_CNT_START (RKISP1_CIF_MI_BASE + 0x00000038)
+#define RKISP1_CIF_MI_SP_Y_BASE_AD_INIT (RKISP1_CIF_MI_BASE + 0x0000003C)
+#define RKISP1_CIF_MI_SP_Y_SIZE_INIT (RKISP1_CIF_MI_BASE + 0x00000040)
+#define RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT (RKISP1_CIF_MI_BASE + 0x00000044)
+#define RKISP1_CIF_MI_SP_Y_OFFS_CNT_START (RKISP1_CIF_MI_BASE + 0x00000048)
+#define RKISP1_CIF_MI_SP_Y_LLENGTH (RKISP1_CIF_MI_BASE + 0x0000004C)
+#define RKISP1_CIF_MI_SP_CB_BASE_AD_INIT (RKISP1_CIF_MI_BASE + 0x00000050)
+#define RKISP1_CIF_MI_SP_CB_SIZE_INIT (RKISP1_CIF_MI_BASE + 0x00000054)
+#define RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT (RKISP1_CIF_MI_BASE + 0x00000058)
+#define RKISP1_CIF_MI_SP_CB_OFFS_CNT_START (RKISP1_CIF_MI_BASE + 0x0000005C)
+#define RKISP1_CIF_MI_SP_CR_BASE_AD_INIT (RKISP1_CIF_MI_BASE + 0x00000060)
+#define RKISP1_CIF_MI_SP_CR_SIZE_INIT (RKISP1_CIF_MI_BASE + 0x00000064)
+#define RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT (RKISP1_CIF_MI_BASE + 0x00000068)
+#define RKISP1_CIF_MI_SP_CR_OFFS_CNT_START (RKISP1_CIF_MI_BASE + 0x0000006C)
+#define RKISP1_CIF_MI_BYTE_CNT (RKISP1_CIF_MI_BASE + 0x00000070)
+#define RKISP1_CIF_MI_CTRL_SHD (RKISP1_CIF_MI_BASE + 0x00000074)
+#define RKISP1_CIF_MI_MP_Y_BASE_AD_SHD (RKISP1_CIF_MI_BASE + 0x00000078)
+#define RKISP1_CIF_MI_MP_Y_SIZE_SHD (RKISP1_CIF_MI_BASE + 0x0000007C)
+#define RKISP1_CIF_MI_MP_Y_OFFS_CNT_SHD (RKISP1_CIF_MI_BASE + 0x00000080)
+#define RKISP1_CIF_MI_MP_Y_IRQ_OFFS_SHD (RKISP1_CIF_MI_BASE + 0x00000084)
+#define RKISP1_CIF_MI_MP_CB_BASE_AD_SHD (RKISP1_CIF_MI_BASE + 0x00000088)
+#define RKISP1_CIF_MI_MP_CB_SIZE_SHD (RKISP1_CIF_MI_BASE + 0x0000008C)
+#define RKISP1_CIF_MI_MP_CB_OFFS_CNT_SHD (RKISP1_CIF_MI_BASE + 0x00000090)
+#define RKISP1_CIF_MI_MP_CR_BASE_AD_SHD (RKISP1_CIF_MI_BASE + 0x00000094)
+#define RKISP1_CIF_MI_MP_CR_SIZE_SHD (RKISP1_CIF_MI_BASE + 0x00000098)
+#define RKISP1_CIF_MI_MP_CR_OFFS_CNT_SHD (RKISP1_CIF_MI_BASE + 0x0000009C)
+#define RKISP1_CIF_MI_SP_Y_BASE_AD_SHD (RKISP1_CIF_MI_BASE + 0x000000A0)
+#define RKISP1_CIF_MI_SP_Y_SIZE_SHD (RKISP1_CIF_MI_BASE + 0x000000A4)
+#define RKISP1_CIF_MI_SP_Y_OFFS_CNT_SHD (RKISP1_CIF_MI_BASE + 0x000000A8)
+#define RKISP1_CIF_MI_SP_CB_BASE_AD_SHD (RKISP1_CIF_MI_BASE + 0x000000B0)
+#define RKISP1_CIF_MI_SP_CB_SIZE_SHD (RKISP1_CIF_MI_BASE + 0x000000B4)
+#define RKISP1_CIF_MI_SP_CB_OFFS_CNT_SHD (RKISP1_CIF_MI_BASE + 0x000000B8)
+#define RKISP1_CIF_MI_SP_CR_BASE_AD_SHD (RKISP1_CIF_MI_BASE + 0x000000BC)
+#define RKISP1_CIF_MI_SP_CR_SIZE_SHD (RKISP1_CIF_MI_BASE + 0x000000C0)
+#define RKISP1_CIF_MI_SP_CR_OFFS_CNT_SHD (RKISP1_CIF_MI_BASE + 0x000000C4)
+#define RKISP1_CIF_MI_DMA_Y_PIC_START_AD (RKISP1_CIF_MI_BASE + 0x000000C8)
+#define RKISP1_CIF_MI_DMA_Y_PIC_WIDTH (RKISP1_CIF_MI_BASE + 0x000000CC)
+#define RKISP1_CIF_MI_DMA_Y_LLENGTH (RKISP1_CIF_MI_BASE + 0x000000D0)
+#define RKISP1_CIF_MI_DMA_Y_PIC_SIZE (RKISP1_CIF_MI_BASE + 0x000000D4)
+#define RKISP1_CIF_MI_DMA_CB_PIC_START_AD (RKISP1_CIF_MI_BASE + 0x000000D8)
+#define RKISP1_CIF_MI_DMA_CR_PIC_START_AD (RKISP1_CIF_MI_BASE + 0x000000E8)
+#define RKISP1_CIF_MI_IMSC (RKISP1_CIF_MI_BASE + 0x000000F8)
+#define RKISP1_CIF_MI_RIS (RKISP1_CIF_MI_BASE + 0x000000FC)
+#define RKISP1_CIF_MI_MIS (RKISP1_CIF_MI_BASE + 0x00000100)
+#define RKISP1_CIF_MI_ICR (RKISP1_CIF_MI_BASE + 0x00000104)
+#define RKISP1_CIF_MI_ISR (RKISP1_CIF_MI_BASE + 0x00000108)
+#define RKISP1_CIF_MI_STATUS (RKISP1_CIF_MI_BASE + 0x0000010C)
+#define RKISP1_CIF_MI_STATUS_CLR (RKISP1_CIF_MI_BASE + 0x00000110)
+#define RKISP1_CIF_MI_SP_Y_PIC_WIDTH (RKISP1_CIF_MI_BASE + 0x00000114)
+#define RKISP1_CIF_MI_SP_Y_PIC_HEIGHT (RKISP1_CIF_MI_BASE + 0x00000118)
+#define RKISP1_CIF_MI_SP_Y_PIC_SIZE (RKISP1_CIF_MI_BASE + 0x0000011C)
+#define RKISP1_CIF_MI_DMA_CTRL (RKISP1_CIF_MI_BASE + 0x00000120)
+#define RKISP1_CIF_MI_DMA_START (RKISP1_CIF_MI_BASE + 0x00000124)
+#define RKISP1_CIF_MI_DMA_STATUS (RKISP1_CIF_MI_BASE + 0x00000128)
+#define RKISP1_CIF_MI_PIXEL_COUNT (RKISP1_CIF_MI_BASE + 0x0000012C)
+#define RKISP1_CIF_MI_MP_Y_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000130)
+#define RKISP1_CIF_MI_MP_CB_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000134)
+#define RKISP1_CIF_MI_MP_CR_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000138)
+#define RKISP1_CIF_MI_SP_Y_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x0000013C)
+#define RKISP1_CIF_MI_SP_CB_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000140)
+#define RKISP1_CIF_MI_SP_CR_BASE_AD_INIT2 (RKISP1_CIF_MI_BASE + 0x00000144)
+#define RKISP1_CIF_MI_XTD_FORMAT_CTRL (RKISP1_CIF_MI_BASE + 0x00000148)
+
+#define RKISP1_CIF_SMIA_BASE 0x00001A00
+#define RKISP1_CIF_SMIA_CTRL (RKISP1_CIF_SMIA_BASE + 0x00000000)
+#define RKISP1_CIF_SMIA_STATUS (RKISP1_CIF_SMIA_BASE + 0x00000004)
+#define RKISP1_CIF_SMIA_IMSC (RKISP1_CIF_SMIA_BASE + 0x00000008)
+#define RKISP1_CIF_SMIA_RIS (RKISP1_CIF_SMIA_BASE + 0x0000000C)
+#define RKISP1_CIF_SMIA_MIS (RKISP1_CIF_SMIA_BASE + 0x00000010)
+#define RKISP1_CIF_SMIA_ICR (RKISP1_CIF_SMIA_BASE + 0x00000014)
+#define RKISP1_CIF_SMIA_ISR (RKISP1_CIF_SMIA_BASE + 0x00000018)
+#define RKISP1_CIF_SMIA_DATA_FORMAT_SEL (RKISP1_CIF_SMIA_BASE + 0x0000001C)
+#define RKISP1_CIF_SMIA_SOF_EMB_DATA_LINES (RKISP1_CIF_SMIA_BASE + 0x00000020)
+#define RKISP1_CIF_SMIA_EMB_HSTART (RKISP1_CIF_SMIA_BASE + 0x00000024)
+#define RKISP1_CIF_SMIA_EMB_HSIZE (RKISP1_CIF_SMIA_BASE + 0x00000028)
+#define RKISP1_CIF_SMIA_EMB_VSTART (RKISP1_CIF_SMIA_BASE + 0x0000002c)
+#define RKISP1_CIF_SMIA_NUM_LINES (RKISP1_CIF_SMIA_BASE + 0x00000030)
+#define RKISP1_CIF_SMIA_EMB_DATA_FIFO (RKISP1_CIF_SMIA_BASE + 0x00000034)
+#define RKISP1_CIF_SMIA_EMB_DATA_WATERMARK (RKISP1_CIF_SMIA_BASE + 0x00000038)
+
+#define RKISP1_CIF_MIPI_BASE 0x00001C00
+#define RKISP1_CIF_MIPI_CTRL (RKISP1_CIF_MIPI_BASE + 0x00000000)
+#define RKISP1_CIF_MIPI_STATUS (RKISP1_CIF_MIPI_BASE + 0x00000004)
+#define RKISP1_CIF_MIPI_IMSC (RKISP1_CIF_MIPI_BASE + 0x00000008)
+#define RKISP1_CIF_MIPI_RIS (RKISP1_CIF_MIPI_BASE + 0x0000000C)
+#define RKISP1_CIF_MIPI_MIS (RKISP1_CIF_MIPI_BASE + 0x00000010)
+#define RKISP1_CIF_MIPI_ICR (RKISP1_CIF_MIPI_BASE + 0x00000014)
+#define RKISP1_CIF_MIPI_ISR (RKISP1_CIF_MIPI_BASE + 0x00000018)
+#define RKISP1_CIF_MIPI_CUR_DATA_ID (RKISP1_CIF_MIPI_BASE + 0x0000001C)
+#define RKISP1_CIF_MIPI_IMG_DATA_SEL (RKISP1_CIF_MIPI_BASE + 0x00000020)
+#define RKISP1_CIF_MIPI_ADD_DATA_SEL_1 (RKISP1_CIF_MIPI_BASE + 0x00000024)
+#define RKISP1_CIF_MIPI_ADD_DATA_SEL_2 (RKISP1_CIF_MIPI_BASE + 0x00000028)
+#define RKISP1_CIF_MIPI_ADD_DATA_SEL_3 (RKISP1_CIF_MIPI_BASE + 0x0000002C)
+#define RKISP1_CIF_MIPI_ADD_DATA_SEL_4 (RKISP1_CIF_MIPI_BASE + 0x00000030)
+#define RKISP1_CIF_MIPI_ADD_DATA_FIFO (RKISP1_CIF_MIPI_BASE + 0x00000034)
+#define RKISP1_CIF_MIPI_FIFO_FILL_LEVEL (RKISP1_CIF_MIPI_BASE + 0x00000038)
+#define RKISP1_CIF_MIPI_COMPRESSED_MODE (RKISP1_CIF_MIPI_BASE + 0x0000003C)
+#define RKISP1_CIF_MIPI_FRAME (RKISP1_CIF_MIPI_BASE + 0x00000040)
+#define RKISP1_CIF_MIPI_GEN_SHORT_DT (RKISP1_CIF_MIPI_BASE + 0x00000044)
+#define RKISP1_CIF_MIPI_GEN_SHORT_8_9 (RKISP1_CIF_MIPI_BASE + 0x00000048)
+#define RKISP1_CIF_MIPI_GEN_SHORT_A_B (RKISP1_CIF_MIPI_BASE + 0x0000004C)
+#define RKISP1_CIF_MIPI_GEN_SHORT_C_D (RKISP1_CIF_MIPI_BASE + 0x00000050)
+#define RKISP1_CIF_MIPI_GEN_SHORT_E_F (RKISP1_CIF_MIPI_BASE + 0x00000054)
+
+#define RKISP1_CIF_ISP_AFM_BASE 0x00002000
+#define RKISP1_CIF_ISP_AFM_CTRL (RKISP1_CIF_ISP_AFM_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_AFM_LT_A (RKISP1_CIF_ISP_AFM_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_AFM_RB_A (RKISP1_CIF_ISP_AFM_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_AFM_LT_B (RKISP1_CIF_ISP_AFM_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_AFM_RB_B (RKISP1_CIF_ISP_AFM_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_AFM_LT_C (RKISP1_CIF_ISP_AFM_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_AFM_RB_C (RKISP1_CIF_ISP_AFM_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_AFM_THRES (RKISP1_CIF_ISP_AFM_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_AFM_VAR_SHIFT (RKISP1_CIF_ISP_AFM_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_AFM_SUM_A (RKISP1_CIF_ISP_AFM_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_AFM_SUM_B (RKISP1_CIF_ISP_AFM_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_AFM_SUM_C (RKISP1_CIF_ISP_AFM_BASE + 0x0000002C)
+#define RKISP1_CIF_ISP_AFM_LUM_A (RKISP1_CIF_ISP_AFM_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_AFM_LUM_B (RKISP1_CIF_ISP_AFM_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_AFM_LUM_C (RKISP1_CIF_ISP_AFM_BASE + 0x00000038)
+
+#define RKISP1_CIF_ISP_LSC_BASE 0x00002200
+#define RKISP1_CIF_ISP_LSC_CTRL (RKISP1_CIF_ISP_LSC_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_LSC_R_TABLE_ADDR (RKISP1_CIF_ISP_LSC_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_LSC_GR_TABLE_ADDR (RKISP1_CIF_ISP_LSC_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_LSC_B_TABLE_ADDR (RKISP1_CIF_ISP_LSC_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_LSC_GB_TABLE_ADDR (RKISP1_CIF_ISP_LSC_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_LSC_R_TABLE_DATA (RKISP1_CIF_ISP_LSC_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_LSC_GR_TABLE_DATA (RKISP1_CIF_ISP_LSC_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_LSC_B_TABLE_DATA (RKISP1_CIF_ISP_LSC_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_LSC_GB_TABLE_DATA (RKISP1_CIF_ISP_LSC_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_LSC_XGRAD_01 (RKISP1_CIF_ISP_LSC_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_LSC_XGRAD_23 (RKISP1_CIF_ISP_LSC_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_LSC_XGRAD_45 (RKISP1_CIF_ISP_LSC_BASE + 0x0000002C)
+#define RKISP1_CIF_ISP_LSC_XGRAD_67 (RKISP1_CIF_ISP_LSC_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_LSC_YGRAD_01 (RKISP1_CIF_ISP_LSC_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_LSC_YGRAD_23 (RKISP1_CIF_ISP_LSC_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_LSC_YGRAD_45 (RKISP1_CIF_ISP_LSC_BASE + 0x0000003C)
+#define RKISP1_CIF_ISP_LSC_YGRAD_67 (RKISP1_CIF_ISP_LSC_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_LSC_XSIZE_01 (RKISP1_CIF_ISP_LSC_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_LSC_XSIZE_23 (RKISP1_CIF_ISP_LSC_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_LSC_XSIZE_45 (RKISP1_CIF_ISP_LSC_BASE + 0x0000004C)
+#define RKISP1_CIF_ISP_LSC_XSIZE_67 (RKISP1_CIF_ISP_LSC_BASE + 0x00000050)
+#define RKISP1_CIF_ISP_LSC_YSIZE_01 (RKISP1_CIF_ISP_LSC_BASE + 0x00000054)
+#define RKISP1_CIF_ISP_LSC_YSIZE_23 (RKISP1_CIF_ISP_LSC_BASE + 0x00000058)
+#define RKISP1_CIF_ISP_LSC_YSIZE_45 (RKISP1_CIF_ISP_LSC_BASE + 0x0000005C)
+#define RKISP1_CIF_ISP_LSC_YSIZE_67 (RKISP1_CIF_ISP_LSC_BASE + 0x00000060)
+#define RKISP1_CIF_ISP_LSC_TABLE_SEL (RKISP1_CIF_ISP_LSC_BASE + 0x00000064)
+#define RKISP1_CIF_ISP_LSC_STATUS (RKISP1_CIF_ISP_LSC_BASE + 0x00000068)
+
+#define RKISP1_CIF_ISP_IS_BASE 0x00002300
+#define RKISP1_CIF_ISP_IS_CTRL (RKISP1_CIF_ISP_IS_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_IS_RECENTER (RKISP1_CIF_ISP_IS_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_IS_H_OFFS (RKISP1_CIF_ISP_IS_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_IS_V_OFFS (RKISP1_CIF_ISP_IS_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_IS_H_SIZE (RKISP1_CIF_ISP_IS_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_IS_V_SIZE (RKISP1_CIF_ISP_IS_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_IS_MAX_DX (RKISP1_CIF_ISP_IS_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_IS_MAX_DY (RKISP1_CIF_ISP_IS_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_IS_DISPLACE (RKISP1_CIF_ISP_IS_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_IS_H_OFFS_SHD (RKISP1_CIF_ISP_IS_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_IS_V_OFFS_SHD (RKISP1_CIF_ISP_IS_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_IS_H_SIZE_SHD (RKISP1_CIF_ISP_IS_BASE + 0x0000002C)
+#define RKISP1_CIF_ISP_IS_V_SIZE_SHD (RKISP1_CIF_ISP_IS_BASE + 0x00000030)
+
+#define RKISP1_CIF_ISP_HIST_BASE 0x00002400
+
+#define RKISP1_CIF_ISP_HIST_PROP (RKISP1_CIF_ISP_HIST_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_HIST_H_OFFS (RKISP1_CIF_ISP_HIST_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_HIST_V_OFFS (RKISP1_CIF_ISP_HIST_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_HIST_H_SIZE (RKISP1_CIF_ISP_HIST_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_HIST_V_SIZE (RKISP1_CIF_ISP_HIST_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_HIST_BIN_0 (RKISP1_CIF_ISP_HIST_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_HIST_BIN_1 (RKISP1_CIF_ISP_HIST_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_HIST_BIN_2 (RKISP1_CIF_ISP_HIST_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_HIST_BIN_3 (RKISP1_CIF_ISP_HIST_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_HIST_BIN_4 (RKISP1_CIF_ISP_HIST_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_HIST_BIN_5 (RKISP1_CIF_ISP_HIST_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_HIST_BIN_6 (RKISP1_CIF_ISP_HIST_BASE + 0x0000002C)
+#define RKISP1_CIF_ISP_HIST_BIN_7 (RKISP1_CIF_ISP_HIST_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_HIST_BIN_8 (RKISP1_CIF_ISP_HIST_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_HIST_BIN_9 (RKISP1_CIF_ISP_HIST_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_HIST_BIN_10 (RKISP1_CIF_ISP_HIST_BASE + 0x0000003C)
+#define RKISP1_CIF_ISP_HIST_BIN_11 (RKISP1_CIF_ISP_HIST_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_HIST_BIN_12 (RKISP1_CIF_ISP_HIST_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_HIST_BIN_13 (RKISP1_CIF_ISP_HIST_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_HIST_BIN_14 (RKISP1_CIF_ISP_HIST_BASE + 0x0000004C)
+#define RKISP1_CIF_ISP_HIST_BIN_15 (RKISP1_CIF_ISP_HIST_BASE + 0x00000050)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_00TO30 (RKISP1_CIF_ISP_HIST_BASE + 0x00000054)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_40TO21 (RKISP1_CIF_ISP_HIST_BASE + 0x00000058)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_31TO12 (RKISP1_CIF_ISP_HIST_BASE + 0x0000005C)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_22TO03 (RKISP1_CIF_ISP_HIST_BASE + 0x00000060)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_13TO43 (RKISP1_CIF_ISP_HIST_BASE + 0x00000064)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_04TO34 (RKISP1_CIF_ISP_HIST_BASE + 0x00000068)
+#define RKISP1_CIF_ISP_HIST_WEIGHT_44 (RKISP1_CIF_ISP_HIST_BASE + 0x0000006C)
+
+#define RKISP1_CIF_ISP_FILT_BASE 0x00002500
+#define RKISP1_CIF_ISP_FILT_MODE (RKISP1_CIF_ISP_FILT_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_FILT_THRESH_BL0 (RKISP1_CIF_ISP_FILT_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_FILT_THRESH_BL1 (RKISP1_CIF_ISP_FILT_BASE + 0x0000002c)
+#define RKISP1_CIF_ISP_FILT_THRESH_SH0 (RKISP1_CIF_ISP_FILT_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_FILT_THRESH_SH1 (RKISP1_CIF_ISP_FILT_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_FILT_LUM_WEIGHT (RKISP1_CIF_ISP_FILT_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_FILT_FAC_SH1 (RKISP1_CIF_ISP_FILT_BASE + 0x0000003c)
+#define RKISP1_CIF_ISP_FILT_FAC_SH0 (RKISP1_CIF_ISP_FILT_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_FILT_FAC_MID (RKISP1_CIF_ISP_FILT_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_FILT_FAC_BL0 (RKISP1_CIF_ISP_FILT_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_FILT_FAC_BL1 (RKISP1_CIF_ISP_FILT_BASE + 0x0000004C)
+
+#define RKISP1_CIF_ISP_CAC_BASE 0x00002580
+#define RKISP1_CIF_ISP_CAC_CTRL (RKISP1_CIF_ISP_CAC_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_CAC_COUNT_START (RKISP1_CIF_ISP_CAC_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_CAC_A (RKISP1_CIF_ISP_CAC_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_CAC_B (RKISP1_CIF_ISP_CAC_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_CAC_C (RKISP1_CIF_ISP_CAC_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_X_NORM (RKISP1_CIF_ISP_CAC_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_Y_NORM (RKISP1_CIF_ISP_CAC_BASE + 0x00000018)
+
+#define RKISP1_CIF_ISP_EXP_BASE 0x00002600
+#define RKISP1_CIF_ISP_EXP_CTRL (RKISP1_CIF_ISP_EXP_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_EXP_H_OFFSET (RKISP1_CIF_ISP_EXP_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_EXP_V_OFFSET (RKISP1_CIF_ISP_EXP_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_EXP_H_SIZE (RKISP1_CIF_ISP_EXP_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_EXP_V_SIZE (RKISP1_CIF_ISP_EXP_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_EXP_MEAN_00 (RKISP1_CIF_ISP_EXP_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_EXP_MEAN_10 (RKISP1_CIF_ISP_EXP_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_EXP_MEAN_20 (RKISP1_CIF_ISP_EXP_BASE + 0x0000001c)
+#define RKISP1_CIF_ISP_EXP_MEAN_30 (RKISP1_CIF_ISP_EXP_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_EXP_MEAN_40 (RKISP1_CIF_ISP_EXP_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_EXP_MEAN_01 (RKISP1_CIF_ISP_EXP_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_EXP_MEAN_11 (RKISP1_CIF_ISP_EXP_BASE + 0x0000002c)
+#define RKISP1_CIF_ISP_EXP_MEAN_21 (RKISP1_CIF_ISP_EXP_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_EXP_MEAN_31 (RKISP1_CIF_ISP_EXP_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_EXP_MEAN_41 (RKISP1_CIF_ISP_EXP_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_EXP_MEAN_02 (RKISP1_CIF_ISP_EXP_BASE + 0x0000003c)
+#define RKISP1_CIF_ISP_EXP_MEAN_12 (RKISP1_CIF_ISP_EXP_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_EXP_MEAN_22 (RKISP1_CIF_ISP_EXP_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_EXP_MEAN_32 (RKISP1_CIF_ISP_EXP_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_EXP_MEAN_42 (RKISP1_CIF_ISP_EXP_BASE + 0x0000004c)
+#define RKISP1_CIF_ISP_EXP_MEAN_03 (RKISP1_CIF_ISP_EXP_BASE + 0x00000050)
+#define RKISP1_CIF_ISP_EXP_MEAN_13 (RKISP1_CIF_ISP_EXP_BASE + 0x00000054)
+#define RKISP1_CIF_ISP_EXP_MEAN_23 (RKISP1_CIF_ISP_EXP_BASE + 0x00000058)
+#define RKISP1_CIF_ISP_EXP_MEAN_33 (RKISP1_CIF_ISP_EXP_BASE + 0x0000005c)
+#define RKISP1_CIF_ISP_EXP_MEAN_43 (RKISP1_CIF_ISP_EXP_BASE + 0x00000060)
+#define RKISP1_CIF_ISP_EXP_MEAN_04 (RKISP1_CIF_ISP_EXP_BASE + 0x00000064)
+#define RKISP1_CIF_ISP_EXP_MEAN_14 (RKISP1_CIF_ISP_EXP_BASE + 0x00000068)
+#define RKISP1_CIF_ISP_EXP_MEAN_24 (RKISP1_CIF_ISP_EXP_BASE + 0x0000006c)
+#define RKISP1_CIF_ISP_EXP_MEAN_34 (RKISP1_CIF_ISP_EXP_BASE + 0x00000070)
+#define RKISP1_CIF_ISP_EXP_MEAN_44 (RKISP1_CIF_ISP_EXP_BASE + 0x00000074)
+
+#define RKISP1_CIF_ISP_BLS_BASE 0x00002700
+#define RKISP1_CIF_ISP_BLS_CTRL (RKISP1_CIF_ISP_BLS_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_BLS_SAMPLES (RKISP1_CIF_ISP_BLS_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_BLS_H1_START (RKISP1_CIF_ISP_BLS_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_BLS_H1_STOP (RKISP1_CIF_ISP_BLS_BASE + 0x0000000c)
+#define RKISP1_CIF_ISP_BLS_V1_START (RKISP1_CIF_ISP_BLS_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_BLS_V1_STOP (RKISP1_CIF_ISP_BLS_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_BLS_H2_START (RKISP1_CIF_ISP_BLS_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_BLS_H2_STOP (RKISP1_CIF_ISP_BLS_BASE + 0x0000001c)
+#define RKISP1_CIF_ISP_BLS_V2_START (RKISP1_CIF_ISP_BLS_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_BLS_V2_STOP (RKISP1_CIF_ISP_BLS_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_BLS_A_FIXED (RKISP1_CIF_ISP_BLS_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_BLS_B_FIXED (RKISP1_CIF_ISP_BLS_BASE + 0x0000002c)
+#define RKISP1_CIF_ISP_BLS_C_FIXED (RKISP1_CIF_ISP_BLS_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_BLS_D_FIXED (RKISP1_CIF_ISP_BLS_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_BLS_A_MEASURED (RKISP1_CIF_ISP_BLS_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_BLS_B_MEASURED (RKISP1_CIF_ISP_BLS_BASE + 0x0000003c)
+#define RKISP1_CIF_ISP_BLS_C_MEASURED (RKISP1_CIF_ISP_BLS_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_BLS_D_MEASURED (RKISP1_CIF_ISP_BLS_BASE + 0x00000044)
+
+#define RKISP1_CIF_ISP_DPF_BASE 0x00002800
+#define RKISP1_CIF_ISP_DPF_MODE (RKISP1_CIF_ISP_DPF_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_DPF_STRENGTH_R (RKISP1_CIF_ISP_DPF_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_DPF_STRENGTH_G (RKISP1_CIF_ISP_DPF_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_DPF_STRENGTH_B (RKISP1_CIF_ISP_DPF_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_DPF_S_WEIGHT_G_1_4 (RKISP1_CIF_ISP_DPF_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_DPF_S_WEIGHT_G_5_6 (RKISP1_CIF_ISP_DPF_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_DPF_S_WEIGHT_RB_1_4 (RKISP1_CIF_ISP_DPF_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_DPF_S_WEIGHT_RB_5_6 (RKISP1_CIF_ISP_DPF_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_0 (RKISP1_CIF_ISP_DPF_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_1 (RKISP1_CIF_ISP_DPF_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_2 (RKISP1_CIF_ISP_DPF_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_3 (RKISP1_CIF_ISP_DPF_BASE + 0x0000002C)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_4 (RKISP1_CIF_ISP_DPF_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_5 (RKISP1_CIF_ISP_DPF_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_6 (RKISP1_CIF_ISP_DPF_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_7 (RKISP1_CIF_ISP_DPF_BASE + 0x0000003C)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_8 (RKISP1_CIF_ISP_DPF_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_9 (RKISP1_CIF_ISP_DPF_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_10 (RKISP1_CIF_ISP_DPF_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_11 (RKISP1_CIF_ISP_DPF_BASE + 0x0000004C)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_12 (RKISP1_CIF_ISP_DPF_BASE + 0x00000050)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_13 (RKISP1_CIF_ISP_DPF_BASE + 0x00000054)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_14 (RKISP1_CIF_ISP_DPF_BASE + 0x00000058)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_15 (RKISP1_CIF_ISP_DPF_BASE + 0x0000005C)
+#define RKISP1_CIF_ISP_DPF_NULL_COEFF_16 (RKISP1_CIF_ISP_DPF_BASE + 0x00000060)
+#define RKISP1_CIF_ISP_DPF_NF_GAIN_R (RKISP1_CIF_ISP_DPF_BASE + 0x00000064)
+#define RKISP1_CIF_ISP_DPF_NF_GAIN_GR (RKISP1_CIF_ISP_DPF_BASE + 0x00000068)
+#define RKISP1_CIF_ISP_DPF_NF_GAIN_GB (RKISP1_CIF_ISP_DPF_BASE + 0x0000006C)
+#define RKISP1_CIF_ISP_DPF_NF_GAIN_B (RKISP1_CIF_ISP_DPF_BASE + 0x00000070)
+
+#define RKISP1_CIF_ISP_DPCC_BASE 0x00002900
+#define RKISP1_CIF_ISP_DPCC_MODE (RKISP1_CIF_ISP_DPCC_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE (RKISP1_CIF_ISP_DPCC_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_DPCC_SET_USE (RKISP1_CIF_ISP_DPCC_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_1 (RKISP1_CIF_ISP_DPCC_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_2 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_DPCC_METHODS_SET_3 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_1 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_1 (RKISP1_CIF_ISP_DPCC_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_DPCC_PG_FAC_1 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_DPCC_RND_THRESH_1 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_DPCC_RG_FAC_1 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_2 (RKISP1_CIF_ISP_DPCC_BASE + 0x0000002C)
+#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_2 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_DPCC_PG_FAC_2 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_DPCC_RND_THRESH_2 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_DPCC_RG_FAC_2 (RKISP1_CIF_ISP_DPCC_BASE + 0x0000003C)
+#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_3 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_3 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_DPCC_PG_FAC_3 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_DPCC_RND_THRESH_3 (RKISP1_CIF_ISP_DPCC_BASE + 0x0000004C)
+#define RKISP1_CIF_ISP_DPCC_RG_FAC_3 (RKISP1_CIF_ISP_DPCC_BASE + 0x00000050)
+#define RKISP1_CIF_ISP_DPCC_RO_LIMITS (RKISP1_CIF_ISP_DPCC_BASE + 0x00000054)
+#define RKISP1_CIF_ISP_DPCC_RND_OFFS (RKISP1_CIF_ISP_DPCC_BASE + 0x00000058)
+#define RKISP1_CIF_ISP_DPCC_BPT_CTRL (RKISP1_CIF_ISP_DPCC_BASE + 0x0000005C)
+#define RKISP1_CIF_ISP_DPCC_BPT_NUMBER (RKISP1_CIF_ISP_DPCC_BASE + 0x00000060)
+#define RKISP1_CIF_ISP_DPCC_BPT_ADDR (RKISP1_CIF_ISP_DPCC_BASE + 0x00000064)
+#define RKISP1_CIF_ISP_DPCC_BPT_DATA (RKISP1_CIF_ISP_DPCC_BASE + 0x00000068)
+
+#define RKISP1_CIF_ISP_WDR_BASE 0x00002A00
+#define RKISP1_CIF_ISP_WDR_CTRL (RKISP1_CIF_ISP_WDR_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_1 (RKISP1_CIF_ISP_WDR_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_2 (RKISP1_CIF_ISP_WDR_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_3 (RKISP1_CIF_ISP_WDR_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_4 (RKISP1_CIF_ISP_WDR_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_0 (RKISP1_CIF_ISP_WDR_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_1 (RKISP1_CIF_ISP_WDR_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_2 (RKISP1_CIF_ISP_WDR_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_3 (RKISP1_CIF_ISP_WDR_BASE + 0x00000020)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_4 (RKISP1_CIF_ISP_WDR_BASE + 0x00000024)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_5 (RKISP1_CIF_ISP_WDR_BASE + 0x00000028)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_6 (RKISP1_CIF_ISP_WDR_BASE + 0x0000002C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_7 (RKISP1_CIF_ISP_WDR_BASE + 0x00000030)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_8 (RKISP1_CIF_ISP_WDR_BASE + 0x00000034)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_9 (RKISP1_CIF_ISP_WDR_BASE + 0x00000038)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_10 (RKISP1_CIF_ISP_WDR_BASE + 0x0000003C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_11 (RKISP1_CIF_ISP_WDR_BASE + 0x00000040)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_12 (RKISP1_CIF_ISP_WDR_BASE + 0x00000044)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_13 (RKISP1_CIF_ISP_WDR_BASE + 0x00000048)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_14 (RKISP1_CIF_ISP_WDR_BASE + 0x0000004C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_15 (RKISP1_CIF_ISP_WDR_BASE + 0x00000050)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_16 (RKISP1_CIF_ISP_WDR_BASE + 0x00000054)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_17 (RKISP1_CIF_ISP_WDR_BASE + 0x00000058)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_18 (RKISP1_CIF_ISP_WDR_BASE + 0x0000005C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_19 (RKISP1_CIF_ISP_WDR_BASE + 0x00000060)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_20 (RKISP1_CIF_ISP_WDR_BASE + 0x00000064)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_21 (RKISP1_CIF_ISP_WDR_BASE + 0x00000068)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_22 (RKISP1_CIF_ISP_WDR_BASE + 0x0000006C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_23 (RKISP1_CIF_ISP_WDR_BASE + 0x00000070)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_24 (RKISP1_CIF_ISP_WDR_BASE + 0x00000074)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_25 (RKISP1_CIF_ISP_WDR_BASE + 0x00000078)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_26 (RKISP1_CIF_ISP_WDR_BASE + 0x0000007C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_27 (RKISP1_CIF_ISP_WDR_BASE + 0x00000080)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_28 (RKISP1_CIF_ISP_WDR_BASE + 0x00000084)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_29 (RKISP1_CIF_ISP_WDR_BASE + 0x00000088)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_30 (RKISP1_CIF_ISP_WDR_BASE + 0x0000008C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_31 (RKISP1_CIF_ISP_WDR_BASE + 0x00000090)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_32 (RKISP1_CIF_ISP_WDR_BASE + 0x00000094)
+#define RKISP1_CIF_ISP_WDR_OFFSET (RKISP1_CIF_ISP_WDR_BASE + 0x00000098)
+#define RKISP1_CIF_ISP_WDR_DELTAMIN (RKISP1_CIF_ISP_WDR_BASE + 0x0000009C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_1_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000A0)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_2_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000A4)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_3_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000A8)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_4_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000AC)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_0_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000B0)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_1_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000B4)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_2_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000B8)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_3_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000BC)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_4_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000C0)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_5_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000C4)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_6_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000C8)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_7_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000CC)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_8_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000D0)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_9_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000D4)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_10_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000D8)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_11_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000DC)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_12_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000E0)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_13_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000E4)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_14_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000E8)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_15_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000EC)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_16_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000F0)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_17_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000F4)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_18_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000F8)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_19_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x000000FC)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_20_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000100)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_21_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000104)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_22_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000108)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_23_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x0000010C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_24_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000110)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_25_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000114)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_26_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000118)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_27_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x0000011C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_28_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000120)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_29_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000124)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_30_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000128)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_31_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x0000012C)
+#define RKISP1_CIF_ISP_WDR_TONECURVE_YM_32_SHD (RKISP1_CIF_ISP_WDR_BASE + 0x00000130)
+
+#define RKISP1_CIF_ISP_VSM_BASE 0x00002F00
+#define RKISP1_CIF_ISP_VSM_MODE (RKISP1_CIF_ISP_VSM_BASE + 0x00000000)
+#define RKISP1_CIF_ISP_VSM_H_OFFS (RKISP1_CIF_ISP_VSM_BASE + 0x00000004)
+#define RKISP1_CIF_ISP_VSM_V_OFFS (RKISP1_CIF_ISP_VSM_BASE + 0x00000008)
+#define RKISP1_CIF_ISP_VSM_H_SIZE (RKISP1_CIF_ISP_VSM_BASE + 0x0000000C)
+#define RKISP1_CIF_ISP_VSM_V_SIZE (RKISP1_CIF_ISP_VSM_BASE + 0x00000010)
+#define RKISP1_CIF_ISP_VSM_H_SEGMENTS (RKISP1_CIF_ISP_VSM_BASE + 0x00000014)
+#define RKISP1_CIF_ISP_VSM_V_SEGMENTS (RKISP1_CIF_ISP_VSM_BASE + 0x00000018)
+#define RKISP1_CIF_ISP_VSM_DELTA_H (RKISP1_CIF_ISP_VSM_BASE + 0x0000001C)
+#define RKISP1_CIF_ISP_VSM_DELTA_V (RKISP1_CIF_ISP_VSM_BASE + 0x00000020)
+
+#endif /* _RKISP1_REGS_H */
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
new file mode 100644
index 000000000000..813670ed9577
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-resizer.c
@@ -0,0 +1,846 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Rockchip ISP1 Driver - V4l resizer device
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ *
+ * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rkisp1-common.h"
+
+#define RKISP1_RSZ_SP_DEV_NAME RKISP1_DRIVER_NAME "_resizer_selfpath"
+#define RKISP1_RSZ_MP_DEV_NAME RKISP1_DRIVER_NAME "_resizer_mainpath"
+
+#define RKISP1_DEF_FMT MEDIA_BUS_FMT_YUYV8_2X8
+#define RKISP1_DEF_PIXEL_ENC V4L2_PIXEL_ENC_YUV
+
+struct rkisp1_rsz_yuv_mbus_info {
+ u32 mbus_code;
+ u32 hdiv;
+ u32 vdiv;
+};
+
+static const struct rkisp1_rsz_yuv_mbus_info rkisp1_rsz_yuv_src_formats[] = {
+ {
+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, /* YUV422 */
+ .hdiv = 2,
+ .vdiv = 1,
+ },
+ {
+ .mbus_code = MEDIA_BUS_FMT_YUYV8_1_5X8, /* YUV420 */
+ .hdiv = 2,
+ .vdiv = 2,
+ },
+};
+
+static const struct rkisp1_rsz_yuv_mbus_info *rkisp1_rsz_get_yuv_mbus_info(u32 mbus_code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(rkisp1_rsz_yuv_src_formats); i++) {
+ if (rkisp1_rsz_yuv_src_formats[i].mbus_code == mbus_code)
+ return &rkisp1_rsz_yuv_src_formats[i];
+ }
+
+ return NULL;
+}
+
+enum rkisp1_shadow_regs_when {
+ RKISP1_SHADOW_REGS_SYNC,
+ RKISP1_SHADOW_REGS_ASYNC,
+};
+
+struct rkisp1_rsz_config {
+ /* constrains */
+ const int max_rsz_width;
+ const int max_rsz_height;
+ const int min_rsz_width;
+ const int min_rsz_height;
+ /* registers */
+ struct {
+ u32 ctrl;
+ u32 ctrl_shd;
+ u32 scale_hy;
+ u32 scale_hcr;
+ u32 scale_hcb;
+ u32 scale_vy;
+ u32 scale_vc;
+ u32 scale_lut;
+ u32 scale_lut_addr;
+ u32 scale_hy_shd;
+ u32 scale_hcr_shd;
+ u32 scale_hcb_shd;
+ u32 scale_vy_shd;
+ u32 scale_vc_shd;
+ u32 phase_hy;
+ u32 phase_hc;
+ u32 phase_vy;
+ u32 phase_vc;
+ u32 phase_hy_shd;
+ u32 phase_hc_shd;
+ u32 phase_vy_shd;
+ u32 phase_vc_shd;
+ } rsz;
+ struct {
+ u32 ctrl;
+ u32 yuvmode_mask;
+ u32 rawmode_mask;
+ u32 h_offset;
+ u32 v_offset;
+ u32 h_size;
+ u32 v_size;
+ } dual_crop;
+};
+
+static const struct rkisp1_rsz_config rkisp1_rsz_config_mp = {
+ /* constraints */
+ .max_rsz_width = RKISP1_RSZ_MP_SRC_MAX_WIDTH,
+ .max_rsz_height = RKISP1_RSZ_MP_SRC_MAX_HEIGHT,
+ .min_rsz_width = RKISP1_RSZ_SRC_MIN_WIDTH,
+ .min_rsz_height = RKISP1_RSZ_SRC_MIN_HEIGHT,
+ /* registers */
+ .rsz = {
+ .ctrl = RKISP1_CIF_MRSZ_CTRL,
+ .scale_hy = RKISP1_CIF_MRSZ_SCALE_HY,
+ .scale_hcr = RKISP1_CIF_MRSZ_SCALE_HCR,
+ .scale_hcb = RKISP1_CIF_MRSZ_SCALE_HCB,
+ .scale_vy = RKISP1_CIF_MRSZ_SCALE_VY,
+ .scale_vc = RKISP1_CIF_MRSZ_SCALE_VC,
+ .scale_lut = RKISP1_CIF_MRSZ_SCALE_LUT,
+ .scale_lut_addr = RKISP1_CIF_MRSZ_SCALE_LUT_ADDR,
+ .scale_hy_shd = RKISP1_CIF_MRSZ_SCALE_HY_SHD,
+ .scale_hcr_shd = RKISP1_CIF_MRSZ_SCALE_HCR_SHD,
+ .scale_hcb_shd = RKISP1_CIF_MRSZ_SCALE_HCB_SHD,
+ .scale_vy_shd = RKISP1_CIF_MRSZ_SCALE_VY_SHD,
+ .scale_vc_shd = RKISP1_CIF_MRSZ_SCALE_VC_SHD,
+ .phase_hy = RKISP1_CIF_MRSZ_PHASE_HY,
+ .phase_hc = RKISP1_CIF_MRSZ_PHASE_HC,
+ .phase_vy = RKISP1_CIF_MRSZ_PHASE_VY,
+ .phase_vc = RKISP1_CIF_MRSZ_PHASE_VC,
+ .ctrl_shd = RKISP1_CIF_MRSZ_CTRL_SHD,
+ .phase_hy_shd = RKISP1_CIF_MRSZ_PHASE_HY_SHD,
+ .phase_hc_shd = RKISP1_CIF_MRSZ_PHASE_HC_SHD,
+ .phase_vy_shd = RKISP1_CIF_MRSZ_PHASE_VY_SHD,
+ .phase_vc_shd = RKISP1_CIF_MRSZ_PHASE_VC_SHD,
+ },
+ .dual_crop = {
+ .ctrl = RKISP1_CIF_DUAL_CROP_CTRL,
+ .yuvmode_mask = RKISP1_CIF_DUAL_CROP_MP_MODE_YUV,
+ .rawmode_mask = RKISP1_CIF_DUAL_CROP_MP_MODE_RAW,
+ .h_offset = RKISP1_CIF_DUAL_CROP_M_H_OFFS,
+ .v_offset = RKISP1_CIF_DUAL_CROP_M_V_OFFS,
+ .h_size = RKISP1_CIF_DUAL_CROP_M_H_SIZE,
+ .v_size = RKISP1_CIF_DUAL_CROP_M_V_SIZE,
+ },
+};
+
+static const struct rkisp1_rsz_config rkisp1_rsz_config_sp = {
+ /* constraints */
+ .max_rsz_width = RKISP1_RSZ_SP_SRC_MAX_WIDTH,
+ .max_rsz_height = RKISP1_RSZ_SP_SRC_MAX_HEIGHT,
+ .min_rsz_width = RKISP1_RSZ_SRC_MIN_WIDTH,
+ .min_rsz_height = RKISP1_RSZ_SRC_MIN_HEIGHT,
+ /* registers */
+ .rsz = {
+ .ctrl = RKISP1_CIF_SRSZ_CTRL,
+ .scale_hy = RKISP1_CIF_SRSZ_SCALE_HY,
+ .scale_hcr = RKISP1_CIF_SRSZ_SCALE_HCR,
+ .scale_hcb = RKISP1_CIF_SRSZ_SCALE_HCB,
+ .scale_vy = RKISP1_CIF_SRSZ_SCALE_VY,
+ .scale_vc = RKISP1_CIF_SRSZ_SCALE_VC,
+ .scale_lut = RKISP1_CIF_SRSZ_SCALE_LUT,
+ .scale_lut_addr = RKISP1_CIF_SRSZ_SCALE_LUT_ADDR,
+ .scale_hy_shd = RKISP1_CIF_SRSZ_SCALE_HY_SHD,
+ .scale_hcr_shd = RKISP1_CIF_SRSZ_SCALE_HCR_SHD,
+ .scale_hcb_shd = RKISP1_CIF_SRSZ_SCALE_HCB_SHD,
+ .scale_vy_shd = RKISP1_CIF_SRSZ_SCALE_VY_SHD,
+ .scale_vc_shd = RKISP1_CIF_SRSZ_SCALE_VC_SHD,
+ .phase_hy = RKISP1_CIF_SRSZ_PHASE_HY,
+ .phase_hc = RKISP1_CIF_SRSZ_PHASE_HC,
+ .phase_vy = RKISP1_CIF_SRSZ_PHASE_VY,
+ .phase_vc = RKISP1_CIF_SRSZ_PHASE_VC,
+ .ctrl_shd = RKISP1_CIF_SRSZ_CTRL_SHD,
+ .phase_hy_shd = RKISP1_CIF_SRSZ_PHASE_HY_SHD,
+ .phase_hc_shd = RKISP1_CIF_SRSZ_PHASE_HC_SHD,
+ .phase_vy_shd = RKISP1_CIF_SRSZ_PHASE_VY_SHD,
+ .phase_vc_shd = RKISP1_CIF_SRSZ_PHASE_VC_SHD,
+ },
+ .dual_crop = {
+ .ctrl = RKISP1_CIF_DUAL_CROP_CTRL,
+ .yuvmode_mask = RKISP1_CIF_DUAL_CROP_SP_MODE_YUV,
+ .rawmode_mask = RKISP1_CIF_DUAL_CROP_SP_MODE_RAW,
+ .h_offset = RKISP1_CIF_DUAL_CROP_S_H_OFFS,
+ .v_offset = RKISP1_CIF_DUAL_CROP_S_V_OFFS,
+ .h_size = RKISP1_CIF_DUAL_CROP_S_H_SIZE,
+ .v_size = RKISP1_CIF_DUAL_CROP_S_V_SIZE,
+ },
+};
+
+static struct v4l2_mbus_framefmt *
+rkisp1_rsz_get_pad_fmt(struct rkisp1_resizer *rsz,
+ struct v4l2_subdev_pad_config *cfg,
+ unsigned int pad, u32 which)
+{
+ if (which == V4L2_SUBDEV_FORMAT_TRY)
+ return v4l2_subdev_get_try_format(&rsz->sd, cfg, pad);
+ else
+ return v4l2_subdev_get_try_format(&rsz->sd, rsz->pad_cfg, pad);
+}
+
+static struct v4l2_rect *
+rkisp1_rsz_get_pad_crop(struct rkisp1_resizer *rsz,
+ struct v4l2_subdev_pad_config *cfg,
+ unsigned int pad, u32 which)
+{
+ if (which == V4L2_SUBDEV_FORMAT_TRY)
+ return v4l2_subdev_get_try_crop(&rsz->sd, cfg, pad);
+ else
+ return v4l2_subdev_get_try_crop(&rsz->sd, rsz->pad_cfg, pad);
+}
+
+/* ----------------------------------------------------------------------------
+ * Dual crop hw configs
+ */
+
+static void rkisp1_dcrop_disable(struct rkisp1_resizer *rsz,
+ enum rkisp1_shadow_regs_when when)
+{
+ u32 dc_ctrl = rkisp1_read(rsz->rkisp1, rsz->config->dual_crop.ctrl);
+ u32 mask = ~(rsz->config->dual_crop.yuvmode_mask |
+ rsz->config->dual_crop.rawmode_mask);
+
+ dc_ctrl &= mask;
+ if (when == RKISP1_SHADOW_REGS_ASYNC)
+ dc_ctrl |= RKISP1_CIF_DUAL_CROP_GEN_CFG_UPD;
+ else
+ dc_ctrl |= RKISP1_CIF_DUAL_CROP_CFG_UPD;
+ rkisp1_write(rsz->rkisp1, dc_ctrl, rsz->config->dual_crop.ctrl);
+}
+
+/* configure dual-crop unit */
+static void rkisp1_dcrop_config(struct rkisp1_resizer *rsz)
+{
+ struct rkisp1_device *rkisp1 = rsz->rkisp1;
+ struct v4l2_mbus_framefmt *sink_fmt;
+ struct v4l2_rect *sink_crop;
+ u32 dc_ctrl;
+
+ sink_crop = rkisp1_rsz_get_pad_crop(rsz, NULL, RKISP1_RSZ_PAD_SINK,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, NULL, RKISP1_RSZ_PAD_SINK,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+
+ if (sink_crop->width == sink_fmt->width &&
+ sink_crop->height == sink_fmt->height &&
+ sink_crop->left == 0 && sink_crop->top == 0) {
+ rkisp1_dcrop_disable(rsz, RKISP1_SHADOW_REGS_SYNC);
+ dev_dbg(rkisp1->dev, "capture %d crop disabled\n", rsz->id);
+ return;
+ }
+
+ dc_ctrl = rkisp1_read(rkisp1, rsz->config->dual_crop.ctrl);
+ rkisp1_write(rkisp1, sink_crop->left, rsz->config->dual_crop.h_offset);
+ rkisp1_write(rkisp1, sink_crop->top, rsz->config->dual_crop.v_offset);
+ rkisp1_write(rkisp1, sink_crop->width, rsz->config->dual_crop.h_size);
+ rkisp1_write(rkisp1, sink_crop->height, rsz->config->dual_crop.v_size);
+ dc_ctrl |= rsz->config->dual_crop.yuvmode_mask;
+ dc_ctrl |= RKISP1_CIF_DUAL_CROP_CFG_UPD;
+ rkisp1_write(rkisp1, dc_ctrl, rsz->config->dual_crop.ctrl);
+
+ dev_dbg(rkisp1->dev, "stream %d crop: %dx%d -> %dx%d\n", rsz->id,
+ sink_fmt->width, sink_fmt->height,
+ sink_crop->width, sink_crop->height);
+}
+
+/* ----------------------------------------------------------------------------
+ * Resizer hw configs
+ */
+
+static void rkisp1_rsz_dump_regs(struct rkisp1_resizer *rsz)
+{
+ dev_dbg(rsz->rkisp1->dev,
+ "RSZ_CTRL 0x%08x/0x%08x\n"
+ "RSZ_SCALE_HY %d/%d\n"
+ "RSZ_SCALE_HCB %d/%d\n"
+ "RSZ_SCALE_HCR %d/%d\n"
+ "RSZ_SCALE_VY %d/%d\n"
+ "RSZ_SCALE_VC %d/%d\n"
+ "RSZ_PHASE_HY %d/%d\n"
+ "RSZ_PHASE_HC %d/%d\n"
+ "RSZ_PHASE_VY %d/%d\n"
+ "RSZ_PHASE_VC %d/%d\n",
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hy),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hy_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcb),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcb_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcr),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcr_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vy),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vy_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vc),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vc_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hy),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hy_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hc),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hc_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vy),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vy_shd),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vc),
+ rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vc_shd));
+}
+
+static void rkisp1_rsz_update_shadow(struct rkisp1_resizer *rsz,
+ enum rkisp1_shadow_regs_when when)
+{
+ u32 ctrl_cfg = rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl);
+
+ if (when == RKISP1_SHADOW_REGS_ASYNC)
+ ctrl_cfg |= RKISP1_CIF_RSZ_CTRL_CFG_UPD_AUTO;
+ else
+ ctrl_cfg |= RKISP1_CIF_RSZ_CTRL_CFG_UPD;
+
+ rkisp1_write(rsz->rkisp1, ctrl_cfg, rsz->config->rsz.ctrl);
+}
+
+static u32 rkisp1_rsz_calc_ratio(u32 len_sink, u32 len_src)
+{
+ if (len_sink < len_src)
+ return ((len_sink - 1) * RKISP1_CIF_RSZ_SCALER_FACTOR) /
+ (len_src - 1);
+
+ return ((len_src - 1) * RKISP1_CIF_RSZ_SCALER_FACTOR) /
+ (len_sink - 1) + 1;
+}
+
+static void rkisp1_rsz_disable(struct rkisp1_resizer *rsz,
+ enum rkisp1_shadow_regs_when when)
+{
+ rkisp1_write(rsz->rkisp1, 0, rsz->config->rsz.ctrl);
+
+ if (when == RKISP1_SHADOW_REGS_SYNC)
+ rkisp1_rsz_update_shadow(rsz, when);
+}
+
+static void rkisp1_rsz_config_regs(struct rkisp1_resizer *rsz,
+ struct v4l2_rect *sink_y,
+ struct v4l2_rect *sink_c,
+ struct v4l2_rect *src_y,
+ struct v4l2_rect *src_c,
+ enum rkisp1_shadow_regs_when when)
+{
+ struct rkisp1_device *rkisp1 = rsz->rkisp1;
+ u32 ratio, rsz_ctrl = 0;
+ unsigned int i;
+
+ /* No phase offset */
+ rkisp1_write(rkisp1, 0, rsz->config->rsz.phase_hy);
+ rkisp1_write(rkisp1, 0, rsz->config->rsz.phase_hc);
+ rkisp1_write(rkisp1, 0, rsz->config->rsz.phase_vy);
+ rkisp1_write(rkisp1, 0, rsz->config->rsz.phase_vc);
+
+ /* Linear interpolation */
+ for (i = 0; i < 64; i++) {
+ rkisp1_write(rkisp1, i, rsz->config->rsz.scale_lut_addr);
+ rkisp1_write(rkisp1, i, rsz->config->rsz.scale_lut);
+ }
+
+ if (sink_y->width != src_y->width) {
+ rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HY_ENABLE;
+ if (sink_y->width < src_y->width)
+ rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HY_UP;
+ ratio = rkisp1_rsz_calc_ratio(sink_y->width, src_y->width);
+ rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_hy);
+ }
+
+ if (sink_c->width != src_c->width) {
+ rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HC_ENABLE;
+ if (sink_c->width < src_c->width)
+ rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HC_UP;
+ ratio = rkisp1_rsz_calc_ratio(sink_c->width, src_c->width);
+ rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_hcb);
+ rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_hcr);
+ }
+
+ if (sink_y->height != src_y->height) {
+ rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VY_ENABLE;
+ if (sink_y->height < src_y->height)
+ rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VY_UP;
+ ratio = rkisp1_rsz_calc_ratio(sink_y->height, src_y->height);
+ rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_vy);
+ }
+
+ if (sink_c->height != src_c->height) {
+ rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VC_ENABLE;
+ if (sink_c->height < src_c->height)
+ rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VC_UP;
+ ratio = rkisp1_rsz_calc_ratio(sink_c->height, src_c->height);
+ rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_vc);
+ }
+
+ rkisp1_write(rkisp1, rsz_ctrl, rsz->config->rsz.ctrl);
+
+ rkisp1_rsz_update_shadow(rsz, when);
+}
+
+static void rkisp1_rsz_config(struct rkisp1_resizer *rsz,
+ enum rkisp1_shadow_regs_when when)
+{
+ const struct rkisp1_rsz_yuv_mbus_info *sink_yuv_info, *src_yuv_info;
+ struct v4l2_rect sink_y, sink_c, src_y, src_c;
+ struct v4l2_mbus_framefmt *src_fmt, *sink_fmt;
+ struct v4l2_rect *sink_crop;
+
+ sink_crop = rkisp1_rsz_get_pad_crop(rsz, NULL, RKISP1_RSZ_PAD_SINK,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ src_fmt = rkisp1_rsz_get_pad_fmt(rsz, NULL, RKISP1_RSZ_PAD_SRC,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ src_yuv_info = rkisp1_rsz_get_yuv_mbus_info(src_fmt->code);
+ sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, NULL, RKISP1_RSZ_PAD_SINK,
+ V4L2_SUBDEV_FORMAT_ACTIVE);
+ sink_yuv_info = rkisp1_rsz_get_yuv_mbus_info(sink_fmt->code);
+
+ /*
+ * The resizer only works on yuv formats,
+ * so return if it is bayer format.
+ */
+ if (rsz->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ rkisp1_rsz_disable(rsz, when);
+ return;
+ }
+
+ sink_y.width = sink_crop->width;
+ sink_y.height = sink_crop->height;
+ src_y.width = src_fmt->width;
+ src_y.height = src_fmt->height;
+
+ sink_c.width = sink_y.width / sink_yuv_info->hdiv;
+ sink_c.height = sink_y.height / sink_yuv_info->vdiv;
+
+ /*
+ * The resizer is used not only to change the dimensions of the frame
+ * but also to change the scale for YUV formats,
+ * (4:2:2 -> 4:2:0 for example). So the width/height of the CbCr
+ * streams should be set according to the media bus format in the src pad.
+ */
+ src_c.width = src_y.width / src_yuv_info->hdiv;
+ src_c.height = src_y.height / src_yuv_info->vdiv;
+
+ if (sink_c.width == src_c.width && sink_c.height == src_c.height) {
+ rkisp1_rsz_disable(rsz, when);
+ return;
+ }
+
+ dev_dbg(rsz->rkisp1->dev, "stream %d rsz/scale: %dx%d -> %dx%d\n",
+ rsz->id, sink_crop->width, sink_crop->height,
+ src_fmt->width, src_fmt->height);
+ dev_dbg(rsz->rkisp1->dev, "chroma scaling %dx%d -> %dx%d\n",
+ sink_c.width, sink_c.height, src_c.width, src_c.height);
+
+ /* set values in the hw */
+ rkisp1_rsz_config_regs(rsz, &sink_y, &sink_c, &src_y, &src_c, when);
+
+ rkisp1_rsz_dump_regs(rsz);
+}
+
+/* ----------------------------------------------------------------------------
+ * Subdev pad operations
+ */
+
+static int rkisp1_rsz_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct rkisp1_resizer *rsz =
+ container_of(sd, struct rkisp1_resizer, sd);
+ struct v4l2_subdev_pad_config dummy_cfg;
+ u32 pad = code->pad;
+ int ret;
+
+ if (code->pad == RKISP1_RSZ_PAD_SRC) {
+ /* supported mbus codes on the src are the same as in the capture */
+ struct rkisp1_capture *cap = &rsz->rkisp1->capture_devs[rsz->id];
+
+ return rkisp1_cap_enum_mbus_codes(cap, code);
+ }
+
+ /*
+ * The selfpath capture doesn't support bayer formats. Therefore the selfpath resizer
+ * should support only YUV422 on the sink pad
+ */
+ if (rsz->id == RKISP1_SELFPATH) {
+ if (code->index > 0)
+ return -EINVAL;
+ code->code = MEDIA_BUS_FMT_YUYV8_2X8;
+ return 0;
+ }
+
+ /* supported mbus codes on the sink pad are the same as isp src pad */
+ code->pad = RKISP1_ISP_PAD_SOURCE_VIDEO;
+ ret = v4l2_subdev_call(&rsz->rkisp1->isp.sd, pad, enum_mbus_code,
+ &dummy_cfg, code);
+
+ /* restore pad */
+ code->pad = pad;
+ code->flags = 0;
+ return ret;
+}
+
+static int rkisp1_rsz_init_config(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg)
+{
+ struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+ struct v4l2_rect *sink_crop;
+
+ sink_fmt = v4l2_subdev_get_try_format(sd, cfg, RKISP1_RSZ_PAD_SRC);
+ sink_fmt->width = RKISP1_DEFAULT_WIDTH;
+ sink_fmt->height = RKISP1_DEFAULT_HEIGHT;
+ sink_fmt->field = V4L2_FIELD_NONE;
+ sink_fmt->code = RKISP1_DEF_FMT;
+
+ sink_crop = v4l2_subdev_get_try_crop(sd, cfg, RKISP1_RSZ_PAD_SINK);
+ sink_crop->width = RKISP1_DEFAULT_WIDTH;
+ sink_crop->height = RKISP1_DEFAULT_HEIGHT;
+ sink_crop->left = 0;
+ sink_crop->top = 0;
+
+ src_fmt = v4l2_subdev_get_try_format(sd, cfg, RKISP1_RSZ_PAD_SINK);
+ *src_fmt = *sink_fmt;
+
+ /* NOTE: there is no crop in the source pad, only in the sink */
+
+ return 0;
+}
+
+static void rkisp1_rsz_set_src_fmt(struct rkisp1_resizer *rsz,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_mbus_framefmt *format,
+ unsigned int which)
+{
+ const struct rkisp1_isp_mbus_info *mbus_info;
+ struct v4l2_mbus_framefmt *src_fmt;
+
+ src_fmt = rkisp1_rsz_get_pad_fmt(rsz, cfg, RKISP1_RSZ_PAD_SRC, which);
+ mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
+
+ /* for YUV formats, userspace can change the mbus code on the src pad if it is supported */
+ if (mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV &&
+ rkisp1_rsz_get_yuv_mbus_info(format->code))
+ src_fmt->code = format->code;
+
+ src_fmt->width = clamp_t(u32, format->width,
+ rsz->config->min_rsz_width,
+ rsz->config->max_rsz_width);
+ src_fmt->height = clamp_t(u32, format->height,
+ rsz->config->min_rsz_height,
+ rsz->config->max_rsz_height);
+
+ *format = *src_fmt;
+}
+
+static void rkisp1_rsz_set_sink_crop(struct rkisp1_resizer *rsz,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_rect *r,
+ unsigned int which)
+{
+ const struct rkisp1_isp_mbus_info *mbus_info;
+ struct v4l2_mbus_framefmt *sink_fmt;
+ struct v4l2_rect *sink_crop;
+
+ sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, cfg, RKISP1_RSZ_PAD_SINK, which);
+ sink_crop = rkisp1_rsz_get_pad_crop(rsz, cfg, RKISP1_RSZ_PAD_SINK,
+ which);
+
+ /* Not crop for MP bayer raw data */
+ mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
+
+ if (rsz->id == RKISP1_MAINPATH &&
+ mbus_info->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
+ sink_crop->left = 0;
+ sink_crop->top = 0;
+ sink_crop->width = sink_fmt->width;
+ sink_crop->height = sink_fmt->height;
+
+ *r = *sink_crop;
+ return;
+ }
+
+ sink_crop->left = ALIGN(r->left, 2);
+ sink_crop->width = ALIGN(r->width, 2);
+ sink_crop->top = r->top;
+ sink_crop->height = r->height;
+ rkisp1_sd_adjust_crop(sink_crop, sink_fmt);
+
+ *r = *sink_crop;
+}
+
+static void rkisp1_rsz_set_sink_fmt(struct rkisp1_resizer *rsz,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_mbus_framefmt *format,
+ unsigned int which)
+{
+ const struct rkisp1_isp_mbus_info *mbus_info;
+ struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
+ struct v4l2_rect *sink_crop;
+
+ sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, cfg, RKISP1_RSZ_PAD_SINK, which);
+ src_fmt = rkisp1_rsz_get_pad_fmt(rsz, cfg, RKISP1_RSZ_PAD_SRC, which);
+ sink_crop = rkisp1_rsz_get_pad_crop(rsz, cfg, RKISP1_RSZ_PAD_SINK,
+ which);
+ if (rsz->id == RKISP1_SELFPATH)
+ sink_fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
+ else
+ sink_fmt->code = format->code;
+
+ mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
+ if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SRC)) {
+ sink_fmt->code = RKISP1_DEF_FMT;
+ mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
+ }
+ if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ rsz->pixel_enc = mbus_info->pixel_enc;
+
+ /* Propagete to source pad */
+ src_fmt->code = sink_fmt->code;
+
+ sink_fmt->width = clamp_t(u32, format->width,
+ RKISP1_ISP_MIN_WIDTH,
+ RKISP1_ISP_MAX_WIDTH);
+ sink_fmt->height = clamp_t(u32, format->height,
+ RKISP1_ISP_MIN_HEIGHT,
+ RKISP1_ISP_MAX_HEIGHT);
+
+ *format = *sink_fmt;
+
+ /* Update sink crop */
+ rkisp1_rsz_set_sink_crop(rsz, cfg, sink_crop, which);
+}
+
+static int rkisp1_rsz_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct rkisp1_resizer *rsz =
+ container_of(sd, struct rkisp1_resizer, sd);
+
+ mutex_lock(&rsz->ops_lock);
+ fmt->format = *rkisp1_rsz_get_pad_fmt(rsz, cfg, fmt->pad, fmt->which);
+ mutex_unlock(&rsz->ops_lock);
+ return 0;
+}
+
+static int rkisp1_rsz_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct rkisp1_resizer *rsz =
+ container_of(sd, struct rkisp1_resizer, sd);
+
+ mutex_lock(&rsz->ops_lock);
+ if (fmt->pad == RKISP1_RSZ_PAD_SINK)
+ rkisp1_rsz_set_sink_fmt(rsz, cfg, &fmt->format, fmt->which);
+ else
+ rkisp1_rsz_set_src_fmt(rsz, cfg, &fmt->format, fmt->which);
+
+ mutex_unlock(&rsz->ops_lock);
+ return 0;
+}
+
+static int rkisp1_rsz_get_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct rkisp1_resizer *rsz =
+ container_of(sd, struct rkisp1_resizer, sd);
+ struct v4l2_mbus_framefmt *mf_sink;
+ int ret = 0;
+
+ if (sel->pad == RKISP1_RSZ_PAD_SRC)
+ return -EINVAL;
+
+ mutex_lock(&rsz->ops_lock);
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ mf_sink = rkisp1_rsz_get_pad_fmt(rsz, cfg, RKISP1_RSZ_PAD_SINK,
+ sel->which);
+ sel->r.height = mf_sink->height;
+ sel->r.width = mf_sink->width;
+ sel->r.left = 0;
+ sel->r.top = 0;
+ break;
+ case V4L2_SEL_TGT_CROP:
+ sel->r = *rkisp1_rsz_get_pad_crop(rsz, cfg, RKISP1_RSZ_PAD_SINK,
+ sel->which);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ mutex_unlock(&rsz->ops_lock);
+ return ret;
+}
+
+static int rkisp1_rsz_set_selection(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_selection *sel)
+{
+ struct rkisp1_resizer *rsz =
+ container_of(sd, struct rkisp1_resizer, sd);
+
+ if (sel->target != V4L2_SEL_TGT_CROP || sel->pad == RKISP1_RSZ_PAD_SRC)
+ return -EINVAL;
+
+ dev_dbg(rsz->rkisp1->dev, "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__,
+ sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height);
+
+ mutex_lock(&rsz->ops_lock);
+ rkisp1_rsz_set_sink_crop(rsz, cfg, &sel->r, sel->which);
+ mutex_unlock(&rsz->ops_lock);
+
+ return 0;
+}
+
+static const struct media_entity_operations rkisp1_rsz_media_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct v4l2_subdev_pad_ops rkisp1_rsz_pad_ops = {
+ .enum_mbus_code = rkisp1_rsz_enum_mbus_code,
+ .get_selection = rkisp1_rsz_get_selection,
+ .set_selection = rkisp1_rsz_set_selection,
+ .init_cfg = rkisp1_rsz_init_config,
+ .get_fmt = rkisp1_rsz_get_fmt,
+ .set_fmt = rkisp1_rsz_set_fmt,
+ .link_validate = v4l2_subdev_link_validate_default,
+};
+
+/* ----------------------------------------------------------------------------
+ * Stream operations
+ */
+
+static int rkisp1_rsz_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct rkisp1_resizer *rsz =
+ container_of(sd, struct rkisp1_resizer, sd);
+ struct rkisp1_device *rkisp1 = rsz->rkisp1;
+ struct rkisp1_capture *other = &rkisp1->capture_devs[rsz->id ^ 1];
+ enum rkisp1_shadow_regs_when when = RKISP1_SHADOW_REGS_SYNC;
+
+ if (!enable) {
+ rkisp1_dcrop_disable(rsz, RKISP1_SHADOW_REGS_ASYNC);
+ rkisp1_rsz_disable(rsz, RKISP1_SHADOW_REGS_ASYNC);
+ return 0;
+ }
+
+ if (other->is_streaming)
+ when = RKISP1_SHADOW_REGS_ASYNC;
+
+ mutex_lock(&rsz->ops_lock);
+ rkisp1_rsz_config(rsz, when);
+ rkisp1_dcrop_config(rsz);
+
+ mutex_unlock(&rsz->ops_lock);
+ return 0;
+}
+
+static const struct v4l2_subdev_video_ops rkisp1_rsz_video_ops = {
+ .s_stream = rkisp1_rsz_s_stream,
+};
+
+static const struct v4l2_subdev_ops rkisp1_rsz_ops = {
+ .video = &rkisp1_rsz_video_ops,
+ .pad = &rkisp1_rsz_pad_ops,
+};
+
+static void rkisp1_rsz_unregister(struct rkisp1_resizer *rsz)
+{
+ v4l2_device_unregister_subdev(&rsz->sd);
+ media_entity_cleanup(&rsz->sd.entity);
+}
+
+static int rkisp1_rsz_register(struct rkisp1_resizer *rsz)
+{
+ static const char * const dev_names[] = {
+ RKISP1_RSZ_MP_DEV_NAME,
+ RKISP1_RSZ_SP_DEV_NAME
+ };
+ struct media_pad *pads = rsz->pads;
+ struct v4l2_subdev *sd = &rsz->sd;
+ int ret;
+
+ if (rsz->id == RKISP1_SELFPATH)
+ rsz->config = &rkisp1_rsz_config_sp;
+ else
+ rsz->config = &rkisp1_rsz_config_mp;
+
+ v4l2_subdev_init(sd, &rkisp1_rsz_ops);
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ sd->entity.ops = &rkisp1_rsz_media_ops;
+ sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
+ sd->owner = THIS_MODULE;
+ strscpy(sd->name, dev_names[rsz->id], sizeof(sd->name));
+
+ pads[RKISP1_RSZ_PAD_SINK].flags = MEDIA_PAD_FL_SINK |
+ MEDIA_PAD_FL_MUST_CONNECT;
+ pads[RKISP1_RSZ_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE |
+ MEDIA_PAD_FL_MUST_CONNECT;
+
+ rsz->pixel_enc = RKISP1_DEF_PIXEL_ENC;
+
+ mutex_init(&rsz->ops_lock);
+ ret = media_entity_pads_init(&sd->entity, RKISP1_RSZ_PAD_MAX, pads);
+ if (ret)
+ return ret;
+
+ ret = v4l2_device_register_subdev(&rsz->rkisp1->v4l2_dev, sd);
+ if (ret) {
+ dev_err(sd->dev, "Failed to register resizer subdev\n");
+ goto err_cleanup_media_entity;
+ }
+
+ rkisp1_rsz_init_config(sd, rsz->pad_cfg);
+ return 0;
+
+err_cleanup_media_entity:
+ media_entity_cleanup(&sd->entity);
+
+ return ret;
+}
+
+int rkisp1_resizer_devs_register(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_resizer *rsz;
+ unsigned int i, j;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(rkisp1->resizer_devs); i++) {
+ rsz = &rkisp1->resizer_devs[i];
+ rsz->rkisp1 = rkisp1;
+ rsz->id = i;
+ ret = rkisp1_rsz_register(rsz);
+ if (ret)
+ goto err_unreg_resizer_devs;
+ }
+
+ return 0;
+
+err_unreg_resizer_devs:
+ for (j = 0; j < i; j++) {
+ rsz = &rkisp1->resizer_devs[j];
+ rkisp1_rsz_unregister(rsz);
+ }
+
+ return ret;
+}
+
+void rkisp1_resizer_devs_unregister(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_resizer *mp = &rkisp1->resizer_devs[RKISP1_MAINPATH];
+ struct rkisp1_resizer *sp = &rkisp1->resizer_devs[RKISP1_SELFPATH];
+
+ rkisp1_rsz_unregister(mp);
+ rkisp1_rsz_unregister(sp);
+}
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
new file mode 100644
index 000000000000..3ddab8fa8f2d
--- /dev/null
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-stats.c
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Rockchip ISP1 Driver - Stats subdevice
+ *
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-vmalloc.h> /* for ISP statistics */
+
+#include "rkisp1-common.h"
+
+#define RKISP1_STATS_DEV_NAME RKISP1_DRIVER_NAME "_stats"
+
+#define RKISP1_ISP_STATS_REQ_BUFS_MIN 2
+#define RKISP1_ISP_STATS_REQ_BUFS_MAX 8
+
+static int rkisp1_stats_enum_fmt_meta_cap(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct video_device *video = video_devdata(file);
+ struct rkisp1_stats *stats = video_get_drvdata(video);
+
+ if (f->index > 0 || f->type != video->queue->type)
+ return -EINVAL;
+
+ f->pixelformat = stats->vdev_fmt.fmt.meta.dataformat;
+ return 0;
+}
+
+static int rkisp1_stats_g_fmt_meta_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct video_device *video = video_devdata(file);
+ struct rkisp1_stats *stats = video_get_drvdata(video);
+ struct v4l2_meta_format *meta = &f->fmt.meta;
+
+ if (f->type != video->queue->type)
+ return -EINVAL;
+
+ memset(meta, 0, sizeof(*meta));
+ meta->dataformat = stats->vdev_fmt.fmt.meta.dataformat;
+ meta->buffersize = stats->vdev_fmt.fmt.meta.buffersize;
+
+ return 0;
+}
+
+static int rkisp1_stats_querycap(struct file *file,
+ void *priv, struct v4l2_capability *cap)
+{
+ struct video_device *vdev = video_devdata(file);
+
+ strscpy(cap->driver, RKISP1_DRIVER_NAME, sizeof(cap->driver));
+ strscpy(cap->card, vdev->name, sizeof(cap->card));
+ strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info));
+
+ return 0;
+}
+
+/* ISP video device IOCTLs */
+static const struct v4l2_ioctl_ops rkisp1_stats_ioctl = {
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_enum_fmt_meta_cap = rkisp1_stats_enum_fmt_meta_cap,
+ .vidioc_g_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap,
+ .vidioc_s_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap,
+ .vidioc_try_fmt_meta_cap = rkisp1_stats_g_fmt_meta_cap,
+ .vidioc_querycap = rkisp1_stats_querycap,
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static const struct v4l2_file_operations rkisp1_stats_fops = {
+ .mmap = vb2_fop_mmap,
+ .unlocked_ioctl = video_ioctl2,
+ .poll = vb2_fop_poll,
+ .open = v4l2_fh_open,
+ .release = vb2_fop_release
+};
+
+static int rkisp1_stats_vb2_queue_setup(struct vb2_queue *vq,
+ unsigned int *num_buffers,
+ unsigned int *num_planes,
+ unsigned int sizes[],
+ struct device *alloc_devs[])
+{
+ *num_planes = 1;
+
+ *num_buffers = clamp_t(u32, *num_buffers, RKISP1_ISP_STATS_REQ_BUFS_MIN,
+ RKISP1_ISP_STATS_REQ_BUFS_MAX);
+
+ sizes[0] = sizeof(struct rkisp1_stat_buffer);
+
+ return 0;
+}
+
+static void rkisp1_stats_vb2_buf_queue(struct vb2_buffer *vb)
+{
+ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+ struct rkisp1_buffer *stats_buf =
+ container_of(vbuf, struct rkisp1_buffer, vb);
+ struct vb2_queue *vq = vb->vb2_queue;
+ struct rkisp1_stats *stats_dev = vq->drv_priv;
+
+ stats_buf->vaddr = vb2_plane_vaddr(vb, 0);
+
+ spin_lock_irq(&stats_dev->lock);
+ list_add_tail(&stats_buf->queue, &stats_dev->stat);
+ spin_unlock_irq(&stats_dev->lock);
+}
+
+static int rkisp1_stats_vb2_buf_prepare(struct vb2_buffer *vb)
+{
+ if (vb2_plane_size(vb, 0) < sizeof(struct rkisp1_stat_buffer))
+ return -EINVAL;
+
+ vb2_set_plane_payload(vb, 0, sizeof(struct rkisp1_stat_buffer));
+
+ return 0;
+}
+
+static void rkisp1_stats_vb2_stop_streaming(struct vb2_queue *vq)
+{
+ struct rkisp1_stats *stats = vq->drv_priv;
+ struct rkisp1_buffer *buf;
+ unsigned int i;
+
+ spin_lock_irq(&stats->lock);
+ for (i = 0; i < RKISP1_ISP_STATS_REQ_BUFS_MAX; i++) {
+ if (list_empty(&stats->stat))
+ break;
+ buf = list_first_entry(&stats->stat,
+ struct rkisp1_buffer, queue);
+ list_del(&buf->queue);
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+ }
+ spin_unlock_irq(&stats->lock);
+}
+
+static const struct vb2_ops rkisp1_stats_vb2_ops = {
+ .queue_setup = rkisp1_stats_vb2_queue_setup,
+ .buf_queue = rkisp1_stats_vb2_buf_queue,
+ .buf_prepare = rkisp1_stats_vb2_buf_prepare,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+ .stop_streaming = rkisp1_stats_vb2_stop_streaming,
+};
+
+static int
+rkisp1_stats_init_vb2_queue(struct vb2_queue *q, struct rkisp1_stats *stats)
+{
+ struct rkisp1_vdev_node *node;
+
+ node = container_of(q, struct rkisp1_vdev_node, buf_queue);
+
+ q->type = V4L2_BUF_TYPE_META_CAPTURE;
+ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
+ q->drv_priv = stats;
+ q->ops = &rkisp1_stats_vb2_ops;
+ q->mem_ops = &vb2_vmalloc_memops;
+ q->buf_struct_size = sizeof(struct rkisp1_buffer);
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->lock = &node->vlock;
+
+ return vb2_queue_init(q);
+}
+
+static void rkisp1_stats_get_awb_meas(struct rkisp1_stats *stats,
+ struct rkisp1_stat_buffer *pbuf)
+{
+ /* Protect against concurrent access from ISR? */
+ struct rkisp1_device *rkisp1 = stats->rkisp1;
+ u32 reg_val;
+
+ pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AWB;
+ reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT);
+ pbuf->params.awb.awb_mean[0].cnt =
+ RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
+ reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN);
+
+ pbuf->params.awb.awb_mean[0].mean_cr_or_r =
+ RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
+ pbuf->params.awb.awb_mean[0].mean_cb_or_b =
+ RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
+ pbuf->params.awb.awb_mean[0].mean_y_or_g =
+ RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
+}
+
+static void rkisp1_stats_get_aec_meas(struct rkisp1_stats *stats,
+ struct rkisp1_stat_buffer *pbuf)
+{
+ struct rkisp1_device *rkisp1 = stats->rkisp1;
+ unsigned int i;
+
+ pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AUTOEXP;
+ for (i = 0; i < RKISP1_CIF_ISP_AE_MEAN_MAX; i++)
+ pbuf->params.ae.exp_mean[i] =
+ (u8)rkisp1_read(rkisp1,
+ RKISP1_CIF_ISP_EXP_MEAN_00 + i * 4);
+}
+
+static void rkisp1_stats_get_afc_meas(struct rkisp1_stats *stats,
+ struct rkisp1_stat_buffer *pbuf)
+{
+ struct rkisp1_device *rkisp1 = stats->rkisp1;
+ struct rkisp1_cif_isp_af_stat *af;
+
+ pbuf->meas_type |= RKISP1_CIF_ISP_STAT_AFM;
+
+ af = &pbuf->params.af;
+ af->window[0].sum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_SUM_A);
+ af->window[0].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_A);
+ af->window[1].sum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_SUM_B);
+ af->window[1].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_B);
+ af->window[2].sum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_SUM_C);
+ af->window[2].lum = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AFM_LUM_C);
+}
+
+static void rkisp1_stats_get_hst_meas(struct rkisp1_stats *stats,
+ struct rkisp1_stat_buffer *pbuf)
+{
+ struct rkisp1_device *rkisp1 = stats->rkisp1;
+ unsigned int i;
+
+ pbuf->meas_type |= RKISP1_CIF_ISP_STAT_HIST;
+ for (i = 0; i < RKISP1_CIF_ISP_HIST_BIN_N_MAX; i++)
+ pbuf->params.hist.hist_bins[i] =
+ (u8)rkisp1_read(rkisp1,
+ RKISP1_CIF_ISP_HIST_BIN_0 + i * 4);
+}
+
+static void rkisp1_stats_get_bls_meas(struct rkisp1_stats *stats,
+ struct rkisp1_stat_buffer *pbuf)
+{
+ struct rkisp1_device *rkisp1 = stats->rkisp1;
+ const struct rkisp1_isp_mbus_info *in_fmt = rkisp1->isp.sink_fmt;
+ struct rkisp1_cif_isp_bls_meas_val *bls_val;
+
+ bls_val = &pbuf->params.ae.bls_val;
+ if (in_fmt->bayer_pat == RKISP1_RAW_BGGR) {
+ bls_val->meas_b =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_A_MEASURED);
+ bls_val->meas_gb =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_B_MEASURED);
+ bls_val->meas_gr =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_C_MEASURED);
+ bls_val->meas_r =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_D_MEASURED);
+ } else if (in_fmt->bayer_pat == RKISP1_RAW_GBRG) {
+ bls_val->meas_gb =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_A_MEASURED);
+ bls_val->meas_b =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_B_MEASURED);
+ bls_val->meas_r =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_C_MEASURED);
+ bls_val->meas_gr =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_D_MEASURED);
+ } else if (in_fmt->bayer_pat == RKISP1_RAW_GRBG) {
+ bls_val->meas_gr =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_A_MEASURED);
+ bls_val->meas_r =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_B_MEASURED);
+ bls_val->meas_b =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_C_MEASURED);
+ bls_val->meas_gb =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_D_MEASURED);
+ } else if (in_fmt->bayer_pat == RKISP1_RAW_RGGB) {
+ bls_val->meas_r =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_A_MEASURED);
+ bls_val->meas_gr =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_B_MEASURED);
+ bls_val->meas_gb =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_C_MEASURED);
+ bls_val->meas_b =
+ rkisp1_read(rkisp1, RKISP1_CIF_ISP_BLS_D_MEASURED);
+ }
+}
+
+static void
+rkisp1_stats_send_measurement(struct rkisp1_stats *stats, u32 isp_ris)
+{
+ struct rkisp1_stat_buffer *cur_stat_buf;
+ struct rkisp1_buffer *cur_buf = NULL;
+ unsigned int frame_sequence = stats->rkisp1->isp.frame_sequence;
+ u64 timestamp = ktime_get_ns();
+
+ /* get one empty buffer */
+ if (!list_empty(&stats->stat)) {
+ cur_buf = list_first_entry(&stats->stat,
+ struct rkisp1_buffer, queue);
+ list_del(&cur_buf->queue);
+ }
+
+ if (!cur_buf)
+ return;
+
+ cur_stat_buf =
+ (struct rkisp1_stat_buffer *)(cur_buf->vaddr);
+
+ if (isp_ris & RKISP1_CIF_ISP_AWB_DONE)
+ rkisp1_stats_get_awb_meas(stats, cur_stat_buf);
+
+ if (isp_ris & RKISP1_CIF_ISP_AFM_FIN)
+ rkisp1_stats_get_afc_meas(stats, cur_stat_buf);
+
+ if (isp_ris & RKISP1_CIF_ISP_EXP_END) {
+ rkisp1_stats_get_aec_meas(stats, cur_stat_buf);
+ rkisp1_stats_get_bls_meas(stats, cur_stat_buf);
+ }
+
+ if (isp_ris & RKISP1_CIF_ISP_HIST_MEASURE_RDY)
+ rkisp1_stats_get_hst_meas(stats, cur_stat_buf);
+
+ vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0,
+ sizeof(struct rkisp1_stat_buffer));
+ cur_buf->vb.sequence = frame_sequence;
+ cur_buf->vb.vb2_buf.timestamp = timestamp;
+ vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
+}
+
+void rkisp1_stats_isr(struct rkisp1_stats *stats, u32 isp_ris)
+{
+ struct rkisp1_device *rkisp1 = stats->rkisp1;
+ unsigned int isp_mis_tmp = 0;
+
+ spin_lock(&stats->lock);
+
+ rkisp1_write(rkisp1, RKISP1_STATS_MEAS_MASK, RKISP1_CIF_ISP_ICR);
+
+ isp_mis_tmp = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS);
+ if (isp_mis_tmp & RKISP1_STATS_MEAS_MASK)
+ rkisp1->debug.stats_error++;
+
+ if (isp_ris & RKISP1_STATS_MEAS_MASK)
+ rkisp1_stats_send_measurement(stats, isp_ris);
+
+ spin_unlock(&stats->lock);
+}
+
+static void rkisp1_init_stats(struct rkisp1_stats *stats)
+{
+ stats->vdev_fmt.fmt.meta.dataformat =
+ V4L2_META_FMT_RK_ISP1_STAT_3A;
+ stats->vdev_fmt.fmt.meta.buffersize =
+ sizeof(struct rkisp1_stat_buffer);
+}
+
+int rkisp1_stats_register(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_stats *stats = &rkisp1->stats;
+ struct rkisp1_vdev_node *node = &stats->vnode;
+ struct video_device *vdev = &node->vdev;
+ int ret;
+
+ stats->rkisp1 = rkisp1;
+ mutex_init(&node->vlock);
+ INIT_LIST_HEAD(&stats->stat);
+ spin_lock_init(&stats->lock);
+
+ strscpy(vdev->name, RKISP1_STATS_DEV_NAME, sizeof(vdev->name));
+
+ video_set_drvdata(vdev, stats);
+ vdev->ioctl_ops = &rkisp1_stats_ioctl;
+ vdev->fops = &rkisp1_stats_fops;
+ vdev->release = video_device_release_empty;
+ vdev->lock = &node->vlock;
+ vdev->v4l2_dev = &rkisp1->v4l2_dev;
+ vdev->queue = &node->buf_queue;
+ vdev->device_caps = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING;
+ vdev->vfl_dir = VFL_DIR_RX;
+ rkisp1_stats_init_vb2_queue(vdev->queue, stats);
+ rkisp1_init_stats(stats);
+ video_set_drvdata(vdev, stats);
+
+ node->pad.flags = MEDIA_PAD_FL_SINK;
+ ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
+ if (ret)
+ goto err_mutex_destroy;
+
+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+ if (ret) {
+ dev_err(&vdev->dev,
+ "failed to register %s, ret=%d\n", vdev->name, ret);
+ goto err_cleanup_media_entity;
+ }
+
+ return 0;
+
+err_cleanup_media_entity:
+ media_entity_cleanup(&vdev->entity);
+err_mutex_destroy:
+ mutex_destroy(&node->vlock);
+ return ret;
+}
+
+void rkisp1_stats_unregister(struct rkisp1_device *rkisp1)
+{
+ struct rkisp1_stats *stats = &rkisp1->stats;
+ struct rkisp1_vdev_node *node = &stats->vnode;
+ struct video_device *vdev = &node->vdev;
+
+ vb2_video_unregister_device(vdev);
+ media_entity_cleanup(&vdev->entity);
+ mutex_destroy(&node->vlock);
+}
diff --git a/drivers/media/platform/s3c-camif/camif-core.c b/drivers/media/platform/s3c-camif/camif-core.c
index 422fd549e9c8..4c3c00d59c92 100644
--- a/drivers/media/platform/s3c-camif/camif-core.c
+++ b/drivers/media/platform/s3c-camif/camif-core.c
@@ -131,11 +131,13 @@ static int camif_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
while (sh--) {
unsigned int tmp = 1 << sh;
if (src >= tar * tmp) {
- *shift = sh, *ratio = tmp;
+ *shift = sh;
+ *ratio = tmp;
return 0;
}
}
- *shift = 0, *ratio = 1;
+ *shift = 0;
+ *ratio = 1;
return 0;
}
diff --git a/drivers/media/platform/s5p-jpeg/jpeg-core.c b/drivers/media/platform/s5p-jpeg/jpeg-core.c
index 9b22dd8e34f4..026111505f5a 100644
--- a/drivers/media/platform/s5p-jpeg/jpeg-core.c
+++ b/drivers/media/platform/s5p-jpeg/jpeg-core.c
@@ -2862,6 +2862,8 @@ static int s5p_jpeg_probe(struct platform_device *pdev)
return -ENOMEM;
jpeg->variant = jpeg_get_drv_data(&pdev->dev);
+ if (!jpeg->variant)
+ return -ENODEV;
mutex_init(&jpeg->lock);
spin_lock_init(&jpeg->slock);
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
index 61e144a35201..a71753d459ba 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
@@ -1109,7 +1109,7 @@ const struct v4l2_ioctl_ops *get_dec_v4l2_ioctl_ops(void)
return &s5p_mfc_dec_ioctl_ops;
}
-#define IS_MFC51_PRIV(x) ((V4L2_CTRL_ID2WHICH(x) == V4L2_CTRL_CLASS_MPEG) \
+#define IS_MFC51_PRIV(x) ((V4L2_CTRL_ID2WHICH(x) == V4L2_CTRL_CLASS_CODEC) \
&& V4L2_CTRL_DRIVER_PRIV(x))
int s5p_mfc_dec_ctrls_setup(struct s5p_mfc_ctx *ctx)
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
index acc2217dd7e9..1fad99edb091 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
@@ -2614,7 +2614,7 @@ const struct v4l2_ioctl_ops *get_enc_v4l2_ioctl_ops(void)
return &s5p_mfc_enc_ioctl_ops;
}
-#define IS_MFC51_PRIV(x) ((V4L2_CTRL_ID2WHICH(x) == V4L2_CTRL_CLASS_MPEG) \
+#define IS_MFC51_PRIV(x) ((V4L2_CTRL_ID2WHICH(x) == V4L2_CTRL_CLASS_CODEC) \
&& V4L2_CTRL_DRIVER_PRIV(x))
int s5p_mfc_enc_ctrls_setup(struct s5p_mfc_ctx *ctx)
diff --git a/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c b/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c
index dbe7788083a4..5ceb366648b3 100644
--- a/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c
+++ b/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c
@@ -765,7 +765,7 @@ static int c8sectpfe_probe(struct platform_device *pdev)
if (!fei->channel_data[index]) {
ret = -ENOMEM;
- goto err_clk_disable;
+ goto err_node_put;
}
tsin = fei->channel_data[index];
@@ -775,7 +775,7 @@ static int c8sectpfe_probe(struct platform_device *pdev)
ret = of_property_read_u32(child, "tsin-num", &tsin->tsin_id);
if (ret) {
dev_err(&pdev->dev, "No tsin_num found\n");
- goto err_clk_disable;
+ goto err_node_put;
}
/* sanity check value */
@@ -784,7 +784,7 @@ static int c8sectpfe_probe(struct platform_device *pdev)
"tsin-num %d specified greater than number\n\tof input block hw in SoC! (%d)",
tsin->tsin_id, fei->hw_stats.num_ib);
ret = -EINVAL;
- goto err_clk_disable;
+ goto err_node_put;
}
tsin->invert_ts_clk = of_property_read_bool(child,
@@ -800,14 +800,14 @@ static int c8sectpfe_probe(struct platform_device *pdev)
&tsin->dvb_card);
if (ret) {
dev_err(&pdev->dev, "No dvb-card found\n");
- goto err_clk_disable;
+ goto err_node_put;
}
i2c_bus = of_parse_phandle(child, "i2c-bus", 0);
if (!i2c_bus) {
dev_err(&pdev->dev, "No i2c-bus found\n");
ret = -ENODEV;
- goto err_clk_disable;
+ goto err_node_put;
}
tsin->i2c_adapter =
of_find_i2c_adapter_by_node(i2c_bus);
@@ -815,7 +815,7 @@ static int c8sectpfe_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "No i2c adapter found\n");
of_node_put(i2c_bus);
ret = -ENODEV;
- goto err_clk_disable;
+ goto err_node_put;
}
of_node_put(i2c_bus);
@@ -826,7 +826,7 @@ static int c8sectpfe_probe(struct platform_device *pdev)
dev_err(dev,
"reset gpio for tsin%d not valid (gpio=%d)\n",
tsin->tsin_id, tsin->rst_gpio);
- goto err_clk_disable;
+ goto err_node_put;
}
ret = devm_gpio_request_one(dev, tsin->rst_gpio,
@@ -834,7 +834,7 @@ static int c8sectpfe_probe(struct platform_device *pdev)
if (ret && ret != -EBUSY) {
dev_err(dev, "Can't request tsin%d reset gpio\n"
, fei->channel_data[index]->tsin_id);
- goto err_clk_disable;
+ goto err_node_put;
}
if (!ret) {
@@ -877,6 +877,8 @@ static int c8sectpfe_probe(struct platform_device *pdev)
return 0;
+err_node_put:
+ of_node_put(child);
err_clk_disable:
clk_disable_unprepare(fei->c8sectpfeclk);
return ret;
@@ -1032,9 +1034,8 @@ static void load_imem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr,
dev_dbg(fei->dev,
"Loading IMEM segment %d 0x%08x\n\t (0x%x bytes) -> 0x%p (0x%x bytes)\n",
-seg_num,
- phdr->p_paddr, phdr->p_filesz,
- dest, phdr->p_memsz + phdr->p_memsz / 3);
+ seg_num, phdr->p_paddr, phdr->p_filesz, dest,
+ phdr->p_memsz + phdr->p_memsz / 3);
for (i = 0; i < phdr->p_filesz; i++) {
diff --git a/drivers/media/platform/stm32/stm32-dcmi.c b/drivers/media/platform/stm32/stm32-dcmi.c
index fd1c41cba52f..b745f1342c2e 100644
--- a/drivers/media/platform/stm32/stm32-dcmi.c
+++ b/drivers/media/platform/stm32/stm32-dcmi.c
@@ -157,6 +157,7 @@ struct stm32_dcmi {
struct vb2_queue queue;
struct v4l2_fwnode_bus_parallel bus;
+ enum v4l2_mbus_type bus_type;
struct completion complete;
struct clk *mclk;
enum state state;
@@ -324,7 +325,7 @@ static int dcmi_start_dma(struct stm32_dcmi *dcmi,
}
/*
- * Avoid call of dmaengine_terminate_all() between
+ * Avoid call of dmaengine_terminate_sync() between
* dmaengine_prep_slave_single() and dmaengine_submit()
* by locking the whole DMA submission sequence
*/
@@ -438,7 +439,7 @@ static void dcmi_process_jpeg(struct stm32_dcmi *dcmi)
}
/* Abort DMA operation */
- dmaengine_terminate_all(dcmi->dma_chan);
+ dmaengine_terminate_sync(dcmi->dma_chan);
/* Restart capture */
if (dcmi_restart_capture(dcmi))
@@ -777,6 +778,23 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count)
if (dcmi->bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
val |= CR_PCKPOL;
+ /*
+ * BT656 embedded synchronisation bus mode.
+ *
+ * Default SAV/EAV mode is supported here with default codes
+ * SAV=0xff000080 & EAV=0xff00009d.
+ * With DCMI this means LSC=SAV=0x80 & LEC=EAV=0x9d.
+ */
+ if (dcmi->bus_type == V4L2_MBUS_BT656) {
+ val |= CR_ESS;
+
+ /* Unmask all codes */
+ reg_write(dcmi->regs, DCMI_ESUR, 0xffffffff);/* FEC:LEC:LSC:FSC */
+
+ /* Trig on LSC=0x80 & LEC=0x9d codes, ignore FSC and FEC */
+ reg_write(dcmi->regs, DCMI_ESCR, 0xff9d80ff);/* FEC:LEC:LSC:FSC */
+ }
+
reg_write(dcmi->regs, DCMI_CR, val);
/* Set crop */
@@ -882,7 +900,7 @@ static void dcmi_stop_streaming(struct vb2_queue *vq)
/* Stop all pending DMA operations */
mutex_lock(&dcmi->dma_lock);
- dmaengine_terminate_all(dcmi->dma_chan);
+ dmaengine_terminate_sync(dcmi->dma_chan);
mutex_unlock(&dcmi->dma_lock);
pm_runtime_put(dcmi->dev);
@@ -1067,8 +1085,9 @@ static int dcmi_set_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f)
if (ret)
return ret;
- /* Disable crop if JPEG is requested */
- if (pix->pixelformat == V4L2_PIX_FMT_JPEG)
+ /* Disable crop if JPEG is requested or BT656 bus is selected */
+ if (pix->pixelformat == V4L2_PIX_FMT_JPEG &&
+ dcmi->bus_type != V4L2_MBUS_BT656)
dcmi->do_crop = false;
/* pix to mbus format */
@@ -1574,6 +1593,22 @@ static const struct dcmi_format dcmi_formats[] = {
.fourcc = V4L2_PIX_FMT_JPEG,
.mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
.bpp = 1,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SBGGR8,
+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
+ .bpp = 1,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGBRG8,
+ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
+ .bpp = 1,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
+ .bpp = 1,
+ }, {
+ .fourcc = V4L2_PIX_FMT_SRGGB8,
+ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
+ .bpp = 1,
},
};
@@ -1592,6 +1627,11 @@ static int dcmi_formats_init(struct stm32_dcmi *dcmi)
if (dcmi_formats[i].mbus_code != mbus_code.code)
continue;
+ /* Exclude JPEG if BT656 bus is selected */
+ if (dcmi_formats[i].fourcc == V4L2_PIX_FMT_JPEG &&
+ dcmi->bus_type == V4L2_MBUS_BT656)
+ continue;
+
/* Code supported, have we got this fourcc yet? */
for (j = 0; j < num_fmts; j++)
if (sd_fmts[j]->fourcc ==
@@ -1851,7 +1891,9 @@ static int dcmi_probe(struct platform_device *pdev)
dcmi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(dcmi->rstc)) {
- dev_err(&pdev->dev, "Could not get reset control\n");
+ if (PTR_ERR(dcmi->rstc) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Could not get reset control\n");
+
return PTR_ERR(dcmi->rstc);
}
@@ -1873,9 +1915,18 @@ static int dcmi_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "CSI bus not supported\n");
return -ENODEV;
}
+
+ if (ep.bus_type == V4L2_MBUS_BT656 &&
+ ep.bus.parallel.bus_width != 8) {
+ dev_err(&pdev->dev, "BT656 bus conflicts with %u bits bus width (8 bits required)\n",
+ ep.bus.parallel.bus_width);
+ return -ENODEV;
+ }
+
dcmi->bus.flags = ep.bus.parallel.flags;
dcmi->bus.bus_width = ep.bus.parallel.bus_width;
dcmi->bus.data_shift = ep.bus.parallel.data_shift;
+ dcmi->bus_type = ep.bus_type;
irq = platform_get_irq(pdev, 0);
if (irq <= 0)
diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c
index 8f4e254b6a41..1a2f65d83a6c 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c
@@ -363,7 +363,7 @@ int sun4i_csi_v4l2_register(struct sun4i_csi *csi)
vdev->lock = &csi->lock;
/* Set a default format */
- csi->fmt.pixelformat = sun4i_csi_formats[0].fourcc,
+ csi->fmt.pixelformat = sun4i_csi_formats[0].fourcc;
csi->fmt.width = CSI_DEFAULT_WIDTH;
csi->fmt.height = CSI_DEFAULT_HEIGHT;
_sun4i_csi_try_fmt(csi, &csi->fmt);
diff --git a/drivers/media/radio/radio-sf16fmr2.c b/drivers/media/radio/radio-sf16fmr2.c
index bd323e640f1a..0388894cfe41 100644
--- a/drivers/media/radio/radio-sf16fmr2.c
+++ b/drivers/media/radio/radio-sf16fmr2.c
@@ -215,7 +215,7 @@ static int fmr2_probe(struct fmr2 *fmr2, struct device *pdev, int io)
return -EBUSY;
strscpy(fmr2->v4l2_dev.name, "radio-sf16fmr2",
- sizeof(fmr2->v4l2_dev.name)),
+ sizeof(fmr2->v4l2_dev.name));
fmr2->io = io;
if (!request_region(fmr2->io, 2, fmr2->v4l2_dev.name)) {
diff --git a/drivers/media/radio/si4713/si4713.c b/drivers/media/radio/si4713/si4713.c
index 6afa7c3464ab..adbf43ff6a21 100644
--- a/drivers/media/radio/si4713/si4713.c
+++ b/drivers/media/radio/si4713/si4713.c
@@ -86,7 +86,7 @@ MODULE_VERSION("0.0.1");
#define check_command_failed(status) (!(status & SI4713_CTS) || \
(status & SI4713_ERR))
/* mute definition */
-#define set_mute(p) ((p & 1) | ((p & 1) << 1));
+#define set_mute(p) (((p) & 1) | (((p) & 1) << 1))
#ifdef DEBUG
#define DBG_BUFFER(device, message, buffer, size) \
diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
index aaa1bf81d00d..b252a1d2ebd6 100644
--- a/drivers/media/rc/keymaps/Makefile
+++ b/drivers/media/rc/keymaps/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
rc-it913x-v2.o \
rc-kaiomy.o \
rc-khadas.o \
+ rc-khamsin.o \
rc-kworld-315u.o \
rc-kworld-pc150u.o \
rc-kworld-plus-tv-analog.o \
@@ -79,6 +80,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \
rc-npgtech.o \
rc-odroid.o \
rc-pctv-sedna.o \
+ rc-pine64.o \
rc-pinnacle-color.o \
rc-pinnacle-grey.o \
rc-pinnacle-pctv-hd.o \
diff --git a/drivers/media/rc/keymaps/rc-khamsin.c b/drivers/media/rc/keymaps/rc-khamsin.c
new file mode 100644
index 000000000000..0c98c2faacff
--- /dev/null
+++ b/drivers/media/rc/keymaps/rc-khamsin.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2020 Christian Hewitt
+
+#include <media/rc-map.h>
+#include <linux/module.h>
+
+/*
+ * KHAMSIN is an IR/Bluetooth RCU supplied with the SmartLabs
+ * SML-5442TW DVB-S/VOD box. The RCU has separate IR (TV) and
+ * BT (STB) modes. This keymap suppors the IR controls.
+ */
+
+static struct rc_map_table khamsin[] = {
+ { 0x70702, KEY_POWER},
+
+ { 0x70701, KEY_VIDEO}, // source
+
+ { 0x7076c, KEY_RED},
+ { 0x70714, KEY_GREEN},
+ { 0x70715, KEY_YELLOW},
+ { 0x70716, KEY_BLUE},
+
+ { 0x7071a, KEY_MENU},
+ { 0x7074f, KEY_EPG},
+
+ { 0x70760, KEY_UP },
+ { 0x70761, KEY_DOWN },
+ { 0x70765, KEY_LEFT },
+ { 0x70762, KEY_RIGHT },
+ { 0x70768, KEY_ENTER },
+
+ { 0x7072d, KEY_ESC }, // back
+
+ { 0x70707, KEY_VOLUMEUP },
+ { 0x7070b, KEY_VOLUMEDOWN },
+ { 0x7070f, KEY_MUTE },
+ { 0x70712, KEY_CHANNELUP },
+ { 0x70710, KEY_CHANNELDOWN },
+
+ { 0x70704, KEY_1 },
+ { 0x70705, KEY_2 },
+ { 0x70706, KEY_3 },
+ { 0x70708, KEY_4 },
+ { 0x70709, KEY_5 },
+ { 0x7070a, KEY_6 },
+ { 0x7070c, KEY_7 },
+ { 0x7070d, KEY_8 },
+ { 0x7070e, KEY_9 },
+ { 0x70711, KEY_0 },
+};
+
+static struct rc_map_list khamsin_map = {
+ .map = {
+ .scan = khamsin,
+ .size = ARRAY_SIZE(khamsin),
+ .rc_proto = RC_PROTO_NECX,
+ .name = RC_MAP_KHAMSIN,
+ }
+};
+
+static int __init init_rc_map_khamsin(void)
+{
+ return rc_map_register(&khamsin_map);
+}
+
+static void __exit exit_rc_map_khamsin(void)
+{
+ rc_map_unregister(&khamsin_map);
+}
+
+module_init(init_rc_map_khamsin)
+module_exit(exit_rc_map_khamsin)
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Christian Hewitt <christianshewitt@gmail.com>");
diff --git a/drivers/media/rc/keymaps/rc-pine64.c b/drivers/media/rc/keymaps/rc-pine64.c
new file mode 100644
index 000000000000..9b2bdbbce04e
--- /dev/null
+++ b/drivers/media/rc/keymaps/rc-pine64.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+// Keytable for the Pine64 IR Remote Controller
+// Copyright (c) 2017 Jonas Karlman
+
+#include <media/rc-map.h>
+#include <linux/module.h>
+
+static struct rc_map_table pine64[] = {
+ { 0x40404d, KEY_POWER },
+ { 0x40401f, KEY_WWW },
+ { 0x40400a, KEY_MUTE },
+
+ { 0x404017, KEY_VOLUMEDOWN },
+ { 0x404018, KEY_VOLUMEUP },
+
+ { 0x404010, KEY_LEFT },
+ { 0x404011, KEY_RIGHT },
+ { 0x40400b, KEY_UP },
+ { 0x40400e, KEY_DOWN },
+ { 0x40400d, KEY_OK },
+
+ { 0x40401d, KEY_MENU },
+ { 0x40401a, KEY_HOME },
+
+ { 0x404045, KEY_BACK },
+
+ { 0x404001, KEY_NUMERIC_1 },
+ { 0x404002, KEY_NUMERIC_2 },
+ { 0x404003, KEY_NUMERIC_3 },
+ { 0x404004, KEY_NUMERIC_4 },
+ { 0x404005, KEY_NUMERIC_5 },
+ { 0x404006, KEY_NUMERIC_6 },
+ { 0x404007, KEY_NUMERIC_7 },
+ { 0x404008, KEY_NUMERIC_8 },
+ { 0x404009, KEY_NUMERIC_9 },
+ { 0x40400c, KEY_BACKSPACE },
+ { 0x404000, KEY_NUMERIC_0 },
+ { 0x404047, KEY_EPG }, // mouse
+};
+
+static struct rc_map_list pine64_map = {
+ .map = {
+ .scan = pine64,
+ .size = ARRAY_SIZE(pine64),
+ .rc_proto = RC_PROTO_NECX,
+ .name = RC_MAP_PINE64,
+ }
+};
+
+static int __init init_rc_map_pine64(void)
+{
+ return rc_map_register(&pine64_map);
+}
+
+static void __exit exit_rc_map_pine64(void)
+{
+ rc_map_unregister(&pine64_map);
+}
+
+module_init(init_rc_map_pine64)
+module_exit(exit_rc_map_pine64)
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jonas Karlman");
diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c
index 220363b9a868..116daf90c858 100644
--- a/drivers/media/rc/lirc_dev.c
+++ b/drivers/media/rc/lirc_dev.c
@@ -263,7 +263,8 @@ static ssize_t lirc_transmit(struct file *file, const char __user *buf,
goto out_unlock;
}
- if (scan.flags || scan.keycode || scan.timestamp) {
+ if (scan.flags || scan.keycode || scan.timestamp ||
+ scan.rc_proto > RC_PROTO_MAX) {
ret = -EINVAL;
goto out_unlock;
}
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index ddee6ee37bab..8555c7798706 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -73,10 +73,6 @@
#define SUNXI_IR_BASE_CLK 8000000
/* Noise threshold in samples */
#define SUNXI_IR_RXNOISE 1
-/* Idle Threshold in samples */
-#define SUNXI_IR_RXIDLE 20
-/* Time after which device stops sending data in ms */
-#define SUNXI_IR_TIMEOUT 120
/**
* struct sunxi_ir_quirks - Differences between SoC variants.
@@ -137,6 +133,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
} else if (status & REG_RXSTA_RPE) {
ir_raw_event_set_idle(ir->rc, true);
ir_raw_event_handle(ir->rc);
+ } else {
+ ir_raw_event_handle(ir->rc);
}
spin_unlock(&ir->ir_lock);
@@ -144,6 +142,41 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
return IRQ_HANDLED;
}
+/* Convert idle threshold to usec */
+static unsigned int sunxi_ithr_to_usec(unsigned int base_clk, unsigned int ithr)
+{
+ return DIV_ROUND_CLOSEST(USEC_PER_SEC * (ithr + 1),
+ base_clk / (128 * 64));
+}
+
+/* Convert usec to idle threshold */
+static unsigned int sunxi_usec_to_ithr(unsigned int base_clk, unsigned int usec)
+{
+ /* make sure we don't end up with a timeout less than requested */
+ return DIV_ROUND_UP((base_clk / (128 * 64)) * usec, USEC_PER_SEC) - 1;
+}
+
+static int sunxi_ir_set_timeout(struct rc_dev *rc_dev, unsigned int timeout)
+{
+ struct sunxi_ir *ir = rc_dev->priv;
+ unsigned int base_clk = clk_get_rate(ir->clk);
+ unsigned long flags;
+
+ unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout);
+
+ dev_dbg(rc_dev->dev.parent, "setting idle threshold to %u\n", ithr);
+
+ spin_lock_irqsave(&ir->ir_lock, flags);
+ /* Set noise threshold and idle threshold */
+ writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) | REG_CIR_ITHR(ithr),
+ ir->base + SUNXI_IR_CIR_REG);
+ spin_unlock_irqrestore(&ir->ir_lock, flags);
+
+ rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr);
+
+ return 0;
+}
+
static int sunxi_ir_probe(struct platform_device *pdev)
{
int ret = 0;
@@ -240,9 +273,11 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
- /* Frequency after IR internal divider with sample period in ns */
+ /* Frequency after IR internal divider with sample period in us */
ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));
- ir->rc->timeout = MS_TO_US(SUNXI_IR_TIMEOUT);
+ ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0);
+ ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255);
+ ir->rc->s_timeout = sunxi_ir_set_timeout;
ir->rc->driver_name = SUNXI_IR_DEV;
ret = rc_register_device(ir->rc);
@@ -270,8 +305,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
/* Set noise threshold and idle threshold */
- writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
- ir->base + SUNXI_IR_CIR_REG);
+ sunxi_ir_set_timeout(ir->rc, IR_DEFAULT_TIMEOUT);
/* Invert Input Signal */
writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
diff --git a/drivers/media/test-drivers/vicodec/codec-fwht.c b/drivers/media/test-drivers/vicodec/codec-fwht.c
index 31faf319e508..1ce682e1b85c 100644
--- a/drivers/media/test-drivers/vicodec/codec-fwht.c
+++ b/drivers/media/test-drivers/vicodec/codec-fwht.c
@@ -11,6 +11,7 @@
#include <linux/string.h>
#include <linux/kernel.h>
+#include <linux/videodev2.h>
#include "codec-fwht.h"
#define OVERFLOW_BIT BIT(14)
@@ -920,7 +921,7 @@ bool fwht_decode_frame(struct fwht_cframe *cf, u32 hdr_flags,
if (!decode_plane(cf, &rlco, height, width, ref->luma, ref_stride,
ref->luma_alpha_step, dst->luma, dst_stride,
dst->luma_alpha_step,
- hdr_flags & FWHT_FL_LUMA_IS_UNCOMPRESSED,
+ hdr_flags & V4L2_FWHT_FL_LUMA_IS_UNCOMPRESSED,
end_of_rlco_buf))
return false;
@@ -928,21 +929,21 @@ bool fwht_decode_frame(struct fwht_cframe *cf, u32 hdr_flags,
u32 h = height;
u32 w = width;
- if (!(hdr_flags & FWHT_FL_CHROMA_FULL_HEIGHT))
+ if (!(hdr_flags & V4L2_FWHT_FL_CHROMA_FULL_HEIGHT))
h /= 2;
- if (!(hdr_flags & FWHT_FL_CHROMA_FULL_WIDTH))
+ if (!(hdr_flags & V4L2_FWHT_FL_CHROMA_FULL_WIDTH))
w /= 2;
if (!decode_plane(cf, &rlco, h, w, ref->cb, ref_chroma_stride,
ref->chroma_step, dst->cb, dst_chroma_stride,
dst->chroma_step,
- hdr_flags & FWHT_FL_CB_IS_UNCOMPRESSED,
+ hdr_flags & V4L2_FWHT_FL_CB_IS_UNCOMPRESSED,
end_of_rlco_buf))
return false;
if (!decode_plane(cf, &rlco, h, w, ref->cr, ref_chroma_stride,
ref->chroma_step, dst->cr, dst_chroma_stride,
dst->chroma_step,
- hdr_flags & FWHT_FL_CR_IS_UNCOMPRESSED,
+ hdr_flags & V4L2_FWHT_FL_CR_IS_UNCOMPRESSED,
end_of_rlco_buf))
return false;
}
@@ -951,7 +952,7 @@ bool fwht_decode_frame(struct fwht_cframe *cf, u32 hdr_flags,
if (!decode_plane(cf, &rlco, height, width, ref->alpha, ref_stride,
ref->luma_alpha_step, dst->alpha, dst_stride,
dst->luma_alpha_step,
- hdr_flags & FWHT_FL_ALPHA_IS_UNCOMPRESSED,
+ hdr_flags & V4L2_FWHT_FL_ALPHA_IS_UNCOMPRESSED,
end_of_rlco_buf))
return false;
return true;
diff --git a/drivers/media/test-drivers/vicodec/codec-fwht.h b/drivers/media/test-drivers/vicodec/codec-fwht.h
index b6fec2b1cbca..0eab24020e9e 100644
--- a/drivers/media/test-drivers/vicodec/codec-fwht.h
+++ b/drivers/media/test-drivers/vicodec/codec-fwht.h
@@ -56,38 +56,6 @@
#define FWHT_MAGIC1 0x4f4f4f4f
#define FWHT_MAGIC2 0xffffffff
-#define FWHT_VERSION 3
-
-/* Set if this is an interlaced format */
-#define FWHT_FL_IS_INTERLACED BIT(0)
-/* Set if this is a bottom-first (NTSC) interlaced format */
-#define FWHT_FL_IS_BOTTOM_FIRST BIT(1)
-/* Set if each 'frame' contains just one field */
-#define FWHT_FL_IS_ALTERNATE BIT(2)
-/*
- * If FWHT_FL_IS_ALTERNATE was set, then this is set if this
- * 'frame' is the bottom field, else it is the top field.
- */
-#define FWHT_FL_IS_BOTTOM_FIELD BIT(3)
-/* Set if this frame is uncompressed */
-#define FWHT_FL_LUMA_IS_UNCOMPRESSED BIT(4)
-#define FWHT_FL_CB_IS_UNCOMPRESSED BIT(5)
-#define FWHT_FL_CR_IS_UNCOMPRESSED BIT(6)
-#define FWHT_FL_CHROMA_FULL_HEIGHT BIT(7)
-#define FWHT_FL_CHROMA_FULL_WIDTH BIT(8)
-#define FWHT_FL_ALPHA_IS_UNCOMPRESSED BIT(9)
-#define FWHT_FL_I_FRAME BIT(10)
-
-/* A 4-values flag - the number of components - 1 */
-#define FWHT_FL_COMPONENTS_NUM_MSK GENMASK(18, 16)
-#define FWHT_FL_COMPONENTS_NUM_OFFSET 16
-
-#define FWHT_FL_PIXENC_MSK GENMASK(20, 19)
-#define FWHT_FL_PIXENC_OFFSET 19
-#define FWHT_FL_PIXENC_YUV (1 << FWHT_FL_PIXENC_OFFSET)
-#define FWHT_FL_PIXENC_RGB (2 << FWHT_FL_PIXENC_OFFSET)
-#define FWHT_FL_PIXENC_HSV (3 << FWHT_FL_PIXENC_OFFSET)
-
/*
* A macro to calculate the needed padding in order to make sure
* both luma and chroma components resolutions are rounded up to
diff --git a/drivers/media/test-drivers/vicodec/codec-v4l2-fwht.c b/drivers/media/test-drivers/vicodec/codec-v4l2-fwht.c
index b6e39fbd8ad5..0c83678fcdad 100644
--- a/drivers/media/test-drivers/vicodec/codec-v4l2-fwht.c
+++ b/drivers/media/test-drivers/vicodec/codec-v4l2-fwht.c
@@ -11,34 +11,34 @@
#include "codec-v4l2-fwht.h"
static const struct v4l2_fwht_pixfmt_info v4l2_fwht_pixfmts[] = {
- { V4L2_PIX_FMT_YUV420, 1, 3, 2, 1, 1, 2, 2, 3, 3, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_YVU420, 1, 3, 2, 1, 1, 2, 2, 3, 3, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_YUV422P, 1, 2, 1, 1, 1, 2, 1, 3, 3, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_NV12, 1, 3, 2, 1, 2, 2, 2, 3, 2, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_NV21, 1, 3, 2, 1, 2, 2, 2, 3, 2, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_NV16, 1, 2, 1, 1, 2, 2, 1, 3, 2, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_NV61, 1, 2, 1, 1, 2, 2, 1, 3, 2, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_NV24, 1, 3, 1, 1, 2, 1, 1, 3, 2, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_NV42, 1, 3, 1, 1, 2, 1, 1, 3, 2, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_YUYV, 2, 2, 1, 2, 4, 2, 1, 3, 1, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_YVYU, 2, 2, 1, 2, 4, 2, 1, 3, 1, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_UYVY, 2, 2, 1, 2, 4, 2, 1, 3, 1, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_VYUY, 2, 2, 1, 2, 4, 2, 1, 3, 1, FWHT_FL_PIXENC_YUV},
- { V4L2_PIX_FMT_BGR24, 3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_RGB24, 3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_HSV24, 3, 3, 1, 3, 3, 1, 1, 3, 1, FWHT_FL_PIXENC_HSV},
- { V4L2_PIX_FMT_BGR32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_XBGR32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_ABGR32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_RGB32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_XRGB32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_ARGB32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_BGRX32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_BGRA32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_RGBX32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_RGBA32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_RGB},
- { V4L2_PIX_FMT_HSV32, 4, 4, 1, 4, 4, 1, 1, 4, 1, FWHT_FL_PIXENC_HSV},
- { V4L2_PIX_FMT_GREY, 1, 1, 1, 1, 0, 1, 1, 1, 1, FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_YUV420, 1, 3, 2, 1, 1, 2, 2, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_YVU420, 1, 3, 2, 1, 1, 2, 2, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_YUV422P, 1, 2, 1, 1, 1, 2, 1, 3, 3, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_NV12, 1, 3, 2, 1, 2, 2, 2, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_NV21, 1, 3, 2, 1, 2, 2, 2, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_NV16, 1, 2, 1, 1, 2, 2, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_NV61, 1, 2, 1, 1, 2, 2, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_NV24, 1, 3, 1, 1, 2, 1, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_NV42, 1, 3, 1, 1, 2, 1, 1, 3, 2, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_YUYV, 2, 2, 1, 2, 4, 2, 1, 3, 1, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_YVYU, 2, 2, 1, 2, 4, 2, 1, 3, 1, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_UYVY, 2, 2, 1, 2, 4, 2, 1, 3, 1, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_VYUY, 2, 2, 1, 2, 4, 2, 1, 3, 1, V4L2_FWHT_FL_PIXENC_YUV},
+ { V4L2_PIX_FMT_BGR24, 3, 3, 1, 3, 3, 1, 1, 3, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_RGB24, 3, 3, 1, 3, 3, 1, 1, 3, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_HSV24, 3, 3, 1, 3, 3, 1, 1, 3, 1, V4L2_FWHT_FL_PIXENC_HSV},
+ { V4L2_PIX_FMT_BGR32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_XBGR32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_ABGR32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_RGB32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_XRGB32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_ARGB32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_BGRX32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_BGRA32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_RGBX32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_RGBA32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_RGB},
+ { V4L2_PIX_FMT_HSV32, 4, 4, 1, 4, 4, 1, 1, 4, 1, V4L2_FWHT_FL_PIXENC_HSV},
+ { V4L2_PIX_FMT_GREY, 1, 1, 1, 1, 0, 1, 1, 1, 1, V4L2_FWHT_FL_PIXENC_RGB},
};
bool v4l2_fwht_validate_fmt(const struct v4l2_fwht_pixfmt_info *info,
@@ -251,25 +251,25 @@ int v4l2_fwht_encode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out)
p_hdr = (struct fwht_cframe_hdr *)p_out;
p_hdr->magic1 = FWHT_MAGIC1;
p_hdr->magic2 = FWHT_MAGIC2;
- p_hdr->version = htonl(FWHT_VERSION);
+ p_hdr->version = htonl(V4L2_FWHT_VERSION);
p_hdr->width = htonl(state->visible_width);
p_hdr->height = htonl(state->visible_height);
- flags |= (info->components_num - 1) << FWHT_FL_COMPONENTS_NUM_OFFSET;
+ flags |= (info->components_num - 1) << V4L2_FWHT_FL_COMPONENTS_NUM_OFFSET;
flags |= info->pixenc;
if (encoding & FWHT_LUMA_UNENCODED)
- flags |= FWHT_FL_LUMA_IS_UNCOMPRESSED;
+ flags |= V4L2_FWHT_FL_LUMA_IS_UNCOMPRESSED;
if (encoding & FWHT_CB_UNENCODED)
- flags |= FWHT_FL_CB_IS_UNCOMPRESSED;
+ flags |= V4L2_FWHT_FL_CB_IS_UNCOMPRESSED;
if (encoding & FWHT_CR_UNENCODED)
- flags |= FWHT_FL_CR_IS_UNCOMPRESSED;
+ flags |= V4L2_FWHT_FL_CR_IS_UNCOMPRESSED;
if (encoding & FWHT_ALPHA_UNENCODED)
- flags |= FWHT_FL_ALPHA_IS_UNCOMPRESSED;
+ flags |= V4L2_FWHT_FL_ALPHA_IS_UNCOMPRESSED;
if (!(encoding & FWHT_FRAME_PCODED))
- flags |= FWHT_FL_I_FRAME;
+ flags |= V4L2_FWHT_FL_I_FRAME;
if (rf.height_div == 1)
- flags |= FWHT_FL_CHROMA_FULL_HEIGHT;
+ flags |= V4L2_FWHT_FL_CHROMA_FULL_HEIGHT;
if (rf.width_div == 1)
- flags |= FWHT_FL_CHROMA_FULL_WIDTH;
+ flags |= V4L2_FWHT_FL_CHROMA_FULL_WIDTH;
p_hdr->flags = htonl(flags);
p_hdr->colorspace = htonl(state->colorspace);
p_hdr->xfer_func = htonl(state->xfer_func);
@@ -299,9 +299,9 @@ int v4l2_fwht_decode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out)
info = state->info;
version = ntohl(state->header.version);
- if (!version || version > FWHT_VERSION) {
+ if (!version || version > V4L2_FWHT_VERSION) {
pr_err("version %d is not supported, current version is %d\n",
- version, FWHT_VERSION);
+ version, V4L2_FWHT_VERSION);
return -EINVAL;
}
@@ -317,10 +317,10 @@ int v4l2_fwht_decode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out)
flags = ntohl(state->header.flags);
if (version >= 2) {
- if ((flags & FWHT_FL_PIXENC_MSK) != info->pixenc)
+ if ((flags & V4L2_FWHT_FL_PIXENC_MSK) != info->pixenc)
return -EINVAL;
- components_num = 1 + ((flags & FWHT_FL_COMPONENTS_NUM_MSK) >>
- FWHT_FL_COMPONENTS_NUM_OFFSET);
+ components_num = 1 + ((flags & V4L2_FWHT_FL_COMPONENTS_NUM_MSK) >>
+ V4L2_FWHT_FL_COMPONENTS_NUM_OFFSET);
}
if (components_num != info->components_num)
@@ -333,8 +333,8 @@ int v4l2_fwht_decode(struct v4l2_fwht_state *state, u8 *p_in, u8 *p_out)
cf.rlc_data = (__be16 *)p_in;
cf.size = ntohl(state->header.size);
- hdr_width_div = (flags & FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
- hdr_height_div = (flags & FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
+ hdr_width_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
+ hdr_height_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
if (hdr_width_div != info->width_div ||
hdr_height_div != info->height_div)
return -EINVAL;
diff --git a/drivers/media/test-drivers/vicodec/vicodec-core.c b/drivers/media/test-drivers/vicodec/vicodec-core.c
index 0e115683f8da..025f3ff77302 100644
--- a/drivers/media/test-drivers/vicodec/vicodec-core.c
+++ b/drivers/media/test-drivers/vicodec/vicodec-core.c
@@ -200,14 +200,14 @@ static void copy_cap_to_ref(const u8 *cap, const struct v4l2_fwht_pixfmt_info *i
static bool validate_by_version(unsigned int flags, unsigned int version)
{
- if (!version || version > FWHT_VERSION)
+ if (!version || version > V4L2_FWHT_VERSION)
return false;
if (version >= 2) {
unsigned int components_num = 1 +
- ((flags & FWHT_FL_COMPONENTS_NUM_MSK) >>
- FWHT_FL_COMPONENTS_NUM_OFFSET);
- unsigned int pixenc = flags & FWHT_FL_PIXENC_MSK;
+ ((flags & V4L2_FWHT_FL_COMPONENTS_NUM_MSK) >>
+ V4L2_FWHT_FL_COMPONENTS_NUM_OFFSET);
+ unsigned int pixenc = flags & V4L2_FWHT_FL_PIXENC_MSK;
if (components_num == 0 || components_num > 4 || !pixenc)
return false;
@@ -219,18 +219,18 @@ static bool validate_stateless_params_flags(const struct v4l2_ctrl_fwht_params *
const struct v4l2_fwht_pixfmt_info *cur_info)
{
unsigned int width_div =
- (params->flags & FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
+ (params->flags & V4L2_FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
unsigned int height_div =
- (params->flags & FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
+ (params->flags & V4L2_FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
unsigned int components_num = 3;
unsigned int pixenc = 0;
if (params->version < 3)
return false;
- components_num = 1 + ((params->flags & FWHT_FL_COMPONENTS_NUM_MSK) >>
- FWHT_FL_COMPONENTS_NUM_OFFSET);
- pixenc = (params->flags & FWHT_FL_PIXENC_MSK);
+ components_num = 1 + ((params->flags & V4L2_FWHT_FL_COMPONENTS_NUM_MSK) >>
+ V4L2_FWHT_FL_COMPONENTS_NUM_OFFSET);
+ pixenc = (params->flags & V4L2_FWHT_FL_PIXENC_MSK);
if (v4l2_fwht_validate_fmt(cur_info, width_div, height_div,
components_num, pixenc))
return true;
@@ -278,7 +278,7 @@ static int device_process(struct vicodec_ctx *ctx,
* set the reference buffer from the reference timestamp
* only if this is a P-frame
*/
- if (!(ntohl(ctx->state.header.flags) & FWHT_FL_I_FRAME)) {
+ if (!(ntohl(ctx->state.header.flags) & V4L2_FWHT_FL_I_FRAME)) {
struct vb2_buffer *ref_vb2_buf;
int ref_buf_idx;
struct vb2_queue *vq_cap =
@@ -331,7 +331,7 @@ static int device_process(struct vicodec_ctx *ctx,
copy_cap_to_ref(p_dst, ctx->state.info, &ctx->state);
vb2_set_plane_payload(&dst_vb->vb2_buf, 0, q_dst->sizeimage);
- if (ntohl(ctx->state.header.flags) & FWHT_FL_I_FRAME)
+ if (ntohl(ctx->state.header.flags) & V4L2_FWHT_FL_I_FRAME)
dst_vb->flags |= V4L2_BUF_FLAG_KEYFRAME;
else
dst_vb->flags |= V4L2_BUF_FLAG_PFRAME;
@@ -480,16 +480,16 @@ static const struct v4l2_fwht_pixfmt_info *
info_from_header(const struct fwht_cframe_hdr *p_hdr)
{
unsigned int flags = ntohl(p_hdr->flags);
- unsigned int width_div = (flags & FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
- unsigned int height_div = (flags & FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
+ unsigned int width_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
+ unsigned int height_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
unsigned int components_num = 3;
unsigned int pixenc = 0;
unsigned int version = ntohl(p_hdr->version);
if (version >= 2) {
- components_num = 1 + ((flags & FWHT_FL_COMPONENTS_NUM_MSK) >>
- FWHT_FL_COMPONENTS_NUM_OFFSET);
- pixenc = (flags & FWHT_FL_PIXENC_MSK);
+ components_num = 1 + ((flags & V4L2_FWHT_FL_COMPONENTS_NUM_MSK) >>
+ V4L2_FWHT_FL_COMPONENTS_NUM_OFFSET);
+ pixenc = (flags & V4L2_FWHT_FL_PIXENC_MSK);
}
return v4l2_fwht_find_nth_fmt(width_div, height_div,
components_num, pixenc, 0);
@@ -522,8 +522,8 @@ static void update_capture_data_from_header(struct vicodec_ctx *ctx)
const struct fwht_cframe_hdr *p_hdr = &ctx->state.header;
const struct v4l2_fwht_pixfmt_info *info = info_from_header(p_hdr);
unsigned int flags = ntohl(p_hdr->flags);
- unsigned int hdr_width_div = (flags & FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
- unsigned int hdr_height_div = (flags & FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
+ unsigned int hdr_width_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
+ unsigned int hdr_height_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
/*
* This function should not be used by a stateless codec since
@@ -657,8 +657,8 @@ restart:
if (!is_header_valid(&ctx->state.header) && ctx->comp_has_frame)
return 1;
flags = ntohl(ctx->state.header.flags);
- hdr_width_div = (flags & FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
- hdr_height_div = (flags & FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
+ hdr_width_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_WIDTH) ? 1 : 2;
+ hdr_height_div = (flags & V4L2_FWHT_FL_CHROMA_FULL_HEIGHT) ? 1 : 2;
if (ntohl(ctx->state.header.width) != q_dst->visible_width ||
ntohl(ctx->state.header.height) != q_dst->visible_height ||
@@ -1746,7 +1746,7 @@ static int vicodec_try_ctrl(struct v4l2_ctrl *ctrl)
V4L2_BUF_TYPE_VIDEO_CAPTURE);
switch (ctrl->id) {
- case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS:
+ case V4L2_CID_STATELESS_FWHT_PARAMS:
if (!q_dst->info)
return -EINVAL;
params = ctrl->p_new.p_fwht_params;
@@ -1799,7 +1799,7 @@ static int vicodec_s_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_FWHT_P_FRAME_QP:
ctx->state.p_frame_qp = ctrl->val;
return 0;
- case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS:
+ case V4L2_CID_STATELESS_FWHT_PARAMS:
params = ctrl->p_new.p_fwht_params;
update_header_from_stateless_params(ctx, params);
ctx->state.ref_frame_ts = params->backward_ref_ts;
@@ -1815,7 +1815,7 @@ static const struct v4l2_ctrl_ops vicodec_ctrl_ops = {
static const struct v4l2_ctrl_config vicodec_ctrl_stateless_state = {
.ops = &vicodec_ctrl_ops,
- .id = V4L2_CID_MPEG_VIDEO_FWHT_PARAMS,
+ .id = V4L2_CID_STATELESS_FWHT_PARAMS,
.elem_size = sizeof(struct v4l2_ctrl_fwht_params),
};
diff --git a/drivers/media/test-drivers/vim2m.c b/drivers/media/test-drivers/vim2m.c
index a776bb8e0e09..331a9053a0ed 100644
--- a/drivers/media/test-drivers/vim2m.c
+++ b/drivers/media/test-drivers/vim2m.c
@@ -1325,12 +1325,6 @@ static int vim2m_probe(struct platform_device *pdev)
vfd->lock = &dev->dev_mutex;
vfd->v4l2_dev = &dev->v4l2_dev;
- ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
- if (ret) {
- v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
- goto error_v4l2;
- }
-
video_set_drvdata(vfd, dev);
v4l2_info(&dev->v4l2_dev,
"Device registered as /dev/video%d\n", vfd->num);
@@ -1345,6 +1339,12 @@ static int vim2m_probe(struct platform_device *pdev)
goto error_dev;
}
+ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
+ if (ret) {
+ v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
+ goto error_m2m;
+ }
+
#ifdef CONFIG_MEDIA_CONTROLLER
dev->mdev.dev = &pdev->dev;
strscpy(dev->mdev.model, "vim2m", sizeof(dev->mdev.model));
@@ -1358,7 +1358,7 @@ static int vim2m_probe(struct platform_device *pdev)
MEDIA_ENT_F_PROC_VIDEO_SCALER);
if (ret) {
v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem media controller\n");
- goto error_dev;
+ goto error_v4l2;
}
ret = media_device_register(&dev->mdev);
@@ -1373,11 +1373,13 @@ static int vim2m_probe(struct platform_device *pdev)
error_m2m_mc:
v4l2_m2m_unregister_media_controller(dev->m2m_dev);
#endif
-error_dev:
+error_v4l2:
video_unregister_device(&dev->vfd);
/* vim2m_device_release called by video_unregister_device to release various objects */
return ret;
-error_v4l2:
+error_m2m:
+ v4l2_m2m_release(dev->m2m_dev);
+error_dev:
v4l2_device_unregister(&dev->v4l2_dev);
error_free:
kfree(dev);
diff --git a/drivers/media/test-drivers/vivid/vivid-core.c b/drivers/media/test-drivers/vivid/vivid-core.c
index aa8d350fd682..0dc65ef3aa14 100644
--- a/drivers/media/test-drivers/vivid/vivid-core.c
+++ b/drivers/media/test-drivers/vivid/vivid-core.c
@@ -547,11 +547,13 @@ static int vivid_s_fmt_cap_mplane(struct file *file, void *priv,
return vidioc_s_fmt_vid_cap_mplane(file, priv, f);
}
-static bool vivid_is_in_use(struct video_device *vdev)
+static bool vivid_is_in_use(bool valid, struct video_device *vdev)
{
unsigned long flags;
bool res;
+ if (!valid)
+ return false;
spin_lock_irqsave(&vdev->fh_lock, flags);
res = !list_empty(&vdev->fh_list);
spin_unlock_irqrestore(&vdev->fh_lock, flags);
@@ -560,20 +562,46 @@ static bool vivid_is_in_use(struct video_device *vdev)
static bool vivid_is_last_user(struct vivid_dev *dev)
{
- unsigned uses = vivid_is_in_use(&dev->vid_cap_dev) +
- vivid_is_in_use(&dev->vid_out_dev) +
- vivid_is_in_use(&dev->vbi_cap_dev) +
- vivid_is_in_use(&dev->vbi_out_dev) +
- vivid_is_in_use(&dev->sdr_cap_dev) +
- vivid_is_in_use(&dev->radio_rx_dev) +
- vivid_is_in_use(&dev->radio_tx_dev) +
- vivid_is_in_use(&dev->meta_cap_dev) +
- vivid_is_in_use(&dev->meta_out_dev) +
- vivid_is_in_use(&dev->touch_cap_dev);
+ unsigned int uses =
+ vivid_is_in_use(dev->has_vid_cap, &dev->vid_cap_dev) +
+ vivid_is_in_use(dev->has_vid_out, &dev->vid_out_dev) +
+ vivid_is_in_use(dev->has_vbi_cap, &dev->vbi_cap_dev) +
+ vivid_is_in_use(dev->has_vbi_out, &dev->vbi_out_dev) +
+ vivid_is_in_use(dev->has_radio_rx, &dev->radio_rx_dev) +
+ vivid_is_in_use(dev->has_radio_tx, &dev->radio_tx_dev) +
+ vivid_is_in_use(dev->has_sdr_cap, &dev->sdr_cap_dev) +
+ vivid_is_in_use(dev->has_meta_cap, &dev->meta_cap_dev) +
+ vivid_is_in_use(dev->has_meta_out, &dev->meta_out_dev) +
+ vivid_is_in_use(dev->has_touch_cap, &dev->touch_cap_dev);
return uses == 1;
}
+static void vivid_reconnect(struct vivid_dev *dev)
+{
+ if (dev->has_vid_cap)
+ set_bit(V4L2_FL_REGISTERED, &dev->vid_cap_dev.flags);
+ if (dev->has_vid_out)
+ set_bit(V4L2_FL_REGISTERED, &dev->vid_out_dev.flags);
+ if (dev->has_vbi_cap)
+ set_bit(V4L2_FL_REGISTERED, &dev->vbi_cap_dev.flags);
+ if (dev->has_vbi_out)
+ set_bit(V4L2_FL_REGISTERED, &dev->vbi_out_dev.flags);
+ if (dev->has_radio_rx)
+ set_bit(V4L2_FL_REGISTERED, &dev->radio_rx_dev.flags);
+ if (dev->has_radio_tx)
+ set_bit(V4L2_FL_REGISTERED, &dev->radio_tx_dev.flags);
+ if (dev->has_sdr_cap)
+ set_bit(V4L2_FL_REGISTERED, &dev->sdr_cap_dev.flags);
+ if (dev->has_meta_cap)
+ set_bit(V4L2_FL_REGISTERED, &dev->meta_cap_dev.flags);
+ if (dev->has_meta_out)
+ set_bit(V4L2_FL_REGISTERED, &dev->meta_out_dev.flags);
+ if (dev->has_touch_cap)
+ set_bit(V4L2_FL_REGISTERED, &dev->touch_cap_dev.flags);
+ dev->disconnect_error = false;
+}
+
static int vivid_fop_release(struct file *file)
{
struct vivid_dev *dev = video_drvdata(file);
@@ -581,23 +609,15 @@ static int vivid_fop_release(struct file *file)
mutex_lock(&dev->mutex);
if (!no_error_inj && v4l2_fh_is_singular_file(file) &&
- !video_is_registered(vdev) && vivid_is_last_user(dev)) {
+ dev->disconnect_error && !video_is_registered(vdev) &&
+ vivid_is_last_user(dev)) {
/*
* I am the last user of this driver, and a disconnect
* was forced (since this video_device is unregistered),
* so re-register all video_device's again.
*/
v4l2_info(&dev->v4l2_dev, "reconnect\n");
- set_bit(V4L2_FL_REGISTERED, &dev->vid_cap_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->vid_out_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->vbi_cap_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->vbi_out_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->sdr_cap_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->radio_rx_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->radio_tx_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->meta_cap_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->meta_out_dev.flags);
- set_bit(V4L2_FL_REGISTERED, &dev->touch_cap_dev.flags);
+ vivid_reconnect(dev);
}
mutex_unlock(&dev->mutex);
if (file->private_data == dev->overlay_cap_owner)
@@ -1968,6 +1988,8 @@ static int vivid_remove(struct platform_device *pdev)
if (!dev)
continue;
+ if (dev->disconnect_error)
+ vivid_reconnect(dev);
#ifdef CONFIG_MEDIA_CONTROLLER
media_device_unregister(&dev->mdev);
#endif
diff --git a/drivers/media/test-drivers/vivid/vivid-core.h b/drivers/media/test-drivers/vivid/vivid-core.h
index 99e69b8f770f..9c2d1470b597 100644
--- a/drivers/media/test-drivers/vivid/vivid-core.h
+++ b/drivers/media/test-drivers/vivid/vivid-core.h
@@ -303,6 +303,7 @@ struct vivid_dev {
struct fb_fix_screeninfo fb_fix;
/* Error injection */
+ bool disconnect_error;
bool queue_setup_error;
bool buf_prepare_error;
bool start_streaming_error;
diff --git a/drivers/media/test-drivers/vivid/vivid-ctrls.c b/drivers/media/test-drivers/vivid/vivid-ctrls.c
index 334130568dcb..11e3b5617f52 100644
--- a/drivers/media/test-drivers/vivid/vivid-ctrls.c
+++ b/drivers/media/test-drivers/vivid/vivid-ctrls.c
@@ -107,14 +107,27 @@ static int vivid_user_gen_s_ctrl(struct v4l2_ctrl *ctrl)
switch (ctrl->id) {
case VIVID_CID_DISCONNECT:
v4l2_info(&dev->v4l2_dev, "disconnect\n");
- clear_bit(V4L2_FL_REGISTERED, &dev->vid_cap_dev.flags);
- clear_bit(V4L2_FL_REGISTERED, &dev->vid_out_dev.flags);
- clear_bit(V4L2_FL_REGISTERED, &dev->vbi_cap_dev.flags);
- clear_bit(V4L2_FL_REGISTERED, &dev->vbi_out_dev.flags);
- clear_bit(V4L2_FL_REGISTERED, &dev->sdr_cap_dev.flags);
- clear_bit(V4L2_FL_REGISTERED, &dev->radio_rx_dev.flags);
- clear_bit(V4L2_FL_REGISTERED, &dev->radio_tx_dev.flags);
- clear_bit(V4L2_FL_REGISTERED, &dev->meta_cap_dev.flags);
+ dev->disconnect_error = true;
+ if (dev->has_vid_cap)
+ clear_bit(V4L2_FL_REGISTERED, &dev->vid_cap_dev.flags);
+ if (dev->has_vid_out)
+ clear_bit(V4L2_FL_REGISTERED, &dev->vid_out_dev.flags);
+ if (dev->has_vbi_cap)
+ clear_bit(V4L2_FL_REGISTERED, &dev->vbi_cap_dev.flags);
+ if (dev->has_vbi_out)
+ clear_bit(V4L2_FL_REGISTERED, &dev->vbi_out_dev.flags);
+ if (dev->has_radio_rx)
+ clear_bit(V4L2_FL_REGISTERED, &dev->radio_rx_dev.flags);
+ if (dev->has_radio_tx)
+ clear_bit(V4L2_FL_REGISTERED, &dev->radio_tx_dev.flags);
+ if (dev->has_sdr_cap)
+ clear_bit(V4L2_FL_REGISTERED, &dev->sdr_cap_dev.flags);
+ if (dev->has_meta_cap)
+ clear_bit(V4L2_FL_REGISTERED, &dev->meta_cap_dev.flags);
+ if (dev->has_meta_out)
+ clear_bit(V4L2_FL_REGISTERED, &dev->meta_out_dev.flags);
+ if (dev->has_touch_cap)
+ clear_bit(V4L2_FL_REGISTERED, &dev->touch_cap_dev.flags);
break;
case VIVID_CID_BUTTON:
dev->button_pressed = 30;
diff --git a/drivers/media/test-drivers/vivid/vivid-kthread-cap.c b/drivers/media/test-drivers/vivid/vivid-kthread-cap.c
index 01a9d671b947..67fb3c00f9ad 100644
--- a/drivers/media/test-drivers/vivid/vivid-kthread-cap.c
+++ b/drivers/media/test-drivers/vivid/vivid-kthread-cap.c
@@ -819,7 +819,7 @@ static int vivid_thread_vid_cap(void *data)
break;
if (!mutex_trylock(&dev->mutex)) {
- schedule_timeout_uninterruptible(1);
+ schedule();
continue;
}
@@ -888,7 +888,9 @@ static int vivid_thread_vid_cap(void *data)
next_jiffies_since_start = jiffies_since_start;
wait_jiffies = next_jiffies_since_start - jiffies_since_start;
- schedule_timeout_interruptible(wait_jiffies ? wait_jiffies : 1);
+ while (jiffies - cur_jiffies < wait_jiffies &&
+ !kthread_should_stop())
+ schedule();
}
dprintk(dev, 1, "Video Capture Thread End\n");
return 0;
diff --git a/drivers/media/test-drivers/vivid/vivid-kthread-out.c b/drivers/media/test-drivers/vivid/vivid-kthread-out.c
index 6780687978f9..79c57d14ac4e 100644
--- a/drivers/media/test-drivers/vivid/vivid-kthread-out.c
+++ b/drivers/media/test-drivers/vivid/vivid-kthread-out.c
@@ -167,7 +167,7 @@ static int vivid_thread_vid_out(void *data)
break;
if (!mutex_trylock(&dev->mutex)) {
- schedule_timeout_uninterruptible(1);
+ schedule();
continue;
}
@@ -233,7 +233,9 @@ static int vivid_thread_vid_out(void *data)
next_jiffies_since_start = jiffies_since_start;
wait_jiffies = next_jiffies_since_start - jiffies_since_start;
- schedule_timeout_interruptible(wait_jiffies ? wait_jiffies : 1);
+ while (jiffies - cur_jiffies < wait_jiffies &&
+ !kthread_should_stop())
+ schedule();
}
dprintk(dev, 1, "Video Output Thread End\n");
return 0;
diff --git a/drivers/media/test-drivers/vivid/vivid-kthread-touch.c b/drivers/media/test-drivers/vivid/vivid-kthread-touch.c
index 674507b5ccb5..38fdfee79498 100644
--- a/drivers/media/test-drivers/vivid/vivid-kthread-touch.c
+++ b/drivers/media/test-drivers/vivid/vivid-kthread-touch.c
@@ -69,7 +69,7 @@ static int vivid_thread_touch_cap(void *data)
break;
if (!mutex_trylock(&dev->mutex)) {
- schedule_timeout_uninterruptible(1);
+ schedule();
continue;
}
cur_jiffies = jiffies;
@@ -128,7 +128,9 @@ static int vivid_thread_touch_cap(void *data)
next_jiffies_since_start = jiffies_since_start;
wait_jiffies = next_jiffies_since_start - jiffies_since_start;
- schedule_timeout_interruptible(wait_jiffies ? wait_jiffies : 1);
+ while (jiffies - cur_jiffies < wait_jiffies &&
+ !kthread_should_stop())
+ schedule();
}
dprintk(dev, 1, "Touch Capture Thread End\n");
return 0;
diff --git a/drivers/media/test-drivers/vivid/vivid-sdr-cap.c b/drivers/media/test-drivers/vivid/vivid-sdr-cap.c
index 2b7522e16efc..a1e52708b7ca 100644
--- a/drivers/media/test-drivers/vivid/vivid-sdr-cap.c
+++ b/drivers/media/test-drivers/vivid/vivid-sdr-cap.c
@@ -142,7 +142,7 @@ static int vivid_thread_sdr_cap(void *data)
break;
if (!mutex_trylock(&dev->mutex)) {
- schedule_timeout_uninterruptible(1);
+ schedule();
continue;
}
@@ -201,7 +201,9 @@ static int vivid_thread_sdr_cap(void *data)
next_jiffies_since_start = jiffies_since_start;
wait_jiffies = next_jiffies_since_start - jiffies_since_start;
- schedule_timeout_interruptible(wait_jiffies ? wait_jiffies : 1);
+ while (jiffies - cur_jiffies < wait_jiffies &&
+ !kthread_should_stop())
+ schedule();
}
dprintk(dev, 1, "SDR Capture Thread End\n");
return 0;
diff --git a/drivers/media/test-drivers/vivid/vivid-vid-cap.c b/drivers/media/test-drivers/vivid/vivid-vid-cap.c
index eadf28ab1e39..b9caa4b26209 100644
--- a/drivers/media/test-drivers/vivid/vivid-vid-cap.c
+++ b/drivers/media/test-drivers/vivid/vivid-vid-cap.c
@@ -1107,11 +1107,9 @@ int vidioc_g_fmt_vid_overlay(struct file *file, void *priv,
((compose->width + 7) / 8) * compose->height))
return -EFAULT;
}
- if (clipcount && win->clips) {
- if (copy_to_user(win->clips, dev->clips_cap,
- clipcount * sizeof(dev->clips_cap[0])))
- return -EFAULT;
- }
+ if (clipcount && win->clips)
+ memcpy(win->clips, dev->clips_cap,
+ clipcount * sizeof(dev->clips_cap[0]));
return 0;
}
@@ -1141,9 +1139,8 @@ int vidioc_try_fmt_vid_overlay(struct file *file, void *priv,
if (win->clipcount > MAX_CLIPS)
win->clipcount = MAX_CLIPS;
if (win->clipcount) {
- if (copy_from_user(dev->try_clips_cap, win->clips,
- win->clipcount * sizeof(dev->clips_cap[0])))
- return -EFAULT;
+ memcpy(dev->try_clips_cap, win->clips,
+ win->clipcount * sizeof(dev->clips_cap[0]));
for (i = 0; i < win->clipcount; i++) {
struct v4l2_rect *r = &dev->try_clips_cap[i].c;
@@ -1166,9 +1163,8 @@ int vidioc_try_fmt_vid_overlay(struct file *file, void *priv,
return -EINVAL;
}
}
- if (copy_to_user(win->clips, dev->try_clips_cap,
- win->clipcount * sizeof(dev->clips_cap[0])))
- return -EFAULT;
+ memcpy(win->clips, dev->try_clips_cap,
+ win->clipcount * sizeof(dev->clips_cap[0]));
}
return 0;
}
diff --git a/drivers/media/test-drivers/vivid/vivid-vid-out.c b/drivers/media/test-drivers/vivid/vivid-vid-out.c
index ee3446e3217c..ac1e981e8342 100644
--- a/drivers/media/test-drivers/vivid/vivid-vid-out.c
+++ b/drivers/media/test-drivers/vivid/vivid-vid-out.c
@@ -857,11 +857,9 @@ int vidioc_g_fmt_vid_out_overlay(struct file *file, void *priv,
((dev->compose_out.width + 7) / 8) * dev->compose_out.height))
return -EFAULT;
}
- if (clipcount && win->clips) {
- if (copy_to_user(win->clips, dev->clips_out,
- clipcount * sizeof(dev->clips_out[0])))
- return -EFAULT;
- }
+ if (clipcount && win->clips)
+ memcpy(win->clips, dev->clips_out,
+ clipcount * sizeof(dev->clips_out[0]));
return 0;
}
@@ -891,9 +889,8 @@ int vidioc_try_fmt_vid_out_overlay(struct file *file, void *priv,
if (win->clipcount > MAX_CLIPS)
win->clipcount = MAX_CLIPS;
if (win->clipcount) {
- if (copy_from_user(dev->try_clips_out, win->clips,
- win->clipcount * sizeof(dev->clips_out[0])))
- return -EFAULT;
+ memcpy(dev->try_clips_out, win->clips,
+ win->clipcount * sizeof(dev->clips_out[0]));
for (i = 0; i < win->clipcount; i++) {
struct v4l2_rect *r = &dev->try_clips_out[i].c;
@@ -916,9 +913,8 @@ int vidioc_try_fmt_vid_out_overlay(struct file *file, void *priv,
return -EINVAL;
}
}
- if (copy_to_user(win->clips, dev->try_clips_out,
- win->clipcount * sizeof(dev->clips_out[0])))
- return -EFAULT;
+ memcpy(win->clips, dev->try_clips_out,
+ win->clipcount * sizeof(dev->clips_out[0]));
}
return 0;
}
diff --git a/drivers/media/tuners/mt2060.c b/drivers/media/tuners/mt2060.c
index 0e7ac2b49990..204e6186bf71 100644
--- a/drivers/media/tuners/mt2060.c
+++ b/drivers/media/tuners/mt2060.c
@@ -215,7 +215,7 @@ static int mt2060_set_params(struct dvb_frontend *fe)
f_lo2 = f_lo1 - freq - IF2;
// From the Comtech datasheet, the step used is 50kHz. The tuner chip could be more precise
f_lo2 = ((f_lo2 + 25) / 50) * 50;
- priv->frequency = (f_lo1 - f_lo2 - IF2) * 1000,
+ priv->frequency = (f_lo1 - f_lo2 - IF2) * 1000;
#ifdef MT2060_SPURCHECK
// LO-related spurs detection and correction
diff --git a/drivers/media/tuners/mt2063.c b/drivers/media/tuners/mt2063.c
index 2240d214dfac..d105431a2e2d 100644
--- a/drivers/media/tuners/mt2063.c
+++ b/drivers/media/tuners/mt2063.c
@@ -1849,7 +1849,6 @@ static int mt2063_init(struct dvb_frontend *fe)
default:
return -ENODEV;
- break;
}
while (status >= 0 && *def) {
diff --git a/drivers/media/tuners/mxl5005s.c b/drivers/media/tuners/mxl5005s.c
index 1c07e2225fb3..f6e82a8e7d37 100644
--- a/drivers/media/tuners/mxl5005s.c
+++ b/drivers/media/tuners/mxl5005s.c
@@ -3926,15 +3926,26 @@ static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
u32 bandwidth)
{
struct mxl5005s_state *state = fe->tuner_priv;
-
- u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
- u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
+ u8 *AddrTable;
+ u8 *ByteTable;
int TableLen;
dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
mxl5005s_reset(fe);
+ AddrTable = kcalloc(MXL5005S_REG_WRITING_TABLE_LEN_MAX, sizeof(u8),
+ GFP_KERNEL);
+ if (!AddrTable)
+ return -ENOMEM;
+
+ ByteTable = kcalloc(MXL5005S_REG_WRITING_TABLE_LEN_MAX, sizeof(u8),
+ GFP_KERNEL);
+ if (!ByteTable) {
+ kfree(AddrTable);
+ return -ENOMEM;
+ }
+
/* Tuner initialization stage 0 */
MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
AddrTable[0] = MASTER_CONTROL_ADDR;
@@ -3949,6 +3960,9 @@ static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
+ kfree(AddrTable);
+ kfree(ByteTable);
+
return 0;
}
diff --git a/drivers/media/usb/au0828/au0828-video.c b/drivers/media/usb/au0828/au0828-video.c
index aa5bc6a2ae20..c0f118563c7d 100644
--- a/drivers/media/usb/au0828/au0828-video.c
+++ b/drivers/media/usb/au0828/au0828-video.c
@@ -231,6 +231,7 @@ static int au0828_init_isoc(struct au0828_dev *dev, int max_packets,
for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
urb = usb_alloc_urb(max_packets, GFP_KERNEL);
if (!urb) {
+ au0828_isocdbg("cannot allocate URB\n");
au0828_uninit_isoc(dev);
return -ENOMEM;
}
@@ -239,16 +240,14 @@ static int au0828_init_isoc(struct au0828_dev *dev, int max_packets,
dev->isoc_ctl.transfer_buffer[i] = usb_alloc_coherent(dev->usbdev,
sb_size, GFP_KERNEL, &urb->transfer_dma);
if (!dev->isoc_ctl.transfer_buffer[i]) {
- printk("unable to allocate %i bytes for transfer buffer %i%s\n",
- sb_size, i,
- in_interrupt() ? " while in int" : "");
+ au0828_isocdbg("cannot allocate transfer buffer\n");
au0828_uninit_isoc(dev);
return -ENOMEM;
}
memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
pipe = usb_rcvisocpipe(dev->usbdev,
- dev->isoc_in_endpointaddr),
+ dev->isoc_in_endpointaddr);
usb_fill_int_urb(urb, dev->usbdev, pipe,
dev->isoc_ctl.transfer_buffer[i], sb_size,
diff --git a/drivers/media/usb/cx231xx/cx231xx-audio.c b/drivers/media/usb/cx231xx/cx231xx-audio.c
index de42db6f6ad1..9c71b32552df 100644
--- a/drivers/media/usb/cx231xx/cx231xx-audio.c
+++ b/drivers/media/usb/cx231xx/cx231xx-audio.c
@@ -670,7 +670,7 @@ static int cx231xx_audio_fini(struct cx231xx *dev)
}
if (dev->adev.sndcard) {
- snd_card_free(dev->adev.sndcard);
+ snd_card_free_when_closed(dev->adev.sndcard);
kfree(dev->adev.alt_max_pkt_size);
dev->adev.sndcard = NULL;
}
diff --git a/drivers/media/usb/cx231xx/cx231xx-core.c b/drivers/media/usb/cx231xx/cx231xx-core.c
index 05d91caaed0c..727e6268567f 100644
--- a/drivers/media/usb/cx231xx/cx231xx-core.c
+++ b/drivers/media/usb/cx231xx/cx231xx-core.c
@@ -1061,9 +1061,8 @@ int cx231xx_init_isoc(struct cx231xx *dev, int max_packets,
&urb->transfer_dma);
if (!dev->video_mode.isoc_ctl.transfer_buffer[i]) {
dev_err(dev->dev,
- "unable to allocate %i bytes for transfer buffer %i%s\n",
- sb_size, i,
- in_interrupt() ? " while in int" : "");
+ "unable to allocate %i bytes for transfer buffer %i\n",
+ sb_size, i);
cx231xx_uninit_isoc(dev);
return -ENOMEM;
}
@@ -1197,9 +1196,8 @@ int cx231xx_init_bulk(struct cx231xx *dev, int max_packets,
&urb->transfer_dma);
if (!dev->video_mode.bulk_ctl.transfer_buffer[i]) {
dev_err(dev->dev,
- "unable to allocate %i bytes for transfer buffer %i%s\n",
- sb_size, i,
- in_interrupt() ? " while in int" : "");
+ "unable to allocate %i bytes for transfer buffer %i\n",
+ sb_size, i);
cx231xx_uninit_bulk(dev);
return -ENOMEM;
}
diff --git a/drivers/media/usb/cx231xx/cx231xx-vbi.c b/drivers/media/usb/cx231xx/cx231xx-vbi.c
index d2f143a096d1..fdc8b7f7b0c1 100644
--- a/drivers/media/usb/cx231xx/cx231xx-vbi.c
+++ b/drivers/media/usb/cx231xx/cx231xx-vbi.c
@@ -408,9 +408,8 @@ int cx231xx_init_vbi_isoc(struct cx231xx *dev, int max_packets,
kzalloc(sb_size, GFP_KERNEL);
if (!dev->vbi_mode.bulk_ctl.transfer_buffer[i]) {
dev_err(dev->dev,
- "unable to allocate %i bytes for transfer buffer %i%s\n",
- sb_size, i,
- in_interrupt() ? " while in int" : "");
+ "unable to allocate %i bytes for transfer buffer %i\n",
+ sb_size, i);
cx231xx_uninit_vbi_isoc(dev);
return -ENOMEM;
}
diff --git a/drivers/media/usb/dvb-usb-v2/dvbsky.c b/drivers/media/usb/dvb-usb-v2/dvbsky.c
index 0d9657f7f29d..689829f1b52a 100644
--- a/drivers/media/usb/dvb-usb-v2/dvbsky.c
+++ b/drivers/media/usb/dvb-usb-v2/dvbsky.c
@@ -287,8 +287,8 @@ static int dvbsky_s960_attach(struct dvb_usb_adapter *adap)
m88ds3103_pdata.ts_clk = 16000;
m88ds3103_pdata.ts_clk_pol = 0;
m88ds3103_pdata.agc = 0x99;
- m88ds3103_pdata.lnb_hv_pol = 1,
- m88ds3103_pdata.lnb_en_pol = 1,
+ m88ds3103_pdata.lnb_hv_pol = 1;
+ m88ds3103_pdata.lnb_en_pol = 1;
state->i2c_client_demod = dvb_module_probe("m88ds3103", NULL,
&d->i2c_adap,
@@ -383,15 +383,15 @@ static int dvbsky_s960c_attach(struct dvb_usb_adapter *adap)
struct sp2_config sp2_config = {};
/* attach demod */
- m88ds3103_pdata.clk = 27000000,
- m88ds3103_pdata.i2c_wr_max = 33,
- m88ds3103_pdata.clk_out = 0,
- m88ds3103_pdata.ts_mode = M88DS3103_TS_CI,
- m88ds3103_pdata.ts_clk = 10000,
- m88ds3103_pdata.ts_clk_pol = 1,
- m88ds3103_pdata.agc = 0x99,
- m88ds3103_pdata.lnb_hv_pol = 0,
- m88ds3103_pdata.lnb_en_pol = 1,
+ m88ds3103_pdata.clk = 27000000;
+ m88ds3103_pdata.i2c_wr_max = 33;
+ m88ds3103_pdata.clk_out = 0;
+ m88ds3103_pdata.ts_mode = M88DS3103_TS_CI;
+ m88ds3103_pdata.ts_clk = 10000;
+ m88ds3103_pdata.ts_clk_pol = 1;
+ m88ds3103_pdata.agc = 0x99;
+ m88ds3103_pdata.lnb_hv_pol = 0;
+ m88ds3103_pdata.lnb_en_pol = 1;
state->i2c_client_demod = dvb_module_probe("m88ds3103", NULL,
&d->i2c_adap,
diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
index 91460e4d0c30..3952cc534b4a 100644
--- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
+++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c
@@ -955,7 +955,7 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap)
struct mn88472_config mn88472_config = {};
mn88472_config.fe = &adap->fe[1];
- mn88472_config.i2c_wr_max = 22,
+ mn88472_config.i2c_wr_max = 22;
strscpy(info.type, "mn88472", I2C_NAME_SIZE);
mn88472_config.xtal = 20500000;
mn88472_config.ts_mode = SERIAL_TS_MODE;
@@ -980,7 +980,7 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap)
struct mn88473_config mn88473_config = {};
mn88473_config.fe = &adap->fe[1];
- mn88473_config.i2c_wr_max = 22,
+ mn88473_config.i2c_wr_max = 22;
strscpy(info.type, "mn88473", I2C_NAME_SIZE);
info.addr = 0x18;
info.platform_data = &mn88473_config;
diff --git a/drivers/media/usb/dvb-usb-v2/zd1301.c b/drivers/media/usb/dvb-usb-v2/zd1301.c
index ba2c1b0d3989..72aa6a9a9ed4 100644
--- a/drivers/media/usb/dvb-usb-v2/zd1301.c
+++ b/drivers/media/usb/dvb-usb-v2/zd1301.c
@@ -150,7 +150,7 @@ static int zd1301_frontend_attach(struct dvb_usb_adapter *adap)
}
if (!pdev->dev.driver) {
ret = -ENODEV;
- goto err;
+ goto err_platform_device_unregister;
}
if (!try_module_get(pdev->dev.driver->owner)) {
ret = -ENODEV;
diff --git a/drivers/media/usb/dvb-usb/dib0700_devices.c b/drivers/media/usb/dvb-usb/dib0700_devices.c
index d3288c107906..710c1afe3e85 100644
--- a/drivers/media/usb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/usb/dvb-usb/dib0700_devices.c
@@ -3074,8 +3074,8 @@ static int nim7090_tuner_attach(struct dvb_usb_adapter *adap)
struct dib0700_adapter_state *st = adap->priv;
struct i2c_adapter *tun_i2c = st->dib7000p_ops.get_i2c_tuner(adap->fe_adap[0].fe);
- nim7090_dib0090_config.reset = st->dib7000p_ops.tuner_sleep,
- nim7090_dib0090_config.sleep = st->dib7000p_ops.tuner_sleep,
+ nim7090_dib0090_config.reset = st->dib7000p_ops.tuner_sleep;
+ nim7090_dib0090_config.sleep = st->dib7000p_ops.tuner_sleep;
nim7090_dib0090_config.get_adc_power = st->dib7000p_ops.get_adc_power;
if (dvb_attach(dib0090_register, adap->fe_adap[0].fe, tun_i2c, &nim7090_dib0090_config) == NULL)
diff --git a/drivers/media/usb/dvb-usb/dw2102.c b/drivers/media/usb/dvb-usb/dw2102.c
index a27a68440325..f0e686b05dc6 100644
--- a/drivers/media/usb/dvb-usb/dw2102.c
+++ b/drivers/media/usb/dvb-usb/dw2102.c
@@ -1770,6 +1770,7 @@ enum dw2102_table_entry {
TEVII_S660,
PROF_7500,
GENIATECH_SU3000,
+ HAUPPAUGE_MAX_S2,
TERRATEC_CINERGY_S2,
TEVII_S480_1,
TEVII_S480_2,
@@ -1802,6 +1803,7 @@ static struct usb_device_id dw2102_table[] = {
[TEVII_S660] = {USB_DEVICE(0x9022, USB_PID_TEVII_S660)},
[PROF_7500] = {USB_DEVICE(0x3034, 0x7500)},
[GENIATECH_SU3000] = {USB_DEVICE(0x1f4d, 0x3000)},
+ [HAUPPAUGE_MAX_S2] = {USB_DEVICE(0x2040, 0xd900)},
[TERRATEC_CINERGY_S2] = {USB_DEVICE(USB_VID_TERRATEC, USB_PID_TERRATEC_CINERGY_S2_R1)},
[TEVII_S480_1] = {USB_DEVICE(0x9022, USB_PID_TEVII_S480_1)},
[TEVII_S480_2] = {USB_DEVICE(0x9022, USB_PID_TEVII_S480_2)},
@@ -2230,12 +2232,16 @@ static struct dvb_usb_device_properties su3000_properties = {
}},
}
},
- .num_device_descs = 8,
+ .num_device_descs = 9,
.devices = {
{ "SU3000HD DVB-S USB2.0",
{ &dw2102_table[GENIATECH_SU3000], NULL },
{ NULL },
},
+ { "Hauppauge MAX S2 or WinTV NOVA HD USB2.0",
+ { &dw2102_table[HAUPPAUGE_MAX_S2], NULL },
+ { NULL },
+ },
{ "Terratec Cinergy S2 USB HD",
{ &dw2102_table[TERRATEC_CINERGY_S2], NULL },
{ NULL },
diff --git a/drivers/media/usb/dvb-usb/gp8psk.c b/drivers/media/usb/dvb-usb/gp8psk.c
index c07f46f5176e..b4f661bb5648 100644
--- a/drivers/media/usb/dvb-usb/gp8psk.c
+++ b/drivers/media/usb/dvb-usb/gp8psk.c
@@ -182,7 +182,7 @@ out_rel_fw:
static int gp8psk_power_ctrl(struct dvb_usb_device *d, int onoff)
{
- u8 status, buf;
+ u8 status = 0, buf;
int gp_product_id = le16_to_cpu(d->udev->descriptor.idProduct);
if (onoff) {
diff --git a/drivers/media/usb/em28xx/em28xx-audio.c b/drivers/media/usb/em28xx/em28xx-audio.c
index dc968fd5ace9..4d5ab1433b44 100644
--- a/drivers/media/usb/em28xx/em28xx-audio.c
+++ b/drivers/media/usb/em28xx/em28xx-audio.c
@@ -583,9 +583,9 @@ static int em28xx_cvol_new(struct snd_card *card, struct em28xx *dev,
struct snd_kcontrol_new tmp;
memset(&tmp, 0, sizeof(tmp));
- tmp.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
- tmp.private_value = id,
- tmp.name = ctl_name,
+ tmp.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+ tmp.private_value = id;
+ tmp.name = ctl_name;
/* Add Mute Control */
sprintf(ctl_name, "%s Switch", name);
@@ -600,16 +600,16 @@ static int em28xx_cvol_new(struct snd_card *card, struct em28xx *dev,
ctl_name, id);
memset(&tmp, 0, sizeof(tmp));
- tmp.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
- tmp.private_value = id,
- tmp.name = ctl_name,
+ tmp.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+ tmp.private_value = id;
+ tmp.name = ctl_name;
/* Add Volume Control */
sprintf(ctl_name, "%s Volume", name);
tmp.get = em28xx_vol_get;
tmp.put = em28xx_vol_put;
tmp.info = em28xx_vol_info;
- tmp.tlv.p = em28xx_db_scale,
+ tmp.tlv.p = em28xx_db_scale;
kctl = snd_ctl_new1(&tmp, dev);
err = snd_ctl_add(card, kctl);
if (err < 0)
diff --git a/drivers/media/usb/gspca/gspca.c b/drivers/media/usb/gspca/gspca.c
index c295f642d352..158c8e28ed2c 100644
--- a/drivers/media/usb/gspca/gspca.c
+++ b/drivers/media/usb/gspca/gspca.c
@@ -1575,6 +1575,7 @@ out:
input_unregister_device(gspca_dev->input_dev);
#endif
v4l2_ctrl_handler_free(gspca_dev->vdev.ctrl_handler);
+ v4l2_device_unregister(&gspca_dev->v4l2_dev);
kfree(gspca_dev->usb_buf);
kfree(gspca_dev);
return ret;
diff --git a/drivers/media/usb/gspca/ov534.c b/drivers/media/usb/gspca/ov534.c
index 9a11158f38da..8b6a57f170d0 100644
--- a/drivers/media/usb/gspca/ov534.c
+++ b/drivers/media/usb/gspca/ov534.c
@@ -1220,9 +1220,9 @@ static int sd_init_controls(struct gspca_dev *gspca_dev)
int hflip_def;
if (sd->sensor == SENSOR_OV767x) {
- saturation_min = 0,
- saturation_max = 6,
- saturation_def = 3,
+ saturation_min = 0;
+ saturation_max = 6;
+ saturation_def = 3;
brightness_min = -127;
brightness_max = 127;
brightness_def = 0;
@@ -1233,9 +1233,9 @@ static int sd_init_controls(struct gspca_dev *gspca_dev)
exposure_def = 0x13;
hflip_def = 1;
} else {
- saturation_min = 0,
- saturation_max = 255,
- saturation_def = 64,
+ saturation_min = 0;
+ saturation_max = 255;
+ saturation_def = 64;
brightness_min = 0;
brightness_max = 255;
brightness_def = 0;
diff --git a/drivers/media/usb/msi2500/msi2500.c b/drivers/media/usb/msi2500/msi2500.c
index 65be6f140fe8..63882a5248ae 100644
--- a/drivers/media/usb/msi2500/msi2500.c
+++ b/drivers/media/usb/msi2500/msi2500.c
@@ -867,7 +867,7 @@ static void msi2500_stop_streaming(struct vb2_queue *vq)
/* according to tests, at least 700us delay is required */
msleep(20);
- if (!msi2500_ctrl_msg(dev, CMD_STOP_STREAMING, 0)) {
+ if (dev->udev && !msi2500_ctrl_msg(dev, CMD_STOP_STREAMING, 0)) {
/* sleep USB IF / ADC */
msi2500_ctrl_msg(dev, CMD_WREG, 0x01000003);
}
@@ -1230,7 +1230,7 @@ static int msi2500_probe(struct usb_interface *intf,
}
dev->master = master;
- master->bus_num = 0;
+ master->bus_num = -1;
master->num_chipselect = 1;
master->transfer_one_message = msi2500_transfer_one_message;
spi_master_set_devdata(master, dev);
diff --git a/drivers/media/usb/pvrusb2/pvrusb2-devattr.c b/drivers/media/usb/pvrusb2/pvrusb2-devattr.c
index 1fcf63218885..d1b984ec757d 100644
--- a/drivers/media/usb/pvrusb2/pvrusb2-devattr.c
+++ b/drivers/media/usb/pvrusb2/pvrusb2-devattr.c
@@ -594,7 +594,7 @@ static int pvr2_lgdt3306a_attach(struct pvr2_dvb_adapter *adap)
lgdt3306a_config.mpeg_mode = LGDT3306A_MPEG_PARALLEL;
lgdt3306a_config.tpclk_edge = LGDT3306A_TPCLK_FALLING_EDGE;
lgdt3306a_config.tpvalid_polarity = LGDT3306A_TP_VALID_LOW;
- lgdt3306a_config.xtalMHz = 25, /* demod clock MHz; 24/25 supported */
+ lgdt3306a_config.xtalMHz = 25; /* demod clock MHz; 24/25 supported */
adap->i2c_client_demod[0] = dvb_module_probe("lgdt3306a", NULL,
&adap->channel.hdw->i2c_adap,
diff --git a/drivers/media/usb/tm6000/tm6000-video.c b/drivers/media/usb/tm6000/tm6000-video.c
index bfba06ea60e9..3f650ede0c3d 100644
--- a/drivers/media/usb/tm6000/tm6000-video.c
+++ b/drivers/media/usb/tm6000/tm6000-video.c
@@ -461,11 +461,12 @@ static int tm6000_alloc_urb_buffers(struct tm6000_core *dev)
if (dev->urb_buffer)
return 0;
- dev->urb_buffer = kmalloc_array(num_bufs, sizeof(void *), GFP_KERNEL);
+ dev->urb_buffer = kmalloc_array(num_bufs, sizeof(*dev->urb_buffer),
+ GFP_KERNEL);
if (!dev->urb_buffer)
return -ENOMEM;
- dev->urb_dma = kmalloc_array(num_bufs, sizeof(dma_addr_t *),
+ dev->urb_dma = kmalloc_array(num_bufs, sizeof(*dev->urb_dma),
GFP_KERNEL);
if (!dev->urb_dma)
return -ENOMEM;
@@ -692,8 +693,6 @@ static void free_buffer(struct videobuf_queue *vq, struct tm6000_buffer *buf)
struct tm6000_core *dev = fh->dev;
unsigned long flags;
- BUG_ON(in_interrupt());
-
/* We used to wait for the buffer to finish here, but this didn't work
because, as we were keeping the state as VIDEOBUF_QUEUED,
videobuf_queue_cancel marked it as finished for us.
diff --git a/drivers/media/usb/uvc/uvc_ctrl.c b/drivers/media/usb/uvc/uvc_ctrl.c
index f479d8971dfb..011e69427b7c 100644
--- a/drivers/media/usb/uvc/uvc_ctrl.c
+++ b/drivers/media/usb/uvc/uvc_ctrl.c
@@ -1608,8 +1608,8 @@ int uvc_ctrl_set(struct uvc_fh *handle,
if (step == 0)
step = 1;
- xctrl->value = min + ((u32)(xctrl->value - min) + step / 2)
- / step * step;
+ xctrl->value = min + DIV_ROUND_CLOSEST((u32)(xctrl->value - min),
+ step) * step;
if (mapping->data_type == UVC_CTRL_DATA_TYPE_SIGNED)
xctrl->value = clamp(xctrl->value, min, max);
else
diff --git a/drivers/media/usb/zr364xx/zr364xx.c b/drivers/media/usb/zr364xx/zr364xx.c
index 8c670934d920..1e1c6b4d1874 100644
--- a/drivers/media/usb/zr364xx/zr364xx.c
+++ b/drivers/media/usb/zr364xx/zr364xx.c
@@ -357,8 +357,6 @@ static void free_buffer(struct videobuf_queue *vq, struct zr364xx_buffer *buf)
{
_DBG("%s\n", __func__);
- BUG_ON(in_interrupt());
-
videobuf_vmalloc_free(&buf->vb);
buf->vb.state = VIDEOBUF_NEEDS_INIT;
}
@@ -1327,6 +1325,7 @@ static int zr364xx_board_init(struct zr364xx_camera *cam)
{
struct zr364xx_pipeinfo *pipe = cam->pipe;
unsigned long i;
+ int err;
DBG("board init: %p\n", cam);
memset(pipe, 0, sizeof(*pipe));
@@ -1359,9 +1358,8 @@ static int zr364xx_board_init(struct zr364xx_camera *cam)
if (i == 0) {
printk(KERN_INFO KBUILD_MODNAME ": out of memory. Aborting\n");
- kfree(cam->pipe->transfer_buffer);
- cam->pipe->transfer_buffer = NULL;
- return -ENOMEM;
+ err = -ENOMEM;
+ goto err_free;
} else
cam->buffer.dwFrames = i;
@@ -1376,9 +1374,17 @@ static int zr364xx_board_init(struct zr364xx_camera *cam)
/*** end create system buffers ***/
/* start read pipe */
- zr364xx_start_readpipe(cam);
+ err = zr364xx_start_readpipe(cam);
+ if (err)
+ goto err_free;
+
DBG(": board initialized\n");
return 0;
+
+err_free:
+ kfree(cam->pipe->transfer_buffer);
+ cam->pipe->transfer_buffer = NULL;
+ return err;
}
static int zr364xx_probe(struct usb_interface *intf,
@@ -1575,10 +1581,19 @@ static int zr364xx_resume(struct usb_interface *intf)
if (!cam->was_streaming)
return 0;
- zr364xx_start_readpipe(cam);
+ res = zr364xx_start_readpipe(cam);
+ if (res)
+ return res;
+
res = zr364xx_prepare(cam);
- if (!res)
- zr364xx_start_acquire(cam);
+ if (res)
+ goto err_prepare;
+
+ zr364xx_start_acquire(cam);
+ return 0;
+
+err_prepare:
+ zr364xx_stop_readpipe(cam);
return res;
}
#endif
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
index 3dc17ebe14fa..78007dba4677 100644
--- a/drivers/media/v4l2-core/v4l2-common.c
+++ b/drivers/media/v4l2-core/v4l2-common.c
@@ -441,3 +441,36 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
return 0;
}
EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
+
+s64 v4l2_get_link_rate(struct v4l2_ctrl_handler *handler, unsigned int mul,
+ unsigned int div)
+{
+ struct v4l2_ctrl *ctrl;
+ s64 freq;
+
+ ctrl = v4l2_ctrl_find(handler, V4L2_CID_LINK_FREQ);
+ if (ctrl) {
+ struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ };
+ int ret;
+
+ qm.index = v4l2_ctrl_g_ctrl(ctrl);
+
+ ret = v4l2_querymenu(handler, &qm);
+ if (ret)
+ return -ENOENT;
+
+ freq = qm.value;
+ } else {
+ if (!mul || !div)
+ return -ENOENT;
+
+ ctrl = v4l2_ctrl_find(handler, V4L2_CID_PIXEL_RATE);
+ if (!ctrl)
+ return -ENOENT;
+
+ freq = div_u64(v4l2_ctrl_g_ctrl_int64(ctrl) * mul, div);
+ }
+
+ return freq > 0 ? freq : -EINVAL;
+}
+EXPORT_SYMBOL_GPL(v4l2_get_link_rate);
diff --git a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
index a99e82ec9ab6..0ca75f6784c5 100644
--- a/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
+++ b/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
@@ -23,103 +23,6 @@
#include <media/v4l2-ctrls.h>
#include <media/v4l2-ioctl.h>
-/**
- * assign_in_user() - Copy from one __user var to another one
- *
- * @to: __user var where data will be stored
- * @from: __user var where data will be retrieved.
- *
- * As this code very often needs to allocate userspace memory, it is easier
- * to have a macro that will do both get_user() and put_user() at once.
- *
- * This function complements the macros defined at asm-generic/uaccess.h.
- * It uses the same argument order as copy_in_user()
- */
-#define assign_in_user(to, from) \
-({ \
- typeof(*from) __assign_tmp; \
- \
- get_user(__assign_tmp, from) || put_user(__assign_tmp, to); \
-})
-
-/**
- * get_user_cast() - Stores at a kernelspace local var the contents from a
- * pointer with userspace data that is not tagged with __user.
- *
- * @__x: var where data will be stored
- * @__ptr: var where data will be retrieved.
- *
- * Sometimes we need to declare a pointer without __user because it
- * comes from a pointer struct field that will be retrieved from userspace
- * by the 64-bit native ioctl handler. This function ensures that the
- * @__ptr will be cast to __user before calling get_user() in order to
- * avoid warnings with static code analyzers like smatch.
- */
-#define get_user_cast(__x, __ptr) \
-({ \
- get_user(__x, (typeof(*__ptr) __user *)(__ptr)); \
-})
-
-/**
- * put_user_force() - Stores the contents of a kernelspace local var
- * into a userspace pointer, removing any __user cast.
- *
- * @__x: var where data will be stored
- * @__ptr: var where data will be retrieved.
- *
- * Sometimes we need to remove the __user attribute from some data,
- * by passing the __force macro. This function ensures that the
- * @__ptr will be cast with __force before calling put_user(), in order to
- * avoid warnings with static code analyzers like smatch.
- */
-#define put_user_force(__x, __ptr) \
-({ \
- put_user((typeof(*__x) __force *)(__x), __ptr); \
-})
-
-/**
- * assign_in_user_cast() - Copy from one __user var to another one
- *
- * @to: __user var where data will be stored
- * @from: var where data will be retrieved that needs to be cast to __user.
- *
- * As this code very often needs to allocate userspace memory, it is easier
- * to have a macro that will do both get_user_cast() and put_user() at once.
- *
- * This function should be used instead of assign_in_user() when the @from
- * variable was not declared as __user. See get_user_cast() for more details.
- *
- * This function complements the macros defined at asm-generic/uaccess.h.
- * It uses the same argument order as copy_in_user()
- */
-#define assign_in_user_cast(to, from) \
-({ \
- typeof(*from) __assign_tmp; \
- \
- get_user_cast(__assign_tmp, from) || put_user(__assign_tmp, to);\
-})
-
-/**
- * native_ioctl - Ancillary function that calls the native 64 bits ioctl
- * handler.
- *
- * @file: pointer to &struct file with the file handler
- * @cmd: ioctl to be called
- * @arg: arguments passed from/to the ioctl handler
- *
- * This function calls the native ioctl handler at v4l2-dev, e. g. v4l2_ioctl()
- */
-static long native_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- long ret = -ENOIOCTLCMD;
-
- if (file->f_op->unlocked_ioctl)
- ret = file->f_op->unlocked_ioctl(file, cmd, arg);
-
- return ret;
-}
-
-
/*
* Per-ioctl data copy handlers.
*
@@ -150,77 +53,54 @@ struct v4l2_window32 {
__u8 global_alpha;
};
-static int get_v4l2_window32(struct v4l2_window __user *p64,
- struct v4l2_window32 __user *p32,
- void __user *aux_buf, u32 aux_space)
+static int get_v4l2_window32(struct v4l2_window *p64,
+ struct v4l2_window32 __user *p32)
{
- struct v4l2_clip32 __user *uclips;
- struct v4l2_clip __user *kclips;
- compat_caddr_t p;
- u32 clipcount;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- copy_in_user(&p64->w, &p32->w, sizeof(p32->w)) ||
- assign_in_user(&p64->field, &p32->field) ||
- assign_in_user(&p64->chromakey, &p32->chromakey) ||
- assign_in_user(&p64->global_alpha, &p32->global_alpha) ||
- get_user(clipcount, &p32->clipcount) ||
- put_user(clipcount, &p64->clipcount))
- return -EFAULT;
- if (clipcount > 2048)
- return -EINVAL;
- if (!clipcount)
- return put_user(NULL, &p64->clips);
+ struct v4l2_window32 w32;
- if (get_user(p, &p32->clips))
- return -EFAULT;
- uclips = compat_ptr(p);
- if (aux_space < clipcount * sizeof(*kclips))
- return -EFAULT;
- kclips = aux_buf;
- if (put_user(kclips, &p64->clips))
+ if (copy_from_user(&w32, p32, sizeof(w32)))
return -EFAULT;
- while (clipcount--) {
- if (copy_in_user(&kclips->c, &uclips->c, sizeof(uclips->c)))
- return -EFAULT;
- if (put_user(clipcount ? kclips + 1 : NULL, &kclips->next))
- return -EFAULT;
- uclips++;
- kclips++;
- }
+ *p64 = (struct v4l2_window) {
+ .w = w32.w,
+ .field = w32.field,
+ .chromakey = w32.chromakey,
+ .clips = (void __force *)compat_ptr(w32.clips),
+ .clipcount = w32.clipcount,
+ .bitmap = compat_ptr(w32.bitmap),
+ .global_alpha = w32.global_alpha,
+ };
+
+ if (p64->clipcount > 2048)
+ return -EINVAL;
+ if (!p64->clipcount)
+ p64->clips = NULL;
+
return 0;
}
-static int put_v4l2_window32(struct v4l2_window __user *p64,
+static int put_v4l2_window32(struct v4l2_window *p64,
struct v4l2_window32 __user *p32)
{
- struct v4l2_clip __user *kclips;
- struct v4l2_clip32 __user *uclips;
- compat_caddr_t p;
- u32 clipcount;
-
- if (copy_in_user(&p32->w, &p64->w, sizeof(p64->w)) ||
- assign_in_user(&p32->field, &p64->field) ||
- assign_in_user(&p32->chromakey, &p64->chromakey) ||
- assign_in_user(&p32->global_alpha, &p64->global_alpha) ||
- get_user(clipcount, &p64->clipcount) ||
- put_user(clipcount, &p32->clipcount))
- return -EFAULT;
- if (!clipcount)
- return 0;
+ struct v4l2_window32 w32;
+
+ memset(&w32, 0, sizeof(w32));
+ w32 = (struct v4l2_window32) {
+ .w = p64->w,
+ .field = p64->field,
+ .chromakey = p64->chromakey,
+ .clips = (uintptr_t)p64->clips,
+ .clipcount = p64->clipcount,
+ .bitmap = ptr_to_compat(p64->bitmap),
+ .global_alpha = p64->global_alpha,
+ };
- if (get_user(kclips, &p64->clips))
+ /* copy everything except the clips pointer */
+ if (copy_to_user(p32, &w32, offsetof(struct v4l2_window32, clips)) ||
+ copy_to_user(&p32->clipcount, &w32.clipcount,
+ sizeof(w32) - offsetof(struct v4l2_window32, clipcount)))
return -EFAULT;
- if (get_user(p, &p32->clips))
- return -EFAULT;
- uclips = compat_ptr(p);
- while (clipcount--) {
- if (copy_in_user(&uclips->c, &kclips->c, sizeof(uclips->c)))
- return -EFAULT;
- uclips++;
- kclips++;
- }
+
return 0;
}
@@ -257,169 +137,99 @@ struct v4l2_create_buffers32 {
__u32 reserved[7];
};
-static int __bufsize_v4l2_format(struct v4l2_format32 __user *p32, u32 *size)
-{
- u32 type;
-
- if (get_user(type, &p32->type))
- return -EFAULT;
-
- switch (type) {
- case V4L2_BUF_TYPE_VIDEO_OVERLAY:
- case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY: {
- u32 clipcount;
-
- if (get_user(clipcount, &p32->fmt.win.clipcount))
- return -EFAULT;
- if (clipcount > 2048)
- return -EINVAL;
- *size = clipcount * sizeof(struct v4l2_clip);
- return 0;
- }
- default:
- *size = 0;
- return 0;
- }
-}
-
-static int bufsize_v4l2_format(struct v4l2_format32 __user *p32, u32 *size)
-{
- if (!access_ok(p32, sizeof(*p32)))
- return -EFAULT;
- return __bufsize_v4l2_format(p32, size);
-}
-
-static int __get_v4l2_format32(struct v4l2_format __user *p64,
- struct v4l2_format32 __user *p32,
- void __user *aux_buf, u32 aux_space)
+static int get_v4l2_format32(struct v4l2_format *p64,
+ struct v4l2_format32 __user *p32)
{
- u32 type;
-
- if (get_user(type, &p32->type) || put_user(type, &p64->type))
+ if (get_user(p64->type, &p32->type))
return -EFAULT;
- switch (type) {
+ switch (p64->type) {
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
- return copy_in_user(&p64->fmt.pix, &p32->fmt.pix,
- sizeof(p64->fmt.pix)) ? -EFAULT : 0;
+ return copy_from_user(&p64->fmt.pix, &p32->fmt.pix,
+ sizeof(p64->fmt.pix)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
- return copy_in_user(&p64->fmt.pix_mp, &p32->fmt.pix_mp,
- sizeof(p64->fmt.pix_mp)) ? -EFAULT : 0;
+ return copy_from_user(&p64->fmt.pix_mp, &p32->fmt.pix_mp,
+ sizeof(p64->fmt.pix_mp)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_VIDEO_OVERLAY:
case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
- return get_v4l2_window32(&p64->fmt.win, &p32->fmt.win,
- aux_buf, aux_space);
+ return get_v4l2_window32(&p64->fmt.win, &p32->fmt.win);
case V4L2_BUF_TYPE_VBI_CAPTURE:
case V4L2_BUF_TYPE_VBI_OUTPUT:
- return copy_in_user(&p64->fmt.vbi, &p32->fmt.vbi,
- sizeof(p64->fmt.vbi)) ? -EFAULT : 0;
+ return copy_from_user(&p64->fmt.vbi, &p32->fmt.vbi,
+ sizeof(p64->fmt.vbi)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
- return copy_in_user(&p64->fmt.sliced, &p32->fmt.sliced,
- sizeof(p64->fmt.sliced)) ? -EFAULT : 0;
+ return copy_from_user(&p64->fmt.sliced, &p32->fmt.sliced,
+ sizeof(p64->fmt.sliced)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_SDR_CAPTURE:
case V4L2_BUF_TYPE_SDR_OUTPUT:
- return copy_in_user(&p64->fmt.sdr, &p32->fmt.sdr,
- sizeof(p64->fmt.sdr)) ? -EFAULT : 0;
+ return copy_from_user(&p64->fmt.sdr, &p32->fmt.sdr,
+ sizeof(p64->fmt.sdr)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_META_CAPTURE:
case V4L2_BUF_TYPE_META_OUTPUT:
- return copy_in_user(&p64->fmt.meta, &p32->fmt.meta,
- sizeof(p64->fmt.meta)) ? -EFAULT : 0;
+ return copy_from_user(&p64->fmt.meta, &p32->fmt.meta,
+ sizeof(p64->fmt.meta)) ? -EFAULT : 0;
default:
return -EINVAL;
}
}
-static int get_v4l2_format32(struct v4l2_format __user *p64,
- struct v4l2_format32 __user *p32,
- void __user *aux_buf, u32 aux_space)
-{
- if (!access_ok(p32, sizeof(*p32)))
- return -EFAULT;
- return __get_v4l2_format32(p64, p32, aux_buf, aux_space);
-}
-
-static int bufsize_v4l2_create(struct v4l2_create_buffers32 __user *p32,
- u32 *size)
-{
- if (!access_ok(p32, sizeof(*p32)))
- return -EFAULT;
- return __bufsize_v4l2_format(&p32->format, size);
-}
-
-static int get_v4l2_create32(struct v4l2_create_buffers __user *p64,
- struct v4l2_create_buffers32 __user *p32,
- void __user *aux_buf, u32 aux_space)
+static int get_v4l2_create32(struct v4l2_create_buffers *p64,
+ struct v4l2_create_buffers32 __user *p32)
{
- if (!access_ok(p32, sizeof(*p32)) ||
- copy_in_user(p64, p32,
- offsetof(struct v4l2_create_buffers32, format)))
+ if (copy_from_user(p64, p32,
+ offsetof(struct v4l2_create_buffers32, format)))
return -EFAULT;
- return __get_v4l2_format32(&p64->format, &p32->format,
- aux_buf, aux_space);
+ return get_v4l2_format32(&p64->format, &p32->format);
}
-static int __put_v4l2_format32(struct v4l2_format __user *p64,
- struct v4l2_format32 __user *p32)
+static int put_v4l2_format32(struct v4l2_format *p64,
+ struct v4l2_format32 __user *p32)
{
- u32 type;
-
- if (get_user(type, &p64->type))
- return -EFAULT;
-
- switch (type) {
+ switch (p64->type) {
case V4L2_BUF_TYPE_VIDEO_CAPTURE:
case V4L2_BUF_TYPE_VIDEO_OUTPUT:
- return copy_in_user(&p32->fmt.pix, &p64->fmt.pix,
+ return copy_to_user(&p32->fmt.pix, &p64->fmt.pix,
sizeof(p64->fmt.pix)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
- return copy_in_user(&p32->fmt.pix_mp, &p64->fmt.pix_mp,
+ return copy_to_user(&p32->fmt.pix_mp, &p64->fmt.pix_mp,
sizeof(p64->fmt.pix_mp)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_VIDEO_OVERLAY:
case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY:
return put_v4l2_window32(&p64->fmt.win, &p32->fmt.win);
case V4L2_BUF_TYPE_VBI_CAPTURE:
case V4L2_BUF_TYPE_VBI_OUTPUT:
- return copy_in_user(&p32->fmt.vbi, &p64->fmt.vbi,
+ return copy_to_user(&p32->fmt.vbi, &p64->fmt.vbi,
sizeof(p64->fmt.vbi)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
- return copy_in_user(&p32->fmt.sliced, &p64->fmt.sliced,
+ return copy_to_user(&p32->fmt.sliced, &p64->fmt.sliced,
sizeof(p64->fmt.sliced)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_SDR_CAPTURE:
case V4L2_BUF_TYPE_SDR_OUTPUT:
- return copy_in_user(&p32->fmt.sdr, &p64->fmt.sdr,
+ return copy_to_user(&p32->fmt.sdr, &p64->fmt.sdr,
sizeof(p64->fmt.sdr)) ? -EFAULT : 0;
case V4L2_BUF_TYPE_META_CAPTURE:
case V4L2_BUF_TYPE_META_OUTPUT:
- return copy_in_user(&p32->fmt.meta, &p64->fmt.meta,
+ return copy_to_user(&p32->fmt.meta, &p64->fmt.meta,
sizeof(p64->fmt.meta)) ? -EFAULT : 0;
default:
return -EINVAL;
}
}
-static int put_v4l2_format32(struct v4l2_format __user *p64,
- struct v4l2_format32 __user *p32)
-{
- if (!access_ok(p32, sizeof(*p32)))
- return -EFAULT;
- return __put_v4l2_format32(p64, p32);
-}
-
-static int put_v4l2_create32(struct v4l2_create_buffers __user *p64,
+static int put_v4l2_create32(struct v4l2_create_buffers *p64,
struct v4l2_create_buffers32 __user *p32)
{
- if (!access_ok(p32, sizeof(*p32)) ||
- copy_in_user(p32, p64,
+ if (copy_to_user(p32, p64,
offsetof(struct v4l2_create_buffers32, format)) ||
- assign_in_user(&p32->capabilities, &p64->capabilities) ||
- copy_in_user(p32->reserved, p64->reserved, sizeof(p64->reserved)))
+ put_user(p64->capabilities, &p32->capabilities) ||
+ copy_to_user(p32->reserved, p64->reserved, sizeof(p64->reserved)))
return -EFAULT;
- return __put_v4l2_format32(&p64->format, &p32->format);
+ return put_v4l2_format32(&p64->format, &p32->format);
}
struct v4l2_standard32 {
@@ -431,27 +241,23 @@ struct v4l2_standard32 {
__u32 reserved[4];
};
-static int get_v4l2_standard32(struct v4l2_standard __user *p64,
+static int get_v4l2_standard32(struct v4l2_standard *p64,
struct v4l2_standard32 __user *p32)
{
/* other fields are not set by the user, nor used by the driver */
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p64->index, &p32->index))
- return -EFAULT;
- return 0;
+ return get_user(p64->index, &p32->index);
}
-static int put_v4l2_standard32(struct v4l2_standard __user *p64,
+static int put_v4l2_standard32(struct v4l2_standard *p64,
struct v4l2_standard32 __user *p32)
{
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p32->index, &p64->index) ||
- assign_in_user(&p32->id, &p64->id) ||
- copy_in_user(p32->name, p64->name, sizeof(p32->name)) ||
- copy_in_user(&p32->frameperiod, &p64->frameperiod,
+ if (put_user(p64->index, &p32->index) ||
+ put_user(p64->id, &p32->id) ||
+ copy_to_user(p32->name, p64->name, sizeof(p32->name)) ||
+ copy_to_user(&p32->frameperiod, &p64->frameperiod,
sizeof(p32->frameperiod)) ||
- assign_in_user(&p32->framelines, &p64->framelines) ||
- copy_in_user(p32->reserved, p64->reserved, sizeof(p32->reserved)))
+ put_user(p64->framelines, &p32->framelines) ||
+ copy_to_user(p32->reserved, p64->reserved, sizeof(p32->reserved)))
return -EFAULT;
return 0;
}
@@ -498,6 +304,7 @@ struct v4l2_buffer32 {
__s32 request_fd;
};
+#ifdef CONFIG_COMPAT_32BIT_TIME
struct v4l2_buffer32_time32 {
__u32 index;
__u32 type; /* enum v4l2_buf_type */
@@ -520,481 +327,252 @@ struct v4l2_buffer32_time32 {
__u32 reserved2;
__s32 request_fd;
};
+#endif
-static int get_v4l2_plane32(struct v4l2_plane __user *p64,
+static int get_v4l2_plane32(struct v4l2_plane *p64,
struct v4l2_plane32 __user *p32,
enum v4l2_memory memory)
{
- compat_ulong_t p;
+ struct v4l2_plane32 plane32;
+ typeof(p64->m) m = {};
- if (copy_in_user(p64, p32, 2 * sizeof(__u32)) ||
- copy_in_user(&p64->data_offset, &p32->data_offset,
- sizeof(p64->data_offset)))
+ if (copy_from_user(&plane32, p32, sizeof(plane32)))
return -EFAULT;
switch (memory) {
case V4L2_MEMORY_MMAP:
case V4L2_MEMORY_OVERLAY:
- if (copy_in_user(&p64->m.mem_offset, &p32->m.mem_offset,
- sizeof(p32->m.mem_offset)))
- return -EFAULT;
+ m.mem_offset = plane32.m.mem_offset;
break;
case V4L2_MEMORY_USERPTR:
- if (get_user(p, &p32->m.userptr) ||
- put_user((unsigned long)compat_ptr(p), &p64->m.userptr))
- return -EFAULT;
+ m.userptr = (unsigned long)compat_ptr(plane32.m.userptr);
break;
case V4L2_MEMORY_DMABUF:
- if (copy_in_user(&p64->m.fd, &p32->m.fd, sizeof(p32->m.fd)))
- return -EFAULT;
+ m.fd = plane32.m.fd;
break;
}
+ memset(p64, 0, sizeof(*p64));
+ *p64 = (struct v4l2_plane) {
+ .bytesused = plane32.bytesused,
+ .length = plane32.length,
+ .m = m,
+ .data_offset = plane32.data_offset,
+ };
+
return 0;
}
-static int put_v4l2_plane32(struct v4l2_plane __user *p64,
+static int put_v4l2_plane32(struct v4l2_plane *p64,
struct v4l2_plane32 __user *p32,
enum v4l2_memory memory)
{
- unsigned long p;
+ struct v4l2_plane32 plane32;
- if (copy_in_user(p32, p64, 2 * sizeof(__u32)) ||
- copy_in_user(&p32->data_offset, &p64->data_offset,
- sizeof(p64->data_offset)))
- return -EFAULT;
+ memset(&plane32, 0, sizeof(plane32));
+ plane32 = (struct v4l2_plane32) {
+ .bytesused = p64->bytesused,
+ .length = p64->length,
+ .data_offset = p64->data_offset,
+ };
switch (memory) {
case V4L2_MEMORY_MMAP:
case V4L2_MEMORY_OVERLAY:
- if (copy_in_user(&p32->m.mem_offset, &p64->m.mem_offset,
- sizeof(p64->m.mem_offset)))
- return -EFAULT;
+ plane32.m.mem_offset = p64->m.mem_offset;
break;
case V4L2_MEMORY_USERPTR:
- if (get_user(p, &p64->m.userptr) ||
- put_user((compat_ulong_t)ptr_to_compat((void __user *)p),
- &p32->m.userptr))
- return -EFAULT;
+ plane32.m.userptr = (uintptr_t)(p64->m.userptr);
break;
case V4L2_MEMORY_DMABUF:
- if (copy_in_user(&p32->m.fd, &p64->m.fd, sizeof(p64->m.fd)))
- return -EFAULT;
+ plane32.m.fd = p64->m.fd;
break;
}
- return 0;
-}
-
-static int bufsize_v4l2_buffer(struct v4l2_buffer32 __user *p32, u32 *size)
-{
- u32 type;
- u32 length;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- get_user(type, &p32->type) ||
- get_user(length, &p32->length))
+ if (copy_to_user(p32, &plane32, sizeof(plane32)))
return -EFAULT;
- if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
- if (length > VIDEO_MAX_PLANES)
- return -EINVAL;
-
- /*
- * We don't really care if userspace decides to kill itself
- * by passing a very big length value
- */
- *size = length * sizeof(struct v4l2_plane);
- } else {
- *size = 0;
- }
return 0;
}
-static int bufsize_v4l2_buffer_time32(struct v4l2_buffer32_time32 __user *p32, u32 *size)
+static int get_v4l2_buffer32(struct v4l2_buffer *vb,
+ struct v4l2_buffer32 __user *arg)
{
- u32 type;
- u32 length;
+ struct v4l2_buffer32 vb32;
- if (!access_ok(p32, sizeof(*p32)) ||
- get_user(type, &p32->type) ||
- get_user(length, &p32->length))
+ if (copy_from_user(&vb32, arg, sizeof(vb32)))
return -EFAULT;
- if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
- if (length > VIDEO_MAX_PLANES)
- return -EINVAL;
+ memset(vb, 0, sizeof(*vb));
+ *vb = (struct v4l2_buffer) {
+ .index = vb32.index,
+ .type = vb32.type,
+ .bytesused = vb32.bytesused,
+ .flags = vb32.flags,
+ .field = vb32.field,
+ .timestamp.tv_sec = vb32.timestamp.tv_sec,
+ .timestamp.tv_usec = vb32.timestamp.tv_usec,
+ .timecode = vb32.timecode,
+ .sequence = vb32.sequence,
+ .memory = vb32.memory,
+ .m.offset = vb32.m.offset,
+ .length = vb32.length,
+ .request_fd = vb32.request_fd,
+ };
- /*
- * We don't really care if userspace decides to kill itself
- * by passing a very big length value
- */
- *size = length * sizeof(struct v4l2_plane);
- } else {
- *size = 0;
+ switch (vb->memory) {
+ case V4L2_MEMORY_MMAP:
+ case V4L2_MEMORY_OVERLAY:
+ vb->m.offset = vb32.m.offset;
+ break;
+ case V4L2_MEMORY_USERPTR:
+ vb->m.userptr = (unsigned long)compat_ptr(vb32.m.userptr);
+ break;
+ case V4L2_MEMORY_DMABUF:
+ vb->m.fd = vb32.m.fd;
+ break;
}
- return 0;
-}
-
-static int get_v4l2_buffer32(struct v4l2_buffer __user *p64,
- struct v4l2_buffer32 __user *p32,
- void __user *aux_buf, u32 aux_space)
-{
- u32 type;
- u32 length;
- s32 request_fd;
- enum v4l2_memory memory;
- struct v4l2_plane32 __user *uplane32;
- struct v4l2_plane __user *uplane;
- compat_caddr_t p;
- int ret;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p64->index, &p32->index) ||
- get_user(type, &p32->type) ||
- put_user(type, &p64->type) ||
- assign_in_user(&p64->flags, &p32->flags) ||
- get_user(memory, &p32->memory) ||
- put_user(memory, &p64->memory) ||
- get_user(length, &p32->length) ||
- put_user(length, &p64->length) ||
- get_user(request_fd, &p32->request_fd) ||
- put_user(request_fd, &p64->request_fd))
- return -EFAULT;
-
- if (V4L2_TYPE_IS_OUTPUT(type))
- if (assign_in_user(&p64->bytesused, &p32->bytesused) ||
- assign_in_user(&p64->field, &p32->field) ||
- assign_in_user(&p64->timestamp.tv_sec,
- &p32->timestamp.tv_sec) ||
- assign_in_user(&p64->timestamp.tv_usec,
- &p32->timestamp.tv_usec))
- return -EFAULT;
-
- if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
- u32 num_planes = length;
- if (num_planes == 0) {
- /*
- * num_planes == 0 is legal, e.g. when userspace doesn't
- * need planes array on DQBUF
- */
- return put_user(NULL, &p64->m.planes);
- }
- if (num_planes > VIDEO_MAX_PLANES)
- return -EINVAL;
-
- if (get_user(p, &p32->m.planes))
- return -EFAULT;
-
- uplane32 = compat_ptr(p);
- if (!access_ok(uplane32,
- num_planes * sizeof(*uplane32)))
- return -EFAULT;
-
- /*
- * We don't really care if userspace decides to kill itself
- * by passing a very big num_planes value
- */
- if (aux_space < num_planes * sizeof(*uplane))
- return -EFAULT;
-
- uplane = aux_buf;
- if (put_user_force(uplane, &p64->m.planes))
- return -EFAULT;
-
- while (num_planes--) {
- ret = get_v4l2_plane32(uplane, uplane32, memory);
- if (ret)
- return ret;
- uplane++;
- uplane32++;
- }
- } else {
- switch (memory) {
- case V4L2_MEMORY_MMAP:
- case V4L2_MEMORY_OVERLAY:
- if (assign_in_user(&p64->m.offset, &p32->m.offset))
- return -EFAULT;
- break;
- case V4L2_MEMORY_USERPTR: {
- compat_ulong_t userptr;
-
- if (get_user(userptr, &p32->m.userptr) ||
- put_user((unsigned long)compat_ptr(userptr),
- &p64->m.userptr))
- return -EFAULT;
- break;
- }
- case V4L2_MEMORY_DMABUF:
- if (assign_in_user(&p64->m.fd, &p32->m.fd))
- return -EFAULT;
- break;
- }
- }
+ if (V4L2_TYPE_IS_MULTIPLANAR(vb->type))
+ vb->m.planes = (void __force *)
+ compat_ptr(vb32.m.planes);
return 0;
}
-static int get_v4l2_buffer32_time32(struct v4l2_buffer_time32 __user *p64,
- struct v4l2_buffer32_time32 __user *p32,
- void __user *aux_buf, u32 aux_space)
+#ifdef CONFIG_COMPAT_32BIT_TIME
+static int get_v4l2_buffer32_time32(struct v4l2_buffer *vb,
+ struct v4l2_buffer32_time32 __user *arg)
{
- u32 type;
- u32 length;
- s32 request_fd;
- enum v4l2_memory memory;
- struct v4l2_plane32 __user *uplane32;
- struct v4l2_plane __user *uplane;
- compat_caddr_t p;
- int ret;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p64->index, &p32->index) ||
- get_user(type, &p32->type) ||
- put_user(type, &p64->type) ||
- assign_in_user(&p64->flags, &p32->flags) ||
- get_user(memory, &p32->memory) ||
- put_user(memory, &p64->memory) ||
- get_user(length, &p32->length) ||
- put_user(length, &p64->length) ||
- get_user(request_fd, &p32->request_fd) ||
- put_user(request_fd, &p64->request_fd))
- return -EFAULT;
+ struct v4l2_buffer32_time32 vb32;
- if (V4L2_TYPE_IS_OUTPUT(type))
- if (assign_in_user(&p64->bytesused, &p32->bytesused) ||
- assign_in_user(&p64->field, &p32->field) ||
- assign_in_user(&p64->timestamp.tv_sec,
- &p32->timestamp.tv_sec) ||
- assign_in_user(&p64->timestamp.tv_usec,
- &p32->timestamp.tv_usec))
- return -EFAULT;
-
- if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
- u32 num_planes = length;
-
- if (num_planes == 0) {
- /*
- * num_planes == 0 is legal, e.g. when userspace doesn't
- * need planes array on DQBUF
- */
- return put_user(NULL, &p64->m.planes);
- }
- if (num_planes > VIDEO_MAX_PLANES)
- return -EINVAL;
-
- if (get_user(p, &p32->m.planes))
- return -EFAULT;
-
- uplane32 = compat_ptr(p);
- if (!access_ok(uplane32,
- num_planes * sizeof(*uplane32)))
- return -EFAULT;
-
- /*
- * We don't really care if userspace decides to kill itself
- * by passing a very big num_planes value
- */
- if (aux_space < num_planes * sizeof(*uplane))
- return -EFAULT;
-
- uplane = aux_buf;
- if (put_user_force(uplane, &p64->m.planes))
- return -EFAULT;
-
- while (num_planes--) {
- ret = get_v4l2_plane32(uplane, uplane32, memory);
- if (ret)
- return ret;
- uplane++;
- uplane32++;
- }
- } else {
- switch (memory) {
- case V4L2_MEMORY_MMAP:
- case V4L2_MEMORY_OVERLAY:
- if (assign_in_user(&p64->m.offset, &p32->m.offset))
- return -EFAULT;
- break;
- case V4L2_MEMORY_USERPTR: {
- compat_ulong_t userptr;
+ if (copy_from_user(&vb32, arg, sizeof(vb32)))
+ return -EFAULT;
- if (get_user(userptr, &p32->m.userptr) ||
- put_user((unsigned long)compat_ptr(userptr),
- &p64->m.userptr))
- return -EFAULT;
- break;
- }
- case V4L2_MEMORY_DMABUF:
- if (assign_in_user(&p64->m.fd, &p32->m.fd))
- return -EFAULT;
- break;
- }
+ *vb = (struct v4l2_buffer) {
+ .index = vb32.index,
+ .type = vb32.type,
+ .bytesused = vb32.bytesused,
+ .flags = vb32.flags,
+ .field = vb32.field,
+ .timestamp.tv_sec = vb32.timestamp.tv_sec,
+ .timestamp.tv_usec = vb32.timestamp.tv_usec,
+ .timecode = vb32.timecode,
+ .sequence = vb32.sequence,
+ .memory = vb32.memory,
+ .m.offset = vb32.m.offset,
+ .length = vb32.length,
+ .request_fd = vb32.request_fd,
+ };
+ switch (vb->memory) {
+ case V4L2_MEMORY_MMAP:
+ case V4L2_MEMORY_OVERLAY:
+ vb->m.offset = vb32.m.offset;
+ break;
+ case V4L2_MEMORY_USERPTR:
+ vb->m.userptr = (unsigned long)compat_ptr(vb32.m.userptr);
+ break;
+ case V4L2_MEMORY_DMABUF:
+ vb->m.fd = vb32.m.fd;
+ break;
}
+ if (V4L2_TYPE_IS_MULTIPLANAR(vb->type))
+ vb->m.planes = (void __force *)
+ compat_ptr(vb32.m.planes);
+
return 0;
}
+#endif
-static int put_v4l2_buffer32(struct v4l2_buffer __user *p64,
- struct v4l2_buffer32 __user *p32)
+static int put_v4l2_buffer32(struct v4l2_buffer *vb,
+ struct v4l2_buffer32 __user *arg)
{
- u32 type;
- u32 length;
- enum v4l2_memory memory;
- struct v4l2_plane32 __user *uplane32;
- struct v4l2_plane *uplane;
- compat_caddr_t p;
- int ret;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p32->index, &p64->index) ||
- get_user(type, &p64->type) ||
- put_user(type, &p32->type) ||
- assign_in_user(&p32->flags, &p64->flags) ||
- get_user(memory, &p64->memory) ||
- put_user(memory, &p32->memory))
- return -EFAULT;
+ struct v4l2_buffer32 vb32;
+
+ memset(&vb32, 0, sizeof(vb32));
+ vb32 = (struct v4l2_buffer32) {
+ .index = vb->index,
+ .type = vb->type,
+ .bytesused = vb->bytesused,
+ .flags = vb->flags,
+ .field = vb->field,
+ .timestamp.tv_sec = vb->timestamp.tv_sec,
+ .timestamp.tv_usec = vb->timestamp.tv_usec,
+ .timecode = vb->timecode,
+ .sequence = vb->sequence,
+ .memory = vb->memory,
+ .m.offset = vb->m.offset,
+ .length = vb->length,
+ .request_fd = vb->request_fd,
+ };
- if (assign_in_user(&p32->bytesused, &p64->bytesused) ||
- assign_in_user(&p32->field, &p64->field) ||
- assign_in_user(&p32->timestamp.tv_sec, &p64->timestamp.tv_sec) ||
- assign_in_user(&p32->timestamp.tv_usec, &p64->timestamp.tv_usec) ||
- copy_in_user(&p32->timecode, &p64->timecode, sizeof(p64->timecode)) ||
- assign_in_user(&p32->sequence, &p64->sequence) ||
- assign_in_user(&p32->reserved2, &p64->reserved2) ||
- assign_in_user(&p32->request_fd, &p64->request_fd) ||
- get_user(length, &p64->length) ||
- put_user(length, &p32->length))
- return -EFAULT;
+ switch (vb->memory) {
+ case V4L2_MEMORY_MMAP:
+ case V4L2_MEMORY_OVERLAY:
+ vb32.m.offset = vb->m.offset;
+ break;
+ case V4L2_MEMORY_USERPTR:
+ vb32.m.userptr = (uintptr_t)(vb->m.userptr);
+ break;
+ case V4L2_MEMORY_DMABUF:
+ vb32.m.fd = vb->m.fd;
+ break;
+ }
- if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
- u32 num_planes = length;
+ if (V4L2_TYPE_IS_MULTIPLANAR(vb->type))
+ vb32.m.planes = (uintptr_t)vb->m.planes;
- if (num_planes == 0)
- return 0;
- /* We need to define uplane without __user, even though
- * it does point to data in userspace here. The reason is
- * that v4l2-ioctl.c copies it from userspace to kernelspace,
- * so its definition in videodev2.h doesn't have a
- * __user markup. Defining uplane with __user causes
- * smatch warnings, so instead declare it without __user
- * and cast it as a userspace pointer to put_v4l2_plane32().
- */
- if (get_user(uplane, &p64->m.planes))
- return -EFAULT;
- if (get_user(p, &p32->m.planes))
- return -EFAULT;
- uplane32 = compat_ptr(p);
-
- while (num_planes--) {
- ret = put_v4l2_plane32((void __user *)uplane,
- uplane32, memory);
- if (ret)
- return ret;
- ++uplane;
- ++uplane32;
- }
- } else {
- switch (memory) {
- case V4L2_MEMORY_MMAP:
- case V4L2_MEMORY_OVERLAY:
- if (assign_in_user(&p32->m.offset, &p64->m.offset))
- return -EFAULT;
- break;
- case V4L2_MEMORY_USERPTR:
- if (assign_in_user(&p32->m.userptr, &p64->m.userptr))
- return -EFAULT;
- break;
- case V4L2_MEMORY_DMABUF:
- if (assign_in_user(&p32->m.fd, &p64->m.fd))
- return -EFAULT;
- break;
- }
- }
+ if (copy_to_user(arg, &vb32, sizeof(vb32)))
+ return -EFAULT;
return 0;
}
-static int put_v4l2_buffer32_time32(struct v4l2_buffer_time32 __user *p64,
- struct v4l2_buffer32_time32 __user *p32)
+#ifdef CONFIG_COMPAT_32BIT_TIME
+static int put_v4l2_buffer32_time32(struct v4l2_buffer *vb,
+ struct v4l2_buffer32_time32 __user *arg)
{
- u32 type;
- u32 length;
- enum v4l2_memory memory;
- struct v4l2_plane32 __user *uplane32;
- struct v4l2_plane *uplane;
- compat_caddr_t p;
- int ret;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p32->index, &p64->index) ||
- get_user(type, &p64->type) ||
- put_user(type, &p32->type) ||
- assign_in_user(&p32->flags, &p64->flags) ||
- get_user(memory, &p64->memory) ||
- put_user(memory, &p32->memory))
- return -EFAULT;
-
- if (assign_in_user(&p32->bytesused, &p64->bytesused) ||
- assign_in_user(&p32->field, &p64->field) ||
- assign_in_user(&p32->timestamp.tv_sec, &p64->timestamp.tv_sec) ||
- assign_in_user(&p32->timestamp.tv_usec, &p64->timestamp.tv_usec) ||
- copy_in_user(&p32->timecode, &p64->timecode, sizeof(p64->timecode)) ||
- assign_in_user(&p32->sequence, &p64->sequence) ||
- assign_in_user(&p32->reserved2, &p64->reserved2) ||
- assign_in_user(&p32->request_fd, &p64->request_fd) ||
- get_user(length, &p64->length) ||
- put_user(length, &p32->length))
- return -EFAULT;
+ struct v4l2_buffer32_time32 vb32;
+
+ memset(&vb32, 0, sizeof(vb32));
+ vb32 = (struct v4l2_buffer32_time32) {
+ .index = vb->index,
+ .type = vb->type,
+ .bytesused = vb->bytesused,
+ .flags = vb->flags,
+ .field = vb->field,
+ .timestamp.tv_sec = vb->timestamp.tv_sec,
+ .timestamp.tv_usec = vb->timestamp.tv_usec,
+ .timecode = vb->timecode,
+ .sequence = vb->sequence,
+ .memory = vb->memory,
+ .m.offset = vb->m.offset,
+ .length = vb->length,
+ .request_fd = vb->request_fd,
+ };
+ switch (vb->memory) {
+ case V4L2_MEMORY_MMAP:
+ case V4L2_MEMORY_OVERLAY:
+ vb32.m.offset = vb->m.offset;
+ break;
+ case V4L2_MEMORY_USERPTR:
+ vb32.m.userptr = (uintptr_t)(vb->m.userptr);
+ break;
+ case V4L2_MEMORY_DMABUF:
+ vb32.m.fd = vb->m.fd;
+ break;
+ }
- if (V4L2_TYPE_IS_MULTIPLANAR(type)) {
- u32 num_planes = length;
+ if (V4L2_TYPE_IS_MULTIPLANAR(vb->type))
+ vb32.m.planes = (uintptr_t)vb->m.planes;
- if (num_planes == 0)
- return 0;
- /* We need to define uplane without __user, even though
- * it does point to data in userspace here. The reason is
- * that v4l2-ioctl.c copies it from userspace to kernelspace,
- * so its definition in videodev2.h doesn't have a
- * __user markup. Defining uplane with __user causes
- * smatch warnings, so instead declare it without __user
- * and cast it as a userspace pointer to put_v4l2_plane32().
- */
- if (get_user(uplane, &p64->m.planes))
- return -EFAULT;
- if (get_user(p, &p32->m.planes))
- return -EFAULT;
- uplane32 = compat_ptr(p);
-
- while (num_planes--) {
- ret = put_v4l2_plane32((void __user *)uplane,
- uplane32, memory);
- if (ret)
- return ret;
- ++uplane;
- ++uplane32;
- }
- } else {
- switch (memory) {
- case V4L2_MEMORY_MMAP:
- case V4L2_MEMORY_OVERLAY:
- if (assign_in_user(&p32->m.offset, &p64->m.offset))
- return -EFAULT;
- break;
- case V4L2_MEMORY_USERPTR:
- if (assign_in_user(&p32->m.userptr, &p64->m.userptr))
- return -EFAULT;
- break;
- case V4L2_MEMORY_DMABUF:
- if (assign_in_user(&p32->m.fd, &p64->m.fd))
- return -EFAULT;
- break;
- }
- }
+ if (copy_to_user(arg, &vb32, sizeof(vb32)))
+ return -EFAULT;
return 0;
}
+#endif
struct v4l2_framebuffer32 {
__u32 capability;
@@ -1012,33 +590,30 @@ struct v4l2_framebuffer32 {
} fmt;
};
-static int get_v4l2_framebuffer32(struct v4l2_framebuffer __user *p64,
+static int get_v4l2_framebuffer32(struct v4l2_framebuffer *p64,
struct v4l2_framebuffer32 __user *p32)
{
compat_caddr_t tmp;
- if (!access_ok(p32, sizeof(*p32)) ||
- get_user(tmp, &p32->base) ||
- put_user_force(compat_ptr(tmp), &p64->base) ||
- assign_in_user(&p64->capability, &p32->capability) ||
- assign_in_user(&p64->flags, &p32->flags) ||
- copy_in_user(&p64->fmt, &p32->fmt, sizeof(p64->fmt)))
+ if (get_user(tmp, &p32->base) ||
+ get_user(p64->capability, &p32->capability) ||
+ get_user(p64->flags, &p32->flags) ||
+ copy_from_user(&p64->fmt, &p32->fmt, sizeof(p64->fmt)))
return -EFAULT;
+ p64->base = (void __force *)compat_ptr(tmp);
+
return 0;
}
-static int put_v4l2_framebuffer32(struct v4l2_framebuffer __user *p64,
+static int put_v4l2_framebuffer32(struct v4l2_framebuffer *p64,
struct v4l2_framebuffer32 __user *p32)
{
- void *base;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- get_user(base, &p64->base) ||
- put_user(ptr_to_compat((void __user *)base), &p32->base) ||
- assign_in_user(&p32->capability, &p64->capability) ||
- assign_in_user(&p32->flags, &p64->flags) ||
- copy_in_user(&p32->fmt, &p64->fmt, sizeof(p64->fmt)))
+ if (put_user((uintptr_t)p64->base, &p32->base) ||
+ put_user(p64->capability, &p32->capability) ||
+ put_user(p64->flags, &p32->flags) ||
+ copy_to_user(&p32->fmt, &p64->fmt, sizeof(p64->fmt)))
return -EFAULT;
+
return 0;
}
@@ -1058,18 +633,18 @@ struct v4l2_input32 {
* The 64-bit v4l2_input struct has extra padding at the end of the struct.
* Otherwise it is identical to the 32-bit version.
*/
-static inline int get_v4l2_input32(struct v4l2_input __user *p64,
+static inline int get_v4l2_input32(struct v4l2_input *p64,
struct v4l2_input32 __user *p32)
{
- if (copy_in_user(p64, p32, sizeof(*p32)))
+ if (copy_from_user(p64, p32, sizeof(*p32)))
return -EFAULT;
return 0;
}
-static inline int put_v4l2_input32(struct v4l2_input __user *p64,
+static inline int put_v4l2_input32(struct v4l2_input *p64,
struct v4l2_input32 __user *p32)
{
- if (copy_in_user(p32, p64, sizeof(*p32)))
+ if (copy_to_user(p32, p64, sizeof(*p32)))
return -EFAULT;
return 0;
}
@@ -1124,142 +699,44 @@ static inline bool ctrl_is_pointer(struct file *file, u32 id)
(qec.flags & V4L2_CTRL_FLAG_HAS_PAYLOAD);
}
-static int bufsize_v4l2_ext_controls(struct v4l2_ext_controls32 __user *p32,
- u32 *size)
-{
- u32 count;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- get_user(count, &p32->count))
- return -EFAULT;
- if (count > V4L2_CID_MAX_CTRLS)
- return -EINVAL;
- *size = count * sizeof(struct v4l2_ext_control);
- return 0;
-}
-
-static int get_v4l2_ext_controls32(struct file *file,
- struct v4l2_ext_controls __user *p64,
- struct v4l2_ext_controls32 __user *p32,
- void __user *aux_buf, u32 aux_space)
+static int get_v4l2_ext_controls32(struct v4l2_ext_controls *p64,
+ struct v4l2_ext_controls32 __user *p32)
{
- struct v4l2_ext_control32 __user *ucontrols;
- struct v4l2_ext_control __user *kcontrols;
- u32 count;
- u32 n;
- compat_caddr_t p;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p64->which, &p32->which) ||
- get_user(count, &p32->count) ||
- put_user(count, &p64->count) ||
- assign_in_user(&p64->error_idx, &p32->error_idx) ||
- assign_in_user(&p64->request_fd, &p32->request_fd) ||
- copy_in_user(p64->reserved, p32->reserved, sizeof(p64->reserved)))
- return -EFAULT;
+ struct v4l2_ext_controls32 ec32;
- if (count == 0)
- return put_user(NULL, &p64->controls);
- if (count > V4L2_CID_MAX_CTRLS)
- return -EINVAL;
- if (get_user(p, &p32->controls))
- return -EFAULT;
- ucontrols = compat_ptr(p);
- if (!access_ok(ucontrols, count * sizeof(*ucontrols)))
+ if (copy_from_user(&ec32, p32, sizeof(ec32)))
return -EFAULT;
- if (aux_space < count * sizeof(*kcontrols))
- return -EFAULT;
- kcontrols = aux_buf;
- if (put_user_force(kcontrols, &p64->controls))
- return -EFAULT;
-
- for (n = 0; n < count; n++) {
- u32 id;
-
- if (copy_in_user(kcontrols, ucontrols, sizeof(*ucontrols)))
- return -EFAULT;
- if (get_user(id, &kcontrols->id))
- return -EFAULT;
-
- if (ctrl_is_pointer(file, id)) {
- void __user *s;
+ *p64 = (struct v4l2_ext_controls) {
+ .which = ec32.which,
+ .count = ec32.count,
+ .error_idx = ec32.error_idx,
+ .request_fd = ec32.request_fd,
+ .reserved[0] = ec32.reserved[0],
+ .controls = (void __force *)compat_ptr(ec32.controls),
+ };
- if (get_user(p, &ucontrols->string))
- return -EFAULT;
- s = compat_ptr(p);
- if (put_user(s, &kcontrols->string))
- return -EFAULT;
- }
- ucontrols++;
- kcontrols++;
- }
return 0;
}
-static int put_v4l2_ext_controls32(struct file *file,
- struct v4l2_ext_controls __user *p64,
+static int put_v4l2_ext_controls32(struct v4l2_ext_controls *p64,
struct v4l2_ext_controls32 __user *p32)
{
- struct v4l2_ext_control32 __user *ucontrols;
- struct v4l2_ext_control *kcontrols;
- u32 count;
- u32 n;
- compat_caddr_t p;
-
- /*
- * We need to define kcontrols without __user, even though it does
- * point to data in userspace here. The reason is that v4l2-ioctl.c
- * copies it from userspace to kernelspace, so its definition in
- * videodev2.h doesn't have a __user markup. Defining kcontrols
- * with __user causes smatch warnings, so instead declare it
- * without __user and cast it as a userspace pointer where needed.
- */
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p32->which, &p64->which) ||
- get_user(count, &p64->count) ||
- put_user(count, &p32->count) ||
- assign_in_user(&p32->error_idx, &p64->error_idx) ||
- assign_in_user(&p32->request_fd, &p64->request_fd) ||
- copy_in_user(p32->reserved, p64->reserved, sizeof(p32->reserved)) ||
- get_user(kcontrols, &p64->controls))
- return -EFAULT;
+ struct v4l2_ext_controls32 ec32;
+
+ memset(&ec32, 0, sizeof(ec32));
+ ec32 = (struct v4l2_ext_controls32) {
+ .which = p64->which,
+ .count = p64->count,
+ .error_idx = p64->error_idx,
+ .request_fd = p64->request_fd,
+ .reserved[0] = p64->reserved[0],
+ .controls = (uintptr_t)p64->controls,
+ };
- if (!count || count > (U32_MAX/sizeof(*ucontrols)))
- return 0;
- if (get_user(p, &p32->controls))
- return -EFAULT;
- ucontrols = compat_ptr(p);
- if (!access_ok(ucontrols, count * sizeof(*ucontrols)))
+ if (copy_to_user(p32, &ec32, sizeof(ec32)))
return -EFAULT;
- for (n = 0; n < count; n++) {
- unsigned int size = sizeof(*ucontrols);
- u32 id;
-
- if (get_user_cast(id, &kcontrols->id) ||
- put_user(id, &ucontrols->id) ||
- assign_in_user_cast(&ucontrols->size, &kcontrols->size) ||
- copy_in_user(&ucontrols->reserved2,
- (void __user *)&kcontrols->reserved2,
- sizeof(ucontrols->reserved2)))
- return -EFAULT;
-
- /*
- * Do not modify the pointer when copying a pointer control.
- * The contents of the pointer was changed, not the pointer
- * itself.
- */
- if (ctrl_is_pointer(file, id))
- size -= sizeof(ucontrols->value64);
-
- if (copy_in_user(ucontrols,
- (void __user *)kcontrols, size))
- return -EFAULT;
-
- ucontrols++;
- kcontrols++;
- }
return 0;
}
@@ -1288,6 +765,7 @@ struct v4l2_event32 {
__u32 reserved[8];
};
+#ifdef CONFIG_COMPAT_32BIT_TIME
struct v4l2_event32_time32 {
__u32 type;
union {
@@ -1300,39 +778,40 @@ struct v4l2_event32_time32 {
__u32 id;
__u32 reserved[8];
};
+#endif
-static int put_v4l2_event32(struct v4l2_event __user *p64,
+static int put_v4l2_event32(struct v4l2_event *p64,
struct v4l2_event32 __user *p32)
{
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p32->type, &p64->type) ||
- copy_in_user(&p32->u, &p64->u, sizeof(p64->u)) ||
- assign_in_user(&p32->pending, &p64->pending) ||
- assign_in_user(&p32->sequence, &p64->sequence) ||
- assign_in_user(&p32->timestamp.tv_sec, &p64->timestamp.tv_sec) ||
- assign_in_user(&p32->timestamp.tv_nsec, &p64->timestamp.tv_nsec) ||
- assign_in_user(&p32->id, &p64->id) ||
- copy_in_user(p32->reserved, p64->reserved, sizeof(p32->reserved)))
+ if (put_user(p64->type, &p32->type) ||
+ copy_to_user(&p32->u, &p64->u, sizeof(p64->u)) ||
+ put_user(p64->pending, &p32->pending) ||
+ put_user(p64->sequence, &p32->sequence) ||
+ put_user(p64->timestamp.tv_sec, &p32->timestamp.tv_sec) ||
+ put_user(p64->timestamp.tv_nsec, &p32->timestamp.tv_nsec) ||
+ put_user(p64->id, &p32->id) ||
+ copy_to_user(p32->reserved, p64->reserved, sizeof(p32->reserved)))
return -EFAULT;
return 0;
}
-static int put_v4l2_event32_time32(struct v4l2_event_time32 __user *p64,
+#ifdef CONFIG_COMPAT_32BIT_TIME
+static int put_v4l2_event32_time32(struct v4l2_event *p64,
struct v4l2_event32_time32 __user *p32)
{
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p32->type, &p64->type) ||
- copy_in_user(&p32->u, &p64->u, sizeof(p64->u)) ||
- assign_in_user(&p32->pending, &p64->pending) ||
- assign_in_user(&p32->sequence, &p64->sequence) ||
- assign_in_user(&p32->timestamp.tv_sec, &p64->timestamp.tv_sec) ||
- assign_in_user(&p32->timestamp.tv_nsec, &p64->timestamp.tv_nsec) ||
- assign_in_user(&p32->id, &p64->id) ||
- copy_in_user(p32->reserved, p64->reserved, sizeof(p32->reserved)))
+ if (put_user(p64->type, &p32->type) ||
+ copy_to_user(&p32->u, &p64->u, sizeof(p64->u)) ||
+ put_user(p64->pending, &p32->pending) ||
+ put_user(p64->sequence, &p32->sequence) ||
+ put_user(p64->timestamp.tv_sec, &p32->timestamp.tv_sec) ||
+ put_user(p64->timestamp.tv_nsec, &p32->timestamp.tv_nsec) ||
+ put_user(p64->id, &p32->id) ||
+ copy_to_user(p32->reserved, p64->reserved, sizeof(p32->reserved)))
return -EFAULT;
return 0;
}
#endif
+#endif
struct v4l2_edid32 {
__u32 pad;
@@ -1342,34 +821,23 @@ struct v4l2_edid32 {
compat_caddr_t edid;
};
-static int get_v4l2_edid32(struct v4l2_edid __user *p64,
+static int get_v4l2_edid32(struct v4l2_edid *p64,
struct v4l2_edid32 __user *p32)
{
- compat_uptr_t tmp;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p64->pad, &p32->pad) ||
- assign_in_user(&p64->start_block, &p32->start_block) ||
- assign_in_user_cast(&p64->blocks, &p32->blocks) ||
- get_user(tmp, &p32->edid) ||
- put_user_force(compat_ptr(tmp), &p64->edid) ||
- copy_in_user(p64->reserved, p32->reserved, sizeof(p64->reserved)))
+ compat_uptr_t edid;
+
+ if (copy_from_user(p64, p32, offsetof(struct v4l2_edid32, edid)) ||
+ get_user(edid, &p32->edid))
return -EFAULT;
+
+ p64->edid = (void __force *)compat_ptr(edid);
return 0;
}
-static int put_v4l2_edid32(struct v4l2_edid __user *p64,
+static int put_v4l2_edid32(struct v4l2_edid *p64,
struct v4l2_edid32 __user *p32)
{
- void *edid;
-
- if (!access_ok(p32, sizeof(*p32)) ||
- assign_in_user(&p32->pad, &p64->pad) ||
- assign_in_user(&p32->start_block, &p64->start_block) ||
- assign_in_user(&p32->blocks, &p64->blocks) ||
- get_user(edid, &p64->edid) ||
- put_user(ptr_to_compat((void __user *)edid), &p32->edid) ||
- copy_in_user(p32->reserved, p64->reserved, sizeof(p32->reserved)))
+ if (copy_to_user(p32, p64, offsetof(struct v4l2_edid32, edid)))
return -EFAULT;
return 0;
}
@@ -1385,13 +853,10 @@ static int put_v4l2_edid32(struct v4l2_edid __user *p64,
#define VIDIOC_G_FMT32 _IOWR('V', 4, struct v4l2_format32)
#define VIDIOC_S_FMT32 _IOWR('V', 5, struct v4l2_format32)
#define VIDIOC_QUERYBUF32 _IOWR('V', 9, struct v4l2_buffer32)
-#define VIDIOC_QUERYBUF32_TIME32 _IOWR('V', 9, struct v4l2_buffer32_time32)
#define VIDIOC_G_FBUF32 _IOR ('V', 10, struct v4l2_framebuffer32)
#define VIDIOC_S_FBUF32 _IOW ('V', 11, struct v4l2_framebuffer32)
#define VIDIOC_QBUF32 _IOWR('V', 15, struct v4l2_buffer32)
-#define VIDIOC_QBUF32_TIME32 _IOWR('V', 15, struct v4l2_buffer32_time32)
#define VIDIOC_DQBUF32 _IOWR('V', 17, struct v4l2_buffer32)
-#define VIDIOC_DQBUF32_TIME32 _IOWR('V', 17, struct v4l2_buffer32_time32)
#define VIDIOC_ENUMSTD32 _IOWR('V', 25, struct v4l2_standard32)
#define VIDIOC_ENUMINPUT32 _IOWR('V', 26, struct v4l2_input32)
#define VIDIOC_G_EDID32 _IOWR('V', 40, struct v4l2_edid32)
@@ -1401,366 +866,359 @@ static int put_v4l2_edid32(struct v4l2_edid __user *p64,
#define VIDIOC_S_EXT_CTRLS32 _IOWR('V', 72, struct v4l2_ext_controls32)
#define VIDIOC_TRY_EXT_CTRLS32 _IOWR('V', 73, struct v4l2_ext_controls32)
#define VIDIOC_DQEVENT32 _IOR ('V', 89, struct v4l2_event32)
-#define VIDIOC_DQEVENT32_TIME32 _IOR ('V', 89, struct v4l2_event32_time32)
#define VIDIOC_CREATE_BUFS32 _IOWR('V', 92, struct v4l2_create_buffers32)
#define VIDIOC_PREPARE_BUF32 _IOWR('V', 93, struct v4l2_buffer32)
-#define VIDIOC_PREPARE_BUF32_TIME32 _IOWR('V', 93, struct v4l2_buffer32_time32)
-#define VIDIOC_OVERLAY32 _IOW ('V', 14, s32)
-#define VIDIOC_STREAMON32 _IOW ('V', 18, s32)
-#define VIDIOC_STREAMOFF32 _IOW ('V', 19, s32)
-#define VIDIOC_G_INPUT32 _IOR ('V', 38, s32)
-#define VIDIOC_S_INPUT32 _IOWR('V', 39, s32)
-#define VIDIOC_G_OUTPUT32 _IOR ('V', 46, s32)
-#define VIDIOC_S_OUTPUT32 _IOWR('V', 47, s32)
-
-/**
- * alloc_userspace() - Allocates a 64-bits userspace pointer compatible
- * for calling the native 64-bits version of an ioctl.
- *
- * @size: size of the structure itself to be allocated.
- * @aux_space: extra size needed to store "extra" data, e.g. space for
- * other __user data that is pointed to fields inside the
- * structure.
- * @new_p64: pointer to a pointer to be filled with the allocated struct.
- *
- * Return:
- *
- * if it can't allocate memory, either -ENOMEM or -EFAULT will be returned.
- * Zero otherwise.
- */
-static int alloc_userspace(unsigned int size, u32 aux_space,
- void __user **new_p64)
-{
- *new_p64 = compat_alloc_user_space(size + aux_space);
- if (!*new_p64)
- return -ENOMEM;
- if (clear_user(*new_p64, size))
- return -EFAULT;
- return 0;
-}
+#ifdef CONFIG_COMPAT_32BIT_TIME
+#define VIDIOC_QUERYBUF32_TIME32 _IOWR('V', 9, struct v4l2_buffer32_time32)
+#define VIDIOC_QBUF32_TIME32 _IOWR('V', 15, struct v4l2_buffer32_time32)
+#define VIDIOC_DQBUF32_TIME32 _IOWR('V', 17, struct v4l2_buffer32_time32)
+#ifdef CONFIG_X86_64
+#define VIDIOC_DQEVENT32_TIME32 _IOR ('V', 89, struct v4l2_event32_time32)
+#endif
+#define VIDIOC_PREPARE_BUF32_TIME32 _IOWR('V', 93, struct v4l2_buffer32_time32)
+#endif
-/**
- * do_video_ioctl() - Ancillary function with handles a compat32 ioctl call
- *
- * @file: pointer to &struct file with the file handler
- * @cmd: ioctl to be called
- * @arg: arguments passed from/to the ioctl handler
- *
- * This function is called when a 32 bits application calls a V4L2 ioctl
- * and the Kernel is compiled with 64 bits.
- *
- * This function is called by v4l2_compat_ioctl32() when the function is
- * not private to some specific driver.
- *
- * It converts a 32-bits struct into a 64 bits one, calls the native 64-bits
- * ioctl handler and fills back the 32-bits struct with the results of the
- * native call.
- */
-static long do_video_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+unsigned int v4l2_compat_translate_cmd(unsigned int cmd)
{
- void __user *p32 = compat_ptr(arg);
- void __user *new_p64 = NULL;
- void __user *aux_buf;
- u32 aux_space;
- int compatible_arg = 1;
- long err = 0;
- unsigned int ncmd;
-
- /*
- * 1. When struct size is different, converts the command.
- */
switch (cmd) {
- case VIDIOC_G_FMT32: ncmd = VIDIOC_G_FMT; break;
- case VIDIOC_S_FMT32: ncmd = VIDIOC_S_FMT; break;
- case VIDIOC_QUERYBUF32: ncmd = VIDIOC_QUERYBUF; break;
- case VIDIOC_QUERYBUF32_TIME32: ncmd = VIDIOC_QUERYBUF_TIME32; break;
- case VIDIOC_G_FBUF32: ncmd = VIDIOC_G_FBUF; break;
- case VIDIOC_S_FBUF32: ncmd = VIDIOC_S_FBUF; break;
- case VIDIOC_QBUF32: ncmd = VIDIOC_QBUF; break;
- case VIDIOC_QBUF32_TIME32: ncmd = VIDIOC_QBUF_TIME32; break;
- case VIDIOC_DQBUF32: ncmd = VIDIOC_DQBUF; break;
- case VIDIOC_DQBUF32_TIME32: ncmd = VIDIOC_DQBUF_TIME32; break;
- case VIDIOC_ENUMSTD32: ncmd = VIDIOC_ENUMSTD; break;
- case VIDIOC_ENUMINPUT32: ncmd = VIDIOC_ENUMINPUT; break;
- case VIDIOC_TRY_FMT32: ncmd = VIDIOC_TRY_FMT; break;
- case VIDIOC_G_EXT_CTRLS32: ncmd = VIDIOC_G_EXT_CTRLS; break;
- case VIDIOC_S_EXT_CTRLS32: ncmd = VIDIOC_S_EXT_CTRLS; break;
- case VIDIOC_TRY_EXT_CTRLS32: ncmd = VIDIOC_TRY_EXT_CTRLS; break;
+ case VIDIOC_G_FMT32:
+ return VIDIOC_G_FMT;
+ case VIDIOC_S_FMT32:
+ return VIDIOC_S_FMT;
+ case VIDIOC_TRY_FMT32:
+ return VIDIOC_TRY_FMT;
+ case VIDIOC_G_FBUF32:
+ return VIDIOC_G_FBUF;
+ case VIDIOC_S_FBUF32:
+ return VIDIOC_S_FBUF;
+#ifdef CONFIG_COMPAT_32BIT_TIME
+ case VIDIOC_QUERYBUF32_TIME32:
+ return VIDIOC_QUERYBUF;
+ case VIDIOC_QBUF32_TIME32:
+ return VIDIOC_QBUF;
+ case VIDIOC_DQBUF32_TIME32:
+ return VIDIOC_DQBUF;
+ case VIDIOC_PREPARE_BUF32_TIME32:
+ return VIDIOC_PREPARE_BUF;
+#endif
+ case VIDIOC_QUERYBUF32:
+ return VIDIOC_QUERYBUF;
+ case VIDIOC_QBUF32:
+ return VIDIOC_QBUF;
+ case VIDIOC_DQBUF32:
+ return VIDIOC_DQBUF;
+ case VIDIOC_CREATE_BUFS32:
+ return VIDIOC_CREATE_BUFS;
+ case VIDIOC_G_EXT_CTRLS32:
+ return VIDIOC_G_EXT_CTRLS;
+ case VIDIOC_S_EXT_CTRLS32:
+ return VIDIOC_S_EXT_CTRLS;
+ case VIDIOC_TRY_EXT_CTRLS32:
+ return VIDIOC_TRY_EXT_CTRLS;
+ case VIDIOC_PREPARE_BUF32:
+ return VIDIOC_PREPARE_BUF;
+ case VIDIOC_ENUMSTD32:
+ return VIDIOC_ENUMSTD;
+ case VIDIOC_ENUMINPUT32:
+ return VIDIOC_ENUMINPUT;
+ case VIDIOC_G_EDID32:
+ return VIDIOC_G_EDID;
+ case VIDIOC_S_EDID32:
+ return VIDIOC_S_EDID;
#ifdef CONFIG_X86_64
- case VIDIOC_DQEVENT32: ncmd = VIDIOC_DQEVENT; break;
- case VIDIOC_DQEVENT32_TIME32: ncmd = VIDIOC_DQEVENT_TIME32; break;
+ case VIDIOC_DQEVENT32:
+ return VIDIOC_DQEVENT;
+#ifdef CONFIG_COMPAT_32BIT_TIME
+ case VIDIOC_DQEVENT32_TIME32:
+ return VIDIOC_DQEVENT;
+#endif
#endif
- case VIDIOC_OVERLAY32: ncmd = VIDIOC_OVERLAY; break;
- case VIDIOC_STREAMON32: ncmd = VIDIOC_STREAMON; break;
- case VIDIOC_STREAMOFF32: ncmd = VIDIOC_STREAMOFF; break;
- case VIDIOC_G_INPUT32: ncmd = VIDIOC_G_INPUT; break;
- case VIDIOC_S_INPUT32: ncmd = VIDIOC_S_INPUT; break;
- case VIDIOC_G_OUTPUT32: ncmd = VIDIOC_G_OUTPUT; break;
- case VIDIOC_S_OUTPUT32: ncmd = VIDIOC_S_OUTPUT; break;
- case VIDIOC_CREATE_BUFS32: ncmd = VIDIOC_CREATE_BUFS; break;
- case VIDIOC_PREPARE_BUF32: ncmd = VIDIOC_PREPARE_BUF; break;
- case VIDIOC_PREPARE_BUF32_TIME32: ncmd = VIDIOC_PREPARE_BUF_TIME32; break;
- case VIDIOC_G_EDID32: ncmd = VIDIOC_G_EDID; break;
- case VIDIOC_S_EDID32: ncmd = VIDIOC_S_EDID; break;
- default: ncmd = cmd; break;
}
+ return cmd;
+}
- /*
- * 2. Allocates a 64-bits userspace pointer to store the
- * values of the ioctl and copy data from the 32-bits __user
- * argument into it.
- */
+int v4l2_compat_get_user(void __user *arg, void *parg, unsigned int cmd)
+{
switch (cmd) {
- case VIDIOC_OVERLAY32:
- case VIDIOC_STREAMON32:
- case VIDIOC_STREAMOFF32:
- case VIDIOC_S_INPUT32:
- case VIDIOC_S_OUTPUT32:
- err = alloc_userspace(sizeof(unsigned int), 0, &new_p64);
- if (!err && assign_in_user((unsigned int __user *)new_p64,
- (compat_uint_t __user *)p32))
- err = -EFAULT;
- compatible_arg = 0;
- break;
+ case VIDIOC_G_FMT32:
+ case VIDIOC_S_FMT32:
+ case VIDIOC_TRY_FMT32:
+ return get_v4l2_format32(parg, arg);
- case VIDIOC_G_INPUT32:
- case VIDIOC_G_OUTPUT32:
- err = alloc_userspace(sizeof(unsigned int), 0, &new_p64);
- compatible_arg = 0;
- break;
+ case VIDIOC_S_FBUF32:
+ return get_v4l2_framebuffer32(parg, arg);
+#ifdef CONFIG_COMPAT_32BIT_TIME
+ case VIDIOC_QUERYBUF32_TIME32:
+ case VIDIOC_QBUF32_TIME32:
+ case VIDIOC_DQBUF32_TIME32:
+ case VIDIOC_PREPARE_BUF32_TIME32:
+ return get_v4l2_buffer32_time32(parg, arg);
+#endif
+ case VIDIOC_QUERYBUF32:
+ case VIDIOC_QBUF32:
+ case VIDIOC_DQBUF32:
+ case VIDIOC_PREPARE_BUF32:
+ return get_v4l2_buffer32(parg, arg);
+
+ case VIDIOC_G_EXT_CTRLS32:
+ case VIDIOC_S_EXT_CTRLS32:
+ case VIDIOC_TRY_EXT_CTRLS32:
+ return get_v4l2_ext_controls32(parg, arg);
+
+ case VIDIOC_CREATE_BUFS32:
+ return get_v4l2_create32(parg, arg);
+
+ case VIDIOC_ENUMSTD32:
+ return get_v4l2_standard32(parg, arg);
+
+ case VIDIOC_ENUMINPUT32:
+ return get_v4l2_input32(parg, arg);
case VIDIOC_G_EDID32:
case VIDIOC_S_EDID32:
- err = alloc_userspace(sizeof(struct v4l2_edid), 0, &new_p64);
- if (!err)
- err = get_v4l2_edid32(new_p64, p32);
- compatible_arg = 0;
- break;
+ return get_v4l2_edid32(parg, arg);
+ }
+ return 0;
+}
+int v4l2_compat_put_user(void __user *arg, void *parg, unsigned int cmd)
+{
+ switch (cmd) {
case VIDIOC_G_FMT32:
case VIDIOC_S_FMT32:
case VIDIOC_TRY_FMT32:
- err = bufsize_v4l2_format(p32, &aux_space);
- if (!err)
- err = alloc_userspace(sizeof(struct v4l2_format),
- aux_space, &new_p64);
- if (!err) {
- aux_buf = new_p64 + sizeof(struct v4l2_format);
- err = get_v4l2_format32(new_p64, p32,
- aux_buf, aux_space);
- }
- compatible_arg = 0;
- break;
-
- case VIDIOC_CREATE_BUFS32:
- err = bufsize_v4l2_create(p32, &aux_space);
- if (!err)
- err = alloc_userspace(sizeof(struct v4l2_create_buffers),
- aux_space, &new_p64);
- if (!err) {
- aux_buf = new_p64 + sizeof(struct v4l2_create_buffers);
- err = get_v4l2_create32(new_p64, p32,
- aux_buf, aux_space);
- }
- compatible_arg = 0;
- break;
+ return put_v4l2_format32(parg, arg);
- case VIDIOC_PREPARE_BUF32:
- case VIDIOC_QUERYBUF32:
- case VIDIOC_QBUF32:
- case VIDIOC_DQBUF32:
- err = bufsize_v4l2_buffer(p32, &aux_space);
- if (!err)
- err = alloc_userspace(sizeof(struct v4l2_buffer),
- aux_space, &new_p64);
- if (!err) {
- aux_buf = new_p64 + sizeof(struct v4l2_buffer);
- err = get_v4l2_buffer32(new_p64, p32,
- aux_buf, aux_space);
- }
- compatible_arg = 0;
- break;
-
- case VIDIOC_PREPARE_BUF32_TIME32:
+ case VIDIOC_G_FBUF32:
+ return put_v4l2_framebuffer32(parg, arg);
+#ifdef CONFIG_COMPAT_32BIT_TIME
case VIDIOC_QUERYBUF32_TIME32:
case VIDIOC_QBUF32_TIME32:
case VIDIOC_DQBUF32_TIME32:
- err = bufsize_v4l2_buffer_time32(p32, &aux_space);
- if (!err)
- err = alloc_userspace(sizeof(struct v4l2_buffer),
- aux_space, &new_p64);
- if (!err) {
- aux_buf = new_p64 + sizeof(struct v4l2_buffer);
- err = get_v4l2_buffer32_time32(new_p64, p32,
- aux_buf, aux_space);
- }
- compatible_arg = 0;
- break;
+ case VIDIOC_PREPARE_BUF32_TIME32:
+ return put_v4l2_buffer32_time32(parg, arg);
+#endif
+ case VIDIOC_QUERYBUF32:
+ case VIDIOC_QBUF32:
+ case VIDIOC_DQBUF32:
+ case VIDIOC_PREPARE_BUF32:
+ return put_v4l2_buffer32(parg, arg);
- case VIDIOC_S_FBUF32:
- err = alloc_userspace(sizeof(struct v4l2_framebuffer), 0,
- &new_p64);
- if (!err)
- err = get_v4l2_framebuffer32(new_p64, p32);
- compatible_arg = 0;
- break;
+ case VIDIOC_G_EXT_CTRLS32:
+ case VIDIOC_S_EXT_CTRLS32:
+ case VIDIOC_TRY_EXT_CTRLS32:
+ return put_v4l2_ext_controls32(parg, arg);
- case VIDIOC_G_FBUF32:
- err = alloc_userspace(sizeof(struct v4l2_framebuffer), 0,
- &new_p64);
- compatible_arg = 0;
- break;
+ case VIDIOC_CREATE_BUFS32:
+ return put_v4l2_create32(parg, arg);
case VIDIOC_ENUMSTD32:
- err = alloc_userspace(sizeof(struct v4l2_standard), 0,
- &new_p64);
- if (!err)
- err = get_v4l2_standard32(new_p64, p32);
- compatible_arg = 0;
- break;
+ return put_v4l2_standard32(parg, arg);
case VIDIOC_ENUMINPUT32:
- err = alloc_userspace(sizeof(struct v4l2_input), 0, &new_p64);
- if (!err)
- err = get_v4l2_input32(new_p64, p32);
- compatible_arg = 0;
- break;
+ return put_v4l2_input32(parg, arg);
- case VIDIOC_G_EXT_CTRLS32:
- case VIDIOC_S_EXT_CTRLS32:
- case VIDIOC_TRY_EXT_CTRLS32:
- err = bufsize_v4l2_ext_controls(p32, &aux_space);
- if (!err)
- err = alloc_userspace(sizeof(struct v4l2_ext_controls),
- aux_space, &new_p64);
- if (!err) {
- aux_buf = new_p64 + sizeof(struct v4l2_ext_controls);
- err = get_v4l2_ext_controls32(file, new_p64, p32,
- aux_buf, aux_space);
- }
- compatible_arg = 0;
- break;
+ case VIDIOC_G_EDID32:
+ case VIDIOC_S_EDID32:
+ return put_v4l2_edid32(parg, arg);
#ifdef CONFIG_X86_64
case VIDIOC_DQEVENT32:
- err = alloc_userspace(sizeof(struct v4l2_event), 0, &new_p64);
- compatible_arg = 0;
- break;
+ return put_v4l2_event32(parg, arg);
+#ifdef CONFIG_COMPAT_32BIT_TIME
case VIDIOC_DQEVENT32_TIME32:
- err = alloc_userspace(sizeof(struct v4l2_event_time32), 0, &new_p64);
- compatible_arg = 0;
- break;
+ return put_v4l2_event32_time32(parg, arg);
+#endif
#endif
}
- if (err)
- return err;
-
- /*
- * 3. Calls the native 64-bits ioctl handler.
- *
- * For the functions where a conversion was not needed,
- * compatible_arg is true, and it will call it with the arguments
- * provided by userspace and stored at @p32 var.
- *
- * Otherwise, it will pass the newly allocated @new_p64 argument.
- */
- if (compatible_arg)
- err = native_ioctl(file, ncmd, (unsigned long)p32);
- else
- err = native_ioctl(file, ncmd, (unsigned long)new_p64);
-
- if (err == -ENOTTY)
- return err;
-
- /*
- * 4. Special case: even after an error we need to put the
- * results back for some ioctls.
- *
- * In the case of EXT_CTRLS, the error_idx will contain information
- * on which control failed.
- *
- * In the case of S_EDID, the driver can return E2BIG and set
- * the blocks to maximum allowed value.
- */
+ return 0;
+}
+
+int v4l2_compat_get_array_args(struct file *file, void *mbuf,
+ void __user *user_ptr, size_t array_size,
+ unsigned int cmd, void *arg)
+{
+ int err = 0;
+
switch (cmd) {
- case VIDIOC_G_EXT_CTRLS32:
- case VIDIOC_S_EXT_CTRLS32:
- case VIDIOC_TRY_EXT_CTRLS32:
- if (put_v4l2_ext_controls32(file, new_p64, p32))
- err = -EFAULT;
+ case VIDIOC_G_FMT32:
+ case VIDIOC_S_FMT32:
+ case VIDIOC_TRY_FMT32: {
+ struct v4l2_format *f64 = arg;
+ struct v4l2_clip *c64 = mbuf;
+ struct v4l2_clip32 __user *c32 = user_ptr;
+ u32 clipcount = f64->fmt.win.clipcount;
+
+ if ((f64->type != V4L2_BUF_TYPE_VIDEO_OVERLAY &&
+ f64->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) ||
+ clipcount == 0)
+ return 0;
+ if (clipcount > 2048)
+ return -EINVAL;
+ while (clipcount--) {
+ if (copy_from_user(c64, c32, sizeof(c64->c)))
+ return -EFAULT;
+ c64->next = NULL;
+ c64++;
+ c32++;
+ }
break;
- case VIDIOC_S_EDID32:
- if (put_v4l2_edid32(new_p64, p32))
- err = -EFAULT;
+ }
+#ifdef CONFIG_COMPAT_32BIT_TIME
+ case VIDIOC_QUERYBUF32_TIME32:
+ case VIDIOC_QBUF32_TIME32:
+ case VIDIOC_DQBUF32_TIME32:
+ case VIDIOC_PREPARE_BUF32_TIME32:
+#endif
+ case VIDIOC_QUERYBUF32:
+ case VIDIOC_QBUF32:
+ case VIDIOC_DQBUF32:
+ case VIDIOC_PREPARE_BUF32: {
+ struct v4l2_buffer *b64 = arg;
+ struct v4l2_plane *p64 = mbuf;
+ struct v4l2_plane32 __user *p32 = user_ptr;
+
+ if (V4L2_TYPE_IS_MULTIPLANAR(b64->type)) {
+ u32 num_planes = b64->length;
+
+ if (num_planes == 0)
+ return 0;
+
+ while (num_planes--) {
+ err = get_v4l2_plane32(p64, p32, b64->memory);
+ if (err)
+ return err;
+ ++p64;
+ ++p32;
+ }
+ }
break;
}
- if (err)
- return err;
+ case VIDIOC_G_EXT_CTRLS32:
+ case VIDIOC_S_EXT_CTRLS32:
+ case VIDIOC_TRY_EXT_CTRLS32: {
+ struct v4l2_ext_controls *ecs64 = arg;
+ struct v4l2_ext_control *ec64 = mbuf;
+ struct v4l2_ext_control32 __user *ec32 = user_ptr;
+ int n;
+
+ for (n = 0; n < ecs64->count; n++) {
+ if (copy_from_user(ec64, ec32, sizeof(*ec32)))
+ return -EFAULT;
- /*
- * 5. Copy the data returned at the 64 bits userspace pointer to
- * the original 32 bits structure.
- */
- switch (cmd) {
- case VIDIOC_S_INPUT32:
- case VIDIOC_S_OUTPUT32:
- case VIDIOC_G_INPUT32:
- case VIDIOC_G_OUTPUT32:
- if (assign_in_user((compat_uint_t __user *)p32,
- ((unsigned int __user *)new_p64)))
- err = -EFAULT;
- break;
+ if (ctrl_is_pointer(file, ec64->id)) {
+ compat_uptr_t p;
- case VIDIOC_G_FBUF32:
- err = put_v4l2_framebuffer32(new_p64, p32);
+ if (get_user(p, &ec32->string))
+ return -EFAULT;
+ ec64->string = compat_ptr(p);
+ }
+ ec32++;
+ ec64++;
+ }
break;
-
-#ifdef CONFIG_X86_64
- case VIDIOC_DQEVENT32:
- err = put_v4l2_event32(new_p64, p32);
+ }
+ default:
+ if (copy_from_user(mbuf, user_ptr, array_size))
+ err = -EFAULT;
break;
+ }
- case VIDIOC_DQEVENT32_TIME32:
- err = put_v4l2_event32_time32(new_p64, p32);
- break;
-#endif
+ return err;
+}
- case VIDIOC_G_EDID32:
- err = put_v4l2_edid32(new_p64, p32);
- break;
+int v4l2_compat_put_array_args(struct file *file, void __user *user_ptr,
+ void *mbuf, size_t array_size,
+ unsigned int cmd, void *arg)
+{
+ int err = 0;
+ switch (cmd) {
case VIDIOC_G_FMT32:
case VIDIOC_S_FMT32:
- case VIDIOC_TRY_FMT32:
- err = put_v4l2_format32(new_p64, p32);
- break;
-
- case VIDIOC_CREATE_BUFS32:
- err = put_v4l2_create32(new_p64, p32);
+ case VIDIOC_TRY_FMT32: {
+ struct v4l2_format *f64 = arg;
+ struct v4l2_clip *c64 = mbuf;
+ struct v4l2_clip32 __user *c32 = user_ptr;
+ u32 clipcount = f64->fmt.win.clipcount;
+
+ if ((f64->type != V4L2_BUF_TYPE_VIDEO_OVERLAY &&
+ f64->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY) ||
+ clipcount == 0)
+ return 0;
+ if (clipcount > 2048)
+ return -EINVAL;
+ while (clipcount--) {
+ if (copy_to_user(c32, c64, sizeof(c64->c)))
+ return -EFAULT;
+ c64++;
+ c32++;
+ }
break;
-
- case VIDIOC_PREPARE_BUF32:
+ }
+#ifdef CONFIG_COMPAT_32BIT_TIME
+ case VIDIOC_QUERYBUF32_TIME32:
+ case VIDIOC_QBUF32_TIME32:
+ case VIDIOC_DQBUF32_TIME32:
+ case VIDIOC_PREPARE_BUF32_TIME32:
+#endif
case VIDIOC_QUERYBUF32:
case VIDIOC_QBUF32:
case VIDIOC_DQBUF32:
- err = put_v4l2_buffer32(new_p64, p32);
+ case VIDIOC_PREPARE_BUF32: {
+ struct v4l2_buffer *b64 = arg;
+ struct v4l2_plane *p64 = mbuf;
+ struct v4l2_plane32 __user *p32 = user_ptr;
+
+ if (V4L2_TYPE_IS_MULTIPLANAR(b64->type)) {
+ u32 num_planes = b64->length;
+
+ if (num_planes == 0)
+ return 0;
+
+ while (num_planes--) {
+ err = put_v4l2_plane32(p64, p32, b64->memory);
+ if (err)
+ return err;
+ ++p64;
+ ++p32;
+ }
+ }
break;
+ }
+ case VIDIOC_G_EXT_CTRLS32:
+ case VIDIOC_S_EXT_CTRLS32:
+ case VIDIOC_TRY_EXT_CTRLS32: {
+ struct v4l2_ext_controls *ecs64 = arg;
+ struct v4l2_ext_control *ec64 = mbuf;
+ struct v4l2_ext_control32 __user *ec32 = user_ptr;
+ int n;
+
+ for (n = 0; n < ecs64->count; n++) {
+ unsigned int size = sizeof(*ec32);
+ /*
+ * Do not modify the pointer when copying a pointer
+ * control. The contents of the pointer was changed,
+ * not the pointer itself.
+ * The structures are otherwise compatible.
+ */
+ if (ctrl_is_pointer(file, ec64->id))
+ size -= sizeof(ec32->value64);
- case VIDIOC_PREPARE_BUF32_TIME32:
- case VIDIOC_QUERYBUF32_TIME32:
- case VIDIOC_QBUF32_TIME32:
- case VIDIOC_DQBUF32_TIME32:
- err = put_v4l2_buffer32_time32(new_p64, p32);
- break;
+ if (copy_to_user(ec32, ec64, size))
+ return -EFAULT;
- case VIDIOC_ENUMSTD32:
- err = put_v4l2_standard32(new_p64, p32);
+ ec32++;
+ ec64++;
+ }
break;
-
- case VIDIOC_ENUMINPUT32:
- err = put_v4l2_input32(new_p64, p32);
+ }
+ default:
+ if (copy_to_user(user_ptr, mbuf, array_size))
+ err = -EFAULT;
break;
}
+
return err;
}
@@ -1787,7 +1245,8 @@ long v4l2_compat_ioctl32(struct file *file, unsigned int cmd, unsigned long arg)
return ret;
if (_IOC_TYPE(cmd) == 'V' && _IOC_NR(cmd) < BASE_VIDIOC_PRIVATE)
- ret = do_video_ioctl(file, cmd, arg);
+ ret = file->f_op->unlocked_ioctl(file, cmd,
+ (unsigned long)compat_ptr(arg));
else if (vdev->fops->compat_ioctl32)
ret = vdev->fops->compat_ioctl32(file, cmd, arg);
diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
index bd7f330c941c..5cbe0ffbf501 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -693,9 +693,9 @@ const char * const *v4l2_ctrl_get_menu(u32 id)
return h264_fp_arrangement_type;
case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE:
return h264_fmo_map_type;
- case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE:
+ case V4L2_CID_STATELESS_H264_DECODE_MODE:
return h264_decode_mode;
- case V4L2_CID_MPEG_VIDEO_H264_START_CODE:
+ case V4L2_CID_STATELESS_H264_START_CODE:
return h264_start_code;
case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL:
return mpeg_mpeg2_level;
@@ -830,7 +830,7 @@ const char *v4l2_ctrl_get_name(u32 id)
/* The MPEG controls are applicable to all codec controls
* and the 'MPEG' part of the define is historical */
/* Keep the order of the 'case's the same as in videodev2.h! */
- case V4L2_CID_MPEG_CLASS: return "Codec Controls";
+ case V4L2_CID_CODEC_CLASS: return "Codec Controls";
case V4L2_CID_MPEG_STREAM_TYPE: return "Stream Type";
case V4L2_CID_MPEG_STREAM_PID_PMT: return "Stream PMT Program ID";
case V4L2_CID_MPEG_STREAM_PID_AUDIO: return "Stream Audio Program ID";
@@ -920,14 +920,6 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value";
case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value";
case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value";
- case V4L2_CID_MPEG_VIDEO_H264_SPS: return "H264 Sequence Parameter Set";
- case V4L2_CID_MPEG_VIDEO_H264_PPS: return "H264 Picture Parameter Set";
- case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: return "H264 Scaling Matrix";
- case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters";
- case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters";
- case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE: return "H264 Decode Mode";
- case V4L2_CID_MPEG_VIDEO_H264_START_CODE: return "H264 Start Code";
- case V4L2_CID_MPEG_VIDEO_H264_PRED_WEIGHTS: return "H264 Prediction Weight Table";
case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level";
case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile";
case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value";
@@ -951,7 +943,6 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME: return "Force Key Frame";
case V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS: return "MPEG-2 Slice Parameters";
case V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION: return "MPEG-2 Quantization Matrices";
- case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: return "FWHT Stateless Parameters";
case V4L2_CID_FWHT_I_FRAME_QP: return "FWHT I-Frame QP Value";
case V4L2_CID_FWHT_P_FRAME_QP: return "FWHT P-Frame QP Value";
@@ -1181,6 +1172,19 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD: return "MD Global Threshold";
case V4L2_CID_DETECT_MD_THRESHOLD_GRID: return "MD Threshold Grid";
case V4L2_CID_DETECT_MD_REGION_GRID: return "MD Region Grid";
+
+ /* Stateless Codec controls */
+ /* Keep the order of the 'case's the same as in v4l2-controls.h! */
+ case V4L2_CID_CODEC_STATELESS_CLASS: return "Stateless Codec Controls";
+ case V4L2_CID_STATELESS_H264_DECODE_MODE: return "H264 Decode Mode";
+ case V4L2_CID_STATELESS_H264_START_CODE: return "H264 Start Code";
+ case V4L2_CID_STATELESS_H264_SPS: return "H264 Sequence Parameter Set";
+ case V4L2_CID_STATELESS_H264_PPS: return "H264 Picture Parameter Set";
+ case V4L2_CID_STATELESS_H264_SCALING_MATRIX: return "H264 Scaling Matrix";
+ case V4L2_CID_STATELESS_H264_PRED_WEIGHTS: return "H264 Prediction Weight Table";
+ case V4L2_CID_STATELESS_H264_SLICE_PARAMS: return "H264 Slice Parameters";
+ case V4L2_CID_STATELESS_H264_DECODE_PARAMS: return "H264 Decode Parameters";
+ case V4L2_CID_STATELESS_FWHT_PARAMS: return "FWHT Stateless Parameters";
default:
return NULL;
}
@@ -1306,8 +1310,6 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC:
case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE:
case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE:
- case V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE:
- case V4L2_CID_MPEG_VIDEO_H264_START_CODE:
case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL:
case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE:
case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL:
@@ -1338,6 +1340,8 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE:
case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE:
case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE:
+ case V4L2_CID_STATELESS_H264_DECODE_MODE:
+ case V4L2_CID_STATELESS_H264_START_CODE:
case V4L2_CID_CAMERA_ORIENTATION:
*type = V4L2_CTRL_TYPE_MENU;
break;
@@ -1358,7 +1362,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
break;
case V4L2_CID_USER_CLASS:
case V4L2_CID_CAMERA_CLASS:
- case V4L2_CID_MPEG_CLASS:
+ case V4L2_CID_CODEC_CLASS:
case V4L2_CID_FM_TX_CLASS:
case V4L2_CID_FLASH_CLASS:
case V4L2_CID_JPEG_CLASS:
@@ -1368,6 +1372,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
case V4L2_CID_FM_RX_CLASS:
case V4L2_CID_RF_TUNER_CLASS:
case V4L2_CID_DETECT_CLASS:
+ case V4L2_CID_CODEC_STATELESS_CLASS:
*type = V4L2_CTRL_TYPE_CTRL_CLASS;
/* You can neither read not write these */
*flags |= V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_WRITE_ONLY;
@@ -1428,25 +1433,25 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
case V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION:
*type = V4L2_CTRL_TYPE_MPEG2_QUANTIZATION;
break;
- case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS:
+ case V4L2_CID_STATELESS_FWHT_PARAMS:
*type = V4L2_CTRL_TYPE_FWHT_PARAMS;
break;
- case V4L2_CID_MPEG_VIDEO_H264_SPS:
+ case V4L2_CID_STATELESS_H264_SPS:
*type = V4L2_CTRL_TYPE_H264_SPS;
break;
- case V4L2_CID_MPEG_VIDEO_H264_PPS:
+ case V4L2_CID_STATELESS_H264_PPS:
*type = V4L2_CTRL_TYPE_H264_PPS;
break;
- case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX:
+ case V4L2_CID_STATELESS_H264_SCALING_MATRIX:
*type = V4L2_CTRL_TYPE_H264_SCALING_MATRIX;
break;
- case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS:
+ case V4L2_CID_STATELESS_H264_SLICE_PARAMS:
*type = V4L2_CTRL_TYPE_H264_SLICE_PARAMS;
break;
- case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS:
+ case V4L2_CID_STATELESS_H264_DECODE_PARAMS:
*type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS;
break;
- case V4L2_CID_MPEG_VIDEO_H264_PRED_WEIGHTS:
+ case V4L2_CID_STATELESS_H264_PRED_WEIGHTS:
*type = V4L2_CTRL_TYPE_H264_PRED_WEIGHTS;
break;
case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER:
@@ -1621,6 +1626,8 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx,
union v4l2_ctrl_ptr ptr)
{
struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params;
+ struct v4l2_ctrl_vp8_frame_header *p_vp8_frame_header;
+ struct v4l2_ctrl_fwht_params *p_fwht_params;
void *p = ptr.p + idx * ctrl->elem_size;
if (ctrl->p_def.p_const)
@@ -1643,6 +1650,16 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx,
p_mpeg2_slice_params->picture.picture_coding_type =
V4L2_MPEG2_PICTURE_CODING_TYPE_I;
break;
+ case V4L2_CTRL_TYPE_VP8_FRAME_HEADER:
+ p_vp8_frame_header = p;
+ p_vp8_frame_header->num_dct_parts = 1;
+ break;
+ case V4L2_CTRL_TYPE_FWHT_PARAMS:
+ p_fwht_params = p;
+ p_fwht_params->version = V4L2_FWHT_VERSION;
+ p_fwht_params->width = 1280;
+ p_fwht_params->height = 720;
+ break;
}
}
@@ -1727,6 +1744,27 @@ static void std_log(const struct v4l2_ctrl *ctrl)
case V4L2_CTRL_TYPE_U32:
pr_cont("%u", (unsigned)*ptr.p_u32);
break;
+ case V4L2_CTRL_TYPE_H264_SPS:
+ pr_cont("H264_SPS");
+ break;
+ case V4L2_CTRL_TYPE_H264_PPS:
+ pr_cont("H264_PPS");
+ break;
+ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX:
+ pr_cont("H264_SCALING_MATRIX");
+ break;
+ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS:
+ pr_cont("H264_SLICE_PARAMS");
+ break;
+ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS:
+ pr_cont("H264_DECODE_PARAMS");
+ break;
+ case V4L2_CTRL_TYPE_H264_PRED_WEIGHTS:
+ pr_cont("H264_PRED_WEIGHTS");
+ break;
+ case V4L2_CTRL_TYPE_FWHT_PARAMS:
+ pr_cont("FWHT_PARAMS");
+ break;
default:
pr_cont("unknown type %d", ctrl->type);
break;
@@ -1770,6 +1808,10 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
{
struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params;
struct v4l2_ctrl_vp8_frame_header *p_vp8_frame_header;
+ struct v4l2_ctrl_fwht_params *p_fwht_params;
+ struct v4l2_ctrl_h264_sps *p_h264_sps;
+ struct v4l2_ctrl_h264_pps *p_h264_pps;
+ struct v4l2_ctrl_h264_pred_weights *p_h264_pred_weights;
struct v4l2_ctrl_h264_slice_params *p_h264_slice_params;
struct v4l2_ctrl_h264_decode_params *p_h264_dec_params;
struct v4l2_ctrl_hevc_sps *p_hevc_sps;
@@ -1826,23 +1868,159 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
break;
case V4L2_CTRL_TYPE_FWHT_PARAMS:
+ p_fwht_params = p;
+ if (p_fwht_params->version < V4L2_FWHT_VERSION)
+ return -EINVAL;
+ if (!p_fwht_params->width || !p_fwht_params->height)
+ return -EINVAL;
break;
case V4L2_CTRL_TYPE_H264_SPS:
+ p_h264_sps = p;
+
+ /* Some syntax elements are only conditionally valid */
+ if (p_h264_sps->pic_order_cnt_type != 0) {
+ p_h264_sps->log2_max_pic_order_cnt_lsb_minus4 = 0;
+ } else if (p_h264_sps->pic_order_cnt_type != 1) {
+ p_h264_sps->num_ref_frames_in_pic_order_cnt_cycle = 0;
+ p_h264_sps->offset_for_non_ref_pic = 0;
+ p_h264_sps->offset_for_top_to_bottom_field = 0;
+ memset(&p_h264_sps->offset_for_ref_frame, 0,
+ sizeof(p_h264_sps->offset_for_ref_frame));
+ }
+
+ if (!V4L2_H264_SPS_HAS_CHROMA_FORMAT(p_h264_sps)) {
+ p_h264_sps->chroma_format_idc = 1;
+ p_h264_sps->bit_depth_luma_minus8 = 0;
+ p_h264_sps->bit_depth_chroma_minus8 = 0;
+
+ p_h264_sps->flags &=
+ ~V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS;
+
+ if (p_h264_sps->chroma_format_idc < 3)
+ p_h264_sps->flags &=
+ ~V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE;
+ }
+
+ if (p_h264_sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)
+ p_h264_sps->flags &=
+ ~V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD;
+
+ /*
+ * Chroma 4:2:2 format require at least High 4:2:2 profile.
+ *
+ * The H264 specification and well-known parser implementations
+ * use profile-idc values directly, as that is clearer and
+ * less ambiguous. We do the same here.
+ */
+ if (p_h264_sps->profile_idc < 122 &&
+ p_h264_sps->chroma_format_idc > 1)
+ return -EINVAL;
+ /* Chroma 4:4:4 format require at least High 4:2:2 profile */
+ if (p_h264_sps->profile_idc < 244 &&
+ p_h264_sps->chroma_format_idc > 2)
+ return -EINVAL;
+ if (p_h264_sps->chroma_format_idc > 3)
+ return -EINVAL;
+
+ if (p_h264_sps->bit_depth_luma_minus8 > 6)
+ return -EINVAL;
+ if (p_h264_sps->bit_depth_chroma_minus8 > 6)
+ return -EINVAL;
+ if (p_h264_sps->log2_max_frame_num_minus4 > 12)
+ return -EINVAL;
+ if (p_h264_sps->pic_order_cnt_type > 2)
+ return -EINVAL;
+ if (p_h264_sps->log2_max_pic_order_cnt_lsb_minus4 > 12)
+ return -EINVAL;
+ if (p_h264_sps->max_num_ref_frames > V4L2_H264_REF_LIST_LEN)
+ return -EINVAL;
+ break;
+
case V4L2_CTRL_TYPE_H264_PPS:
+ p_h264_pps = p;
+
+ if (p_h264_pps->num_slice_groups_minus1 > 7)
+ return -EINVAL;
+ if (p_h264_pps->num_ref_idx_l0_default_active_minus1 >
+ (V4L2_H264_REF_LIST_LEN - 1))
+ return -EINVAL;
+ if (p_h264_pps->num_ref_idx_l1_default_active_minus1 >
+ (V4L2_H264_REF_LIST_LEN - 1))
+ return -EINVAL;
+ if (p_h264_pps->weighted_bipred_idc > 2)
+ return -EINVAL;
+ /*
+ * pic_init_qp_minus26 shall be in the range of
+ * -(26 + QpBdOffset_y) to +25, inclusive,
+ * where QpBdOffset_y is 6 * bit_depth_luma_minus8
+ */
+ if (p_h264_pps->pic_init_qp_minus26 < -62 ||
+ p_h264_pps->pic_init_qp_minus26 > 25)
+ return -EINVAL;
+ if (p_h264_pps->pic_init_qs_minus26 < -26 ||
+ p_h264_pps->pic_init_qs_minus26 > 25)
+ return -EINVAL;
+ if (p_h264_pps->chroma_qp_index_offset < -12 ||
+ p_h264_pps->chroma_qp_index_offset > 12)
+ return -EINVAL;
+ if (p_h264_pps->second_chroma_qp_index_offset < -12 ||
+ p_h264_pps->second_chroma_qp_index_offset > 12)
+ return -EINVAL;
+ break;
+
case V4L2_CTRL_TYPE_H264_SCALING_MATRIX:
+ break;
+
case V4L2_CTRL_TYPE_H264_PRED_WEIGHTS:
+ p_h264_pred_weights = p;
+
+ if (p_h264_pred_weights->luma_log2_weight_denom > 7)
+ return -EINVAL;
+ if (p_h264_pred_weights->chroma_log2_weight_denom > 7)
+ return -EINVAL;
break;
case V4L2_CTRL_TYPE_H264_SLICE_PARAMS:
p_h264_slice_params = p;
+ if (p_h264_slice_params->slice_type != V4L2_H264_SLICE_TYPE_B)
+ p_h264_slice_params->flags &=
+ ~V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED;
+
+ if (p_h264_slice_params->colour_plane_id > 2)
+ return -EINVAL;
+ if (p_h264_slice_params->cabac_init_idc > 2)
+ return -EINVAL;
+ if (p_h264_slice_params->disable_deblocking_filter_idc > 2)
+ return -EINVAL;
+ if (p_h264_slice_params->slice_alpha_c0_offset_div2 < -6 ||
+ p_h264_slice_params->slice_alpha_c0_offset_div2 > 6)
+ return -EINVAL;
+ if (p_h264_slice_params->slice_beta_offset_div2 < -6 ||
+ p_h264_slice_params->slice_beta_offset_div2 > 6)
+ return -EINVAL;
+
+ if (p_h264_slice_params->slice_type == V4L2_H264_SLICE_TYPE_I ||
+ p_h264_slice_params->slice_type == V4L2_H264_SLICE_TYPE_SI)
+ p_h264_slice_params->num_ref_idx_l0_active_minus1 = 0;
+ if (p_h264_slice_params->slice_type != V4L2_H264_SLICE_TYPE_B)
+ p_h264_slice_params->num_ref_idx_l1_active_minus1 = 0;
+
+ if (p_h264_slice_params->num_ref_idx_l0_active_minus1 >
+ (V4L2_H264_REF_LIST_LEN - 1))
+ return -EINVAL;
+ if (p_h264_slice_params->num_ref_idx_l1_active_minus1 >
+ (V4L2_H264_REF_LIST_LEN - 1))
+ return -EINVAL;
zero_reserved(*p_h264_slice_params);
break;
case V4L2_CTRL_TYPE_H264_DECODE_PARAMS:
p_h264_dec_params = p;
+ if (p_h264_dec_params->nal_ref_idc > 3)
+ return -EINVAL;
for (i = 0; i < V4L2_H264_NUM_DPB_ENTRIES; i++) {
struct v4l2_h264_dpb_entry *dpb_entry =
&p_h264_dec_params->dpb[i];
@@ -3363,9 +3541,6 @@ static int v4l2_ctrl_request_clone(struct v4l2_ctrl_handler *hdl,
/* Skip refs inherited from other devices */
if (ref->from_other_dev)
continue;
- /* And buttons */
- if (ctrl->type == V4L2_CTRL_TYPE_BUTTON)
- continue;
err = handler_new_ref(hdl, ctrl, &new_ref, false, true);
if (err)
break;
@@ -4110,8 +4285,13 @@ static int try_set_ext_ctrls_common(struct v4l2_fh *fh,
struct v4l2_ctrl *ctrl = helpers[idx].ref->ctrl;
ret = user_to_new(cs->controls + idx, ctrl);
- if (!ret && ctrl->is_ptr)
+ if (!ret && ctrl->is_ptr) {
ret = validate_new(ctrl, ctrl->p_new);
+ if (ret)
+ dprintk(vdev,
+ "failed to validate control %s (%d)\n",
+ v4l2_ctrl_get_name(ctrl->id), ret);
+ }
idx = helpers[idx].next;
} while (!ret && idx);
@@ -4447,8 +4627,7 @@ int v4l2_ctrl_request_setup(struct media_request *req,
* Skip if this control was already handled by a cluster.
* Skip button controls and read-only controls.
*/
- if (ref->req_done || ctrl->type == V4L2_CTRL_TYPE_BUTTON ||
- (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY))
+ if (ref->req_done || (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY))
continue;
v4l2_ctrl_lock(master);
diff --git a/drivers/media/v4l2-core/v4l2-device.c b/drivers/media/v4l2-core/v4l2-device.c
index de4287251a89..d2e58ae91f9b 100644
--- a/drivers/media/v4l2-core/v4l2-device.c
+++ b/drivers/media/v4l2-core/v4l2-device.c
@@ -218,13 +218,14 @@ int __v4l2_device_register_subdev_nodes(struct v4l2_device *v4l2_dev,
vdev->ctrl_handler = sd->ctrl_handler;
if (read_only)
set_bit(V4L2_FL_SUBDEV_RO_DEVNODE, &vdev->flags);
+ sd->devnode = vdev;
err = __video_register_device(vdev, VFL_TYPE_SUBDEV, -1, 1,
sd->owner);
if (err < 0) {
+ sd->devnode = NULL;
kfree(vdev);
goto clean_up;
}
- sd->devnode = vdev;
#if defined(CONFIG_MEDIA_CONTROLLER)
sd->entity.info.dev.major = VIDEO_MAJOR;
sd->entity.info.dev.minor = vdev->minor;
diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c
index d7bbe33840cb..5353e37eb950 100644
--- a/drivers/media/v4l2-core/v4l2-fwnode.c
+++ b/drivers/media/v4l2-core/v4l2-fwnode.c
@@ -93,7 +93,7 @@ v4l2_fwnode_bus_type_to_mbus(enum v4l2_fwnode_bus_type type)
const struct v4l2_fwnode_bus_conv *conv =
get_v4l2_fwnode_bus_conv_by_fwnode_bus(type);
- return conv ? conv->mbus_type : V4L2_MBUS_UNKNOWN;
+ return conv ? conv->mbus_type : V4L2_MBUS_INVALID;
}
static const char *
@@ -416,26 +416,18 @@ static int __v4l2_fwnode_endpoint_parse(struct fwnode_handle *fwnode,
enum v4l2_mbus_type mbus_type;
int rval;
- if (vep->bus_type == V4L2_MBUS_UNKNOWN) {
- /* Zero fields from bus union to until the end */
- memset(&vep->bus, 0,
- sizeof(*vep) - offsetof(typeof(*vep), bus));
- }
-
pr_debug("===== begin parsing endpoint %pfw\n", fwnode);
- /*
- * Zero the fwnode graph endpoint memory in case we don't end up parsing
- * the endpoint.
- */
- memset(&vep->base, 0, sizeof(vep->base));
-
fwnode_property_read_u32(fwnode, "bus-type", &bus_type);
pr_debug("fwnode video bus type %s (%u), mbus type %s (%u)\n",
v4l2_fwnode_bus_type_to_string(bus_type), bus_type,
v4l2_fwnode_mbus_type_to_string(vep->bus_type),
vep->bus_type);
mbus_type = v4l2_fwnode_bus_type_to_mbus(bus_type);
+ if (mbus_type == V4L2_MBUS_INVALID) {
+ pr_debug("unsupported bus type %u\n", bus_type);
+ return -EINVAL;
+ }
if (vep->bus_type != V4L2_MBUS_UNKNOWN) {
if (mbus_type != V4L2_MBUS_UNKNOWN &&
@@ -919,20 +911,6 @@ v4l2_async_notifier_parse_fwnode_endpoints(struct device *dev,
}
EXPORT_SYMBOL_GPL(v4l2_async_notifier_parse_fwnode_endpoints);
-int
-v4l2_async_notifier_parse_fwnode_endpoints_by_port(struct device *dev,
- struct v4l2_async_notifier *notifier,
- size_t asd_struct_size,
- unsigned int port,
- parse_endpoint_func parse_endpoint)
-{
- return __v4l2_async_notifier_parse_fwnode_ep(dev, notifier,
- asd_struct_size,
- port, true,
- parse_endpoint);
-}
-EXPORT_SYMBOL_GPL(v4l2_async_notifier_parse_fwnode_endpoints_by_port);
-
/*
* v4l2_fwnode_reference_parse - parse references for async sub-devices
* @dev: the device node the properties of which are parsed for references
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
index eeff398fbdcc..3198abdd538c 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -8,6 +8,7 @@
* Mauro Carvalho Chehab <mchehab@kernel.org> (version 2)
*/
+#include <linux/compat.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/slab.h>
@@ -1402,6 +1403,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_META_FMT_UVC: descr = "UVC Payload Header Metadata"; break;
case V4L2_META_FMT_D4XX: descr = "Intel D4xx UVC Metadata"; break;
case V4L2_META_FMT_VIVID: descr = "Vivid Metadata"; break;
+ case V4L2_META_FMT_RK_ISP1_PARAMS: descr = "Rockchip ISP1 3A Parameters"; break;
+ case V4L2_META_FMT_RK_ISP1_STAT_3A: descr = "Rockchip ISP1 3A Statistics"; break;
default:
/* Compressed formats */
@@ -1581,7 +1584,7 @@ static int v4l_g_fmt(const struct v4l2_ioctl_ops *ops,
switch (p->type) {
case V4L2_BUF_TYPE_VIDEO_OVERLAY:
case V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY: {
- struct v4l2_clip __user *clips = p->fmt.win.clips;
+ struct v4l2_clip *clips = p->fmt.win.clips;
u32 clipcount = p->fmt.win.clipcount;
void __user *bitmap = p->fmt.win.bitmap;
@@ -3083,6 +3086,27 @@ static int check_array_args(unsigned int cmd, void *parg, size_t *array_size,
}
break;
}
+ case VIDIOC_G_FMT:
+ case VIDIOC_S_FMT:
+ case VIDIOC_TRY_FMT: {
+ struct v4l2_format *fmt = parg;
+
+ if (fmt->type != V4L2_BUF_TYPE_VIDEO_OVERLAY &&
+ fmt->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
+ break;
+ if (fmt->fmt.win.clipcount > 2048)
+ return -EINVAL;
+ if (!fmt->fmt.win.clipcount)
+ break;
+
+ *user_ptr = (void __user *)fmt->fmt.win.clips;
+ *kernel_ptr = (void **)&fmt->fmt.win.clips;
+ *array_size = sizeof(struct v4l2_clip)
+ * fmt->fmt.win.clipcount;
+
+ ret = 1;
+ break;
+ }
}
return ret;
@@ -3104,14 +3128,18 @@ static unsigned int video_translate_cmd(unsigned int cmd)
return VIDIOC_PREPARE_BUF;
#endif
}
+ if (in_compat_syscall())
+ return v4l2_compat_translate_cmd(cmd);
return cmd;
}
-static int video_get_user(void __user *arg, void *parg, unsigned int cmd,
+static int video_get_user(void __user *arg, void *parg,
+ unsigned int real_cmd, unsigned int cmd,
bool *always_copy)
{
- unsigned int n = _IOC_SIZE(cmd);
+ unsigned int n = _IOC_SIZE(real_cmd);
+ int err = 0;
if (!(_IOC_DIR(cmd) & _IOC_WRITE)) {
/* read-only ioctl */
@@ -3119,73 +3147,82 @@ static int video_get_user(void __user *arg, void *parg, unsigned int cmd,
return 0;
}
- switch (cmd) {
-#ifdef CONFIG_COMPAT_32BIT_TIME
- case VIDIOC_QUERYBUF_TIME32:
- case VIDIOC_QBUF_TIME32:
- case VIDIOC_DQBUF_TIME32:
- case VIDIOC_PREPARE_BUF_TIME32: {
- struct v4l2_buffer_time32 vb32;
- struct v4l2_buffer *vb = parg;
-
- if (copy_from_user(&vb32, arg, sizeof(vb32)))
- return -EFAULT;
-
- *vb = (struct v4l2_buffer) {
- .index = vb32.index,
- .type = vb32.type,
- .bytesused = vb32.bytesused,
- .flags = vb32.flags,
- .field = vb32.field,
- .timestamp.tv_sec = vb32.timestamp.tv_sec,
- .timestamp.tv_usec = vb32.timestamp.tv_usec,
- .timecode = vb32.timecode,
- .sequence = vb32.sequence,
- .memory = vb32.memory,
- .m.userptr = vb32.m.userptr,
- .length = vb32.length,
- .request_fd = vb32.request_fd,
- };
-
- if (cmd == VIDIOC_QUERYBUF_TIME32)
- vb->request_fd = 0;
+ /*
+ * In some cases, only a few fields are used as input,
+ * i.e. when the app sets "index" and then the driver
+ * fills in the rest of the structure for the thing
+ * with that index. We only need to copy up the first
+ * non-input field.
+ */
+ if (v4l2_is_known_ioctl(real_cmd)) {
+ u32 flags = v4l2_ioctls[_IOC_NR(real_cmd)].flags;
- break;
+ if (flags & INFO_FL_CLEAR_MASK)
+ n = (flags & INFO_FL_CLEAR_MASK) >> 16;
+ *always_copy = flags & INFO_FL_ALWAYS_COPY;
}
-#endif
- default:
- /*
- * In some cases, only a few fields are used as input,
- * i.e. when the app sets "index" and then the driver
- * fills in the rest of the structure for the thing
- * with that index. We only need to copy up the first
- * non-input field.
- */
- if (v4l2_is_known_ioctl(cmd)) {
- u32 flags = v4l2_ioctls[_IOC_NR(cmd)].flags;
-
- if (flags & INFO_FL_CLEAR_MASK)
- n = (flags & INFO_FL_CLEAR_MASK) >> 16;
- *always_copy = flags & INFO_FL_ALWAYS_COPY;
- }
+ if (cmd == real_cmd) {
if (copy_from_user(parg, (void __user *)arg, n))
- return -EFAULT;
-
- /* zero out anything we don't copy from userspace */
- if (n < _IOC_SIZE(cmd))
- memset((u8 *)parg + n, 0, _IOC_SIZE(cmd) - n);
- break;
+ err = -EFAULT;
+ } else if (in_compat_syscall()) {
+ err = v4l2_compat_get_user(arg, parg, cmd);
+ } else {
+ switch (cmd) {
+#ifdef CONFIG_COMPAT_32BIT_TIME
+ case VIDIOC_QUERYBUF_TIME32:
+ case VIDIOC_QBUF_TIME32:
+ case VIDIOC_DQBUF_TIME32:
+ case VIDIOC_PREPARE_BUF_TIME32: {
+ struct v4l2_buffer_time32 vb32;
+ struct v4l2_buffer *vb = parg;
+
+ if (copy_from_user(&vb32, arg, sizeof(vb32)))
+ return -EFAULT;
+
+ *vb = (struct v4l2_buffer) {
+ .index = vb32.index,
+ .type = vb32.type,
+ .bytesused = vb32.bytesused,
+ .flags = vb32.flags,
+ .field = vb32.field,
+ .timestamp.tv_sec = vb32.timestamp.tv_sec,
+ .timestamp.tv_usec = vb32.timestamp.tv_usec,
+ .timecode = vb32.timecode,
+ .sequence = vb32.sequence,
+ .memory = vb32.memory,
+ .m.userptr = vb32.m.userptr,
+ .length = vb32.length,
+ .request_fd = vb32.request_fd,
+ };
+ break;
+ }
+#endif
+ }
}
- return 0;
+ /* zero out anything we don't copy from userspace */
+ if (!err && n < _IOC_SIZE(real_cmd))
+ memset((u8 *)parg + n, 0, _IOC_SIZE(real_cmd) - n);
+ return err;
}
-static int video_put_user(void __user *arg, void *parg, unsigned int cmd)
+static int video_put_user(void __user *arg, void *parg,
+ unsigned int real_cmd, unsigned int cmd)
{
if (!(_IOC_DIR(cmd) & _IOC_READ))
return 0;
+ if (cmd == real_cmd) {
+ /* Copy results into user buffer */
+ if (copy_to_user(arg, parg, _IOC_SIZE(cmd)))
+ return -EFAULT;
+ return 0;
+ }
+
+ if (in_compat_syscall())
+ return v4l2_compat_put_user(arg, parg, cmd);
+
switch (cmd) {
#ifdef CONFIG_COMPAT_32BIT_TIME
case VIDIOC_DQEVENT_TIME32: {
@@ -3236,11 +3273,6 @@ static int video_put_user(void __user *arg, void *parg, unsigned int cmd)
break;
}
#endif
- default:
- /* Copy results into user buffer */
- if (copy_to_user(arg, parg, _IOC_SIZE(cmd)))
- return -EFAULT;
- break;
}
return 0;
@@ -3274,8 +3306,8 @@ video_usercopy(struct file *file, unsigned int orig_cmd, unsigned long arg,
parg = mbuf;
}
- err = video_get_user((void __user *)arg, parg, orig_cmd,
- &always_copy);
+ err = video_get_user((void __user *)arg, parg, cmd,
+ orig_cmd, &always_copy);
if (err)
goto out;
}
@@ -3297,7 +3329,14 @@ video_usercopy(struct file *file, unsigned int orig_cmd, unsigned long arg,
if (NULL == mbuf)
goto out_array_args;
err = -EFAULT;
- if (copy_from_user(mbuf, user_ptr, array_size))
+ if (in_compat_syscall())
+ err = v4l2_compat_get_array_args(file, mbuf, user_ptr,
+ array_size, orig_cmd,
+ parg);
+ else
+ err = copy_from_user(mbuf, user_ptr, array_size) ?
+ -EFAULT : 0;
+ if (err)
goto out_array_args;
*kernel_ptr = mbuf;
}
@@ -3318,8 +3357,17 @@ video_usercopy(struct file *file, unsigned int orig_cmd, unsigned long arg,
if (has_array_args) {
*kernel_ptr = (void __force *)user_ptr;
- if (copy_to_user(user_ptr, mbuf, array_size))
+ if (in_compat_syscall()) {
+ int put_err;
+
+ put_err = v4l2_compat_put_array_args(file, user_ptr, mbuf,
+ array_size, orig_cmd,
+ parg);
+ if (put_err)
+ err = put_err;
+ } else if (copy_to_user(user_ptr, mbuf, array_size)) {
err = -EFAULT;
+ }
goto out_array_args;
}
/*
@@ -3330,7 +3378,7 @@ video_usercopy(struct file *file, unsigned int orig_cmd, unsigned long arg,
goto out;
out_array_args:
- if (video_put_user((void __user *)arg, parg, orig_cmd))
+ if (video_put_user((void __user *)arg, parg, cmd, orig_cmd))
err = -EFAULT;
out:
kvfree(mbuf);
diff --git a/drivers/media/v4l2-core/v4l2-subdev.c b/drivers/media/v4l2-core/v4l2-subdev.c
index a7d508e74d6b..956dafab43d4 100644
--- a/drivers/media/v4l2-core/v4l2-subdev.c
+++ b/drivers/media/v4l2-core/v4l2-subdev.c
@@ -792,21 +792,55 @@ int v4l2_subdev_link_validate_default(struct v4l2_subdev *sd,
struct v4l2_subdev_format *source_fmt,
struct v4l2_subdev_format *sink_fmt)
{
+ bool pass = true;
+
/* The width, height and code must match. */
- if (source_fmt->format.width != sink_fmt->format.width
- || source_fmt->format.height != sink_fmt->format.height
- || source_fmt->format.code != sink_fmt->format.code)
- return -EPIPE;
+ if (source_fmt->format.width != sink_fmt->format.width) {
+ dev_dbg(sd->entity.graph_obj.mdev->dev,
+ "%s: width does not match (source %u, sink %u)\n",
+ __func__,
+ source_fmt->format.width, sink_fmt->format.width);
+ pass = false;
+ }
+
+ if (source_fmt->format.height != sink_fmt->format.height) {
+ dev_dbg(sd->entity.graph_obj.mdev->dev,
+ "%s: height does not match (source %u, sink %u)\n",
+ __func__,
+ source_fmt->format.height, sink_fmt->format.height);
+ pass = false;
+ }
+
+ if (source_fmt->format.code != sink_fmt->format.code) {
+ dev_dbg(sd->entity.graph_obj.mdev->dev,
+ "%s: media bus code does not match (source 0x%8.8x, sink 0x%8.8x)\n",
+ __func__,
+ source_fmt->format.code, sink_fmt->format.code);
+ pass = false;
+ }
/* The field order must match, or the sink field order must be NONE
* to support interlaced hardware connected to bridges that support
* progressive formats only.
*/
if (source_fmt->format.field != sink_fmt->format.field &&
- sink_fmt->format.field != V4L2_FIELD_NONE)
- return -EPIPE;
+ sink_fmt->format.field != V4L2_FIELD_NONE) {
+ dev_dbg(sd->entity.graph_obj.mdev->dev,
+ "%s: field does not match (source %u, sink %u)\n",
+ __func__,
+ source_fmt->format.field, sink_fmt->format.field);
+ pass = false;
+ }
- return 0;
+ if (pass)
+ return 0;
+
+ dev_dbg(sd->entity.graph_obj.mdev->dev,
+ "%s: link was \"%s\":%u -> \"%s\":%u\n", __func__,
+ link->source->entity->name, link->source->index,
+ link->sink->entity->name, link->sink->index);
+
+ return -EPIPE;
}
EXPORT_SYMBOL_GPL(v4l2_subdev_link_validate_default);