diff options
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h | 1 |
3 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h index c24a81eebc7c..880152c0f775 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h +++ b/drivers/gpu/drm/amd/amdgpu/smu_ucode_xfer_vi.h @@ -44,6 +44,7 @@ #define UCODE_ID_IH_REG_RESTORE 11 #define UCODE_ID_VBIOS 12 #define UCODE_ID_MISC_METADATA 13 +#define UCODE_ID_SMU_SK 14 #define UCODE_ID_RLC_SCRATCH 32 #define UCODE_ID_RLC_SRM_ARAM 33 #define UCODE_ID_RLC_SRM_DRAM 34 diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h index 733fa371a29c..f81626257a37 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h @@ -71,8 +71,12 @@ struct SMU_SclkSetting { uint16_t Pcc_fcw_int; uint8_t PllRange; uint8_t SSc_En; + uint16_t Sclk_slew_rate; + uint16_t Pcc_up_slew_rate; + uint16_t Pcc_down_slew_rate; uint16_t Fcw1_int; uint16_t Fcw1_frac; + uint16_t Sclk_ss_slew_rate; }; typedef struct SMU_SclkSetting SMU_SclkSetting; @@ -120,7 +124,8 @@ struct SMU74_Discrete_Ulv { uint16_t VddcOffset; uint8_t VddcOffsetVid; uint8_t VddcPhase; - uint32_t Reserved; + uint16_t BifSclkDfs; + uint16_t Reserved; }; typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv; @@ -155,7 +160,8 @@ struct SMU74_Discrete_LinkLevel { uint8_t SPC; uint32_t DownThreshold; uint32_t UpThreshold; - uint32_t Reserved; + uint16_t BifSclkDfs; + uint16_t Reserved; }; typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel; diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h index c24a81eebc7c..880152c0f775 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_ucode_xfer_vi.h @@ -44,6 +44,7 @@ #define UCODE_ID_IH_REG_RESTORE 11 #define UCODE_ID_VBIOS 12 #define UCODE_ID_MISC_METADATA 13 +#define UCODE_ID_SMU_SK 14 #define UCODE_ID_RLC_SCRATCH 32 #define UCODE_ID_RLC_SRM_ARAM 33 #define UCODE_ID_RLC_SRM_DRAM 34 |