diff options
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_sprite.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 111 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 39 |
6 files changed, 131 insertions, 44 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 4934c89882b1..18af078c208b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5273,8 +5273,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask; int config, i; - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) - /* Wa_1409767108: tgl */ + if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) || + IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) + /* Wa_1409767108:tgl,dg1 */ table = wa_1409767108_buddy_page_masks; else table = tgl_buddy_page_masks; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 3ae7470c1b8b..88bfebdf9228 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2886,8 +2886,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, enum plane_id plane_id) { - /* Wa_14010477008:tgl[a0..c0],rkl[all] */ - if (IS_ROCKETLAKE(dev_priv) || + /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ + if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) return false; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index c6433b72f5e9..fed9503a7c4e 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -672,6 +672,20 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 0); } +static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); + + /* Wa_1409044764 */ + WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, + DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); + + /* Wa_22010493298 */ + WA_SET_BIT_MASKED(HIZ_CHICKEN, + DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); +} + static void __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, struct i915_wa_list *wal, @@ -684,7 +698,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) + if (IS_DG1(i915)) + dg1_ctx_workarounds_init(engine, wal); + else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 12)) gen12_ctx_workarounds_init(engine, wal); @@ -1245,9 +1261,35 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void +dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); + + /* Wa_1607087056:dg1 */ + if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0)) + wa_write_or(wal, + SLICE_UNIT_LEVEL_CLKGATE, + L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); + + /* Wa_1409420604:dg1 */ + if (IS_DG1(i915)) + wa_write_or(wal, + SUBSLICE_UNIT_LEVEL_CLKGATE2, + CPSSUNIT_CLKGATE_DIS); + + /* Wa_1408615072:dg1 */ + /* Empirical testing shows this register is unaffected by engine reset. */ + if (IS_DG1(i915)) + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + VSUNIT_CLKGATE_DIS_TGL); +} + +static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_TIGERLAKE(i915)) + if (IS_DG1(i915)) + dg1_gt_workarounds_init(i915, wal); + else if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 12)) gen12_gt_workarounds_init(i915, wal); @@ -1612,6 +1654,20 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) } } +static void dg1_whitelist_build(struct intel_engine_cs *engine) +{ + struct i915_wa_list *w = &engine->whitelist; + + tgl_whitelist_build(engine); + + /* GEN:BUG:1409280441:dg1 */ + if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) && + (engine->class == RENDER_CLASS || + engine->class == COPY_ENGINE_CLASS)) + whitelist_reg_ext(w, RING_ID(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); +} + void intel_engine_init_whitelist(struct intel_engine_cs *engine) { struct drm_i915_private *i915 = engine->i915; @@ -1619,7 +1675,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) wa_init_start(w, "whitelist", engine->name); - if (IS_GEN(i915, 12)) + if (IS_DG1(i915)) + dg1_whitelist_build(engine); + else if (IS_GEN(i915, 12)) tgl_whitelist_build(engine); else if (IS_GEN(i915, 11)) icl_whitelist_build(engine); @@ -1673,15 +1731,18 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct drm_i915_private *i915 = engine->i915; - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { + if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || + IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { /* - * Wa_1607138336:tgl - * Wa_1607063988:tgl + * Wa_1607138336:tgl[a0],dg1[a0] + * Wa_1607063988:tgl[a0],dg1[a0] */ wa_write_or(wal, GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); + } + if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) @@ -1695,35 +1756,41 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } - if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl,rkl */ + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl,dg1 */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); - /* Wa_1409804808:tgl,rkl */ + /* + * Wa_1407928979:tgl A* + * Wa_18011464164:tgl[B0+],dg1[B0+] + * Wa_22010931296:tgl[B0+],dg1[B0+] + * Wa_14010919138:rkl, dg1 + */ + wa_write_or(wal, GEN7_FF_THREAD_MODE, + GEN12_FF_TESSELATION_DOP_GATE_DISABLE); + } + + if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || + IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1409804808:tgl,rkl,dg1[a0] */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); /* * Wa_1409085225:tgl - * Wa_14010229206:tgl,rkl + * Wa_14010229206:tgl,rkl,dg1[a0] */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); /* - * Wa_1407928979:tgl A* - * Wa_18011464164:tgl B0+ - * Wa_22010931296:tgl B0+ - * Wa_14010919138:rkl,tgl - */ - wa_write_or(wal, GEN7_FF_THREAD_MODE, - GEN12_FF_TESSELATION_DOP_GATE_DISABLE); - - /* * Wa_1607030317:tgl * Wa_1607186500:tgl - * Wa_1607297627:tgl,rkl there are multiple entries for this - * WA in the BSpec; some indicate this is an A0-only WA, - * others indicate it applies to all steppings. + * Wa_1607297627:tgl,rkl,dg1[a0] + * + * On TGL and RKL there are multiple entries for this WA in the + * BSpec; some indicate this is an A0-only WA, others indicate + * it applies to all steppings so we trust the "all steppings." + * For DG1 this only applies to A0. */ wa_masked_en(wal, GEN6_RC_SLEEP_PSMI_CONTROL, diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 16d4e72bed09..d0eeb2181e74 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -918,6 +918,8 @@ static const struct intel_device_info dg1_info __maybe_unused = { .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), + /* Wa_16011227922 */ + .ppgtt_size = 47, }; #undef GEN diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 49945e33f573..d33d0057aef4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2528,6 +2528,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) #define RING_HWS_PGA(base) _MMIO((base) + 0x80) +#define RING_ID(base) _MMIO((base) + 0x8c) #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) #define RESET_CTL_CAT_ERROR REG_BIT(2) @@ -4147,6 +4148,7 @@ enum { #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) #define TGL_VRH_GATING_DIS REG_BIT(31) +#define DPT_GATING_DIS REG_BIT(22) #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) #define BXT_GMBUS_GATING_DIS (1 << 14) @@ -8019,13 +8021,15 @@ enum { #define GEN8_L3CNTLREG _MMIO(0x7034) #define GEN8_ERRDETBCTRL (1 << 9) -#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) - #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) - #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9) +#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) + #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) + #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) + #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) #define HIZ_CHICKEN _MMIO(0x7018) -# define CHV_HZ_8X8_MODE_IN_1X (1 << 15) -# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3) +# define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15) +# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) +# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3) #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) #define DISABLE_PIXEL_MASK_CAMMING (1 << 14) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8cd62402d597..ae6b367e63cb 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7116,25 +7116,26 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv) 0, CNL_DELAY_PMRSP); } -static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) +static void gen12_init_clock_gating(struct drm_i915_private *i915) { - u32 vd_pg_enable = 0; unsigned int i; + /* This is not a WA. Enable VD HCP & MFX_ENC powergate */ + for (i = 0; i < I915_MAX_VCS; i++) + if (HAS_ENGINE(&i915->gt, _VCS(i))) + intel_uncore_rmw(&i915->uncore, POWERGATE_ENABLE, 0, + VDN_HCP_POWERGATE_ENABLE(i) | + VDN_MFX_POWERGATE_ENABLE(i)); +} + +static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) +{ + gen12_init_clock_gating(dev_priv); + /* Wa_1409120013:tgl */ I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); - /* This is not a WA. Enable VD HCP & MFX_ENC powergate */ - for (i = 0; i < I915_MAX_VCS; i++) { - if (HAS_ENGINE(&dev_priv->gt, _VCS(i))) - vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) | - VDN_MFX_POWERGATE_ENABLE(i); - } - - I915_WRITE(POWERGATE_ENABLE, - I915_READ(POWERGATE_ENABLE) | vd_pg_enable); - /* Wa_1409825376:tgl (pre-prod)*/ if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1)) I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | @@ -7145,6 +7146,16 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) 0, DFR_DISABLE); } +static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) +{ + gen12_init_clock_gating(dev_priv); + + /* Wa_1409836686:dg1[a0] */ + if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0)) + I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | + DPT_GATING_DIS); +} + static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) { if (!HAS_PCH_CNP(dev_priv)) @@ -7590,7 +7601,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) */ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { - if (IS_GEN(dev_priv, 12)) + if (IS_DG1(dev_priv)) + dev_priv->display.init_clock_gating = dg1_init_clock_gating; + else if (IS_GEN(dev_priv, 12)) dev_priv->display.init_clock_gating = tgl_init_clock_gating; else if (IS_GEN(dev_priv, 11)) dev_priv->display.init_clock_gating = icl_init_clock_gating; |