diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 32 |
1 files changed, 25 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 44b8da19a2a0..b2d785969d17 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1254,13 +1254,13 @@ enum i915_power_well_id { /* * HSW/BDW - * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) + * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) */ HSW_DISP_PW_GLOBAL = 15, /* * GEN9+ - * - HSW_PWR_WELL_DRIVER (status bit: id*2, req bit: id*2+1) + * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1) */ SKL_DISP_PW_MISC_IO = 0, SKL_DISP_PW_DDI_A_E, @@ -8189,11 +8189,29 @@ enum { #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) /* HSW Power Wells */ -#define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */ -#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */ -#define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */ -#define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */ -#define _HSW_PW_SHIFT(pw) ((pw) * 2) +#define _HSW_PWR_WELL_CTL1 0x45400 +#define _HSW_PWR_WELL_CTL2 0x45404 +#define _HSW_PWR_WELL_CTL3 0x45408 +#define _HSW_PWR_WELL_CTL4 0x4540C + +/* + * Each power well control register contains up to 16 (request, status) HW + * flag tuples. The register index and HW flag shift is determined by the + * power well ID (see i915_power_well_id). There are 4 possible sources of + * power well requests each source having its own set of control registers: + * BIOS, DRIVER, KVMR, DEBUG. + */ +#define _HSW_PW_REG_IDX(pw) ((pw) >> 4) +#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2) +/* TODO: Add all PWR_WELL_CTL registers below for new platforms */ +#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL1)) +#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL2)) +#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3) +#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \ + _HSW_PWR_WELL_CTL4)) + #define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1)) #define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw)) #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) |