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Diffstat (limited to 'drivers/gpu/drm/i915/gt')
-rw-r--r--drivers/gpu/drm/i915/gt/gen7_renderclear.c5
-rw-r--r--drivers/gpu/drm/i915/gt/gen8_ppgtt.h7
-rw-r--r--drivers/gpu/drm/i915/gt/intel_engine_cs.c40
-rw-r--r--drivers/gpu/drm/i915/gt/intel_ggtt.c7
-rw-r--r--drivers/gpu/drm/i915/gt/intel_gtt.h5
-rw-r--r--drivers/gpu/drm/i915/gt/selftest_engine_cs.c18
-rw-r--r--drivers/gpu/drm/i915/gt/selftest_workarounds.c10
-rw-r--r--drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c1
8 files changed, 54 insertions, 39 deletions
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index de575fdb033f..21f08e53889c 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -397,7 +397,10 @@ static void emit_batch(struct i915_vma * const vma,
gen7_emit_pipeline_invalidate(&cmds);
batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
- batch_add(&cmds, 0xffff0000);
+ batch_add(&cmds, 0xffff0000 |
+ ((IS_IVB_GT1(i915) || IS_VALLEYVIEW(i915)) ?
+ HIZ_RAW_STALL_OPT_DISABLE :
+ 0));
batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
gen7_emit_pipeline_invalidate(&cmds);
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
index 76a08b9c1f5c..b9028c2ad3c7 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
@@ -6,8 +6,15 @@
#ifndef __GEN8_PPGTT_H__
#define __GEN8_PPGTT_H__
+#include <linux/kernel.h>
+
+struct i915_address_space;
struct intel_gt;
+enum i915_cache_level;
struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
+u64 gen8_ggtt_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags);
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index efe935f80c1a..6dbdbde00f14 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -45,9 +45,9 @@ struct engine_info {
unsigned int hw_id;
u8 class;
u8 instance;
- /* mmio bases table *must* be sorted in reverse gen order */
+ /* mmio bases table *must* be sorted in reverse graphics_ver order */
struct engine_mmio_base {
- u32 gen : 8;
+ u32 graphics_ver : 8;
u32 base : 24;
} mmio_bases[MAX_MMIO_BASES];
};
@@ -58,7 +58,7 @@ static const struct engine_info intel_engines[] = {
.class = RENDER_CLASS,
.instance = 0,
.mmio_bases = {
- { .gen = 1, .base = RENDER_RING_BASE }
+ { .graphics_ver = 1, .base = RENDER_RING_BASE }
},
},
[BCS0] = {
@@ -66,7 +66,7 @@ static const struct engine_info intel_engines[] = {
.class = COPY_ENGINE_CLASS,
.instance = 0,
.mmio_bases = {
- { .gen = 6, .base = BLT_RING_BASE }
+ { .graphics_ver = 6, .base = BLT_RING_BASE }
},
},
[VCS0] = {
@@ -74,9 +74,9 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_DECODE_CLASS,
.instance = 0,
.mmio_bases = {
- { .gen = 11, .base = GEN11_BSD_RING_BASE },
- { .gen = 6, .base = GEN6_BSD_RING_BASE },
- { .gen = 4, .base = BSD_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
+ { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
+ { .graphics_ver = 4, .base = BSD_RING_BASE }
},
},
[VCS1] = {
@@ -84,8 +84,8 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_DECODE_CLASS,
.instance = 1,
.mmio_bases = {
- { .gen = 11, .base = GEN11_BSD2_RING_BASE },
- { .gen = 8, .base = GEN8_BSD2_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
+ { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
},
},
[VCS2] = {
@@ -93,7 +93,7 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_DECODE_CLASS,
.instance = 2,
.mmio_bases = {
- { .gen = 11, .base = GEN11_BSD3_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
},
},
[VCS3] = {
@@ -101,7 +101,7 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_DECODE_CLASS,
.instance = 3,
.mmio_bases = {
- { .gen = 11, .base = GEN11_BSD4_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
},
},
[VECS0] = {
@@ -109,8 +109,8 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 0,
.mmio_bases = {
- { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
- { .gen = 7, .base = VEBOX_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
+ { .graphics_ver = 7, .base = VEBOX_RING_BASE }
},
},
[VECS1] = {
@@ -118,7 +118,7 @@ static const struct engine_info intel_engines[] = {
.class = VIDEO_ENHANCEMENT_CLASS,
.instance = 1,
.mmio_bases = {
- { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
+ { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
},
},
};
@@ -146,9 +146,9 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
switch (class) {
case RENDER_CLASS:
- switch (INTEL_GEN(gt->i915)) {
+ switch (GRAPHICS_VER(gt->i915)) {
default:
- MISSING_CASE(INTEL_GEN(gt->i915));
+ MISSING_CASE(GRAPHICS_VER(gt->i915));
return DEFAULT_LR_CONTEXT_RENDER_SIZE;
case 12:
case 11:
@@ -184,8 +184,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
*/
cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
drm_dbg(&gt->i915->drm,
- "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
- INTEL_GEN(gt->i915), cxt_size * 64,
+ "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
+ GRAPHICS_VER(gt->i915), cxt_size * 64,
cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
case 3:
@@ -201,7 +201,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
case VIDEO_DECODE_CLASS:
case VIDEO_ENHANCEMENT_CLASS:
case COPY_ENGINE_CLASS:
- if (INTEL_GEN(gt->i915) < 8)
+ if (GRAPHICS_VER(gt->i915) < 8)
return 0;
return GEN8_LR_CONTEXT_OTHER_SIZE;
}
@@ -213,7 +213,7 @@ static u32 __engine_mmio_base(struct drm_i915_private *i915,
int i;
for (i = 0; i < MAX_MMIO_BASES; i++)
- if (INTEL_GEN(i915) >= bases[i].gen)
+ if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
break;
GEM_BUG_ON(i == MAX_MMIO_BASES);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 670c1271e7d5..38742bf33fa3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -18,6 +18,7 @@
#include "i915_vgpu.h"
#include "intel_gtt.h"
+#include "gen8_ppgtt.h"
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma);
@@ -187,9 +188,9 @@ static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_gtt_chipset_flush();
}
-static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- u32 flags)
+u64 gen8_ggtt_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen8_pte_t pte = addr | _PAGE_PRESENT;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index e67e34e17913..79f565aeb8c0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -245,6 +245,7 @@ struct i915_address_space {
struct dma_resv resv; /* reservation lock for all pd objects, and buffer pool */
#define VM_CLASS_GGTT 0
#define VM_CLASS_PPGTT 1
+#define VM_CLASS_DPT 2
struct drm_i915_gem_object *scratch[4];
/**
@@ -255,6 +256,9 @@ struct i915_address_space {
/* Global GTT */
bool is_ggtt:1;
+ /* Display page table */
+ bool is_dpt:1;
+
/* Some systems support read-only mappings for GGTT and/or PPGTT */
bool has_read_only:1;
@@ -351,6 +355,7 @@ struct i915_ppgtt {
};
#define i915_is_ggtt(vm) ((vm)->is_ggtt)
+#define i915_is_dpt(vm) ((vm)->is_dpt)
int __must_check
i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index b32814a1f20b..3453eb77c498 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -376,34 +376,34 @@ static int intel_mmio_bases_check(void *arg)
u8 prev = U8_MAX;
for (j = 0; j < MAX_MMIO_BASES; j++) {
- u8 gen = info->mmio_bases[j].gen;
+ u8 ver = info->mmio_bases[j].graphics_ver;
u32 base = info->mmio_bases[j].base;
- if (gen >= prev) {
- pr_err("%s(%s, class:%d, instance:%d): mmio base for gen %x is before the one for gen %x\n",
+ if (ver >= prev) {
+ pr_err("%s(%s, class:%d, instance:%d): mmio base for graphics ver %u is before the one for ver %u\n",
__func__,
intel_engine_class_repr(info->class),
info->class, info->instance,
- prev, gen);
+ prev, ver);
return -EINVAL;
}
- if (gen == 0)
+ if (ver == 0)
break;
if (!base) {
- pr_err("%s(%s, class:%d, instance:%d): invalid mmio base (%x) for gen %x at entry %u\n",
+ pr_err("%s(%s, class:%d, instance:%d): invalid mmio base (%x) for graphics ver %u at entry %u\n",
__func__,
intel_engine_class_repr(info->class),
info->class, info->instance,
- base, gen, j);
+ base, ver, j);
return -EINVAL;
}
- prev = gen;
+ prev = ver;
}
- pr_debug("%s: min gen supported for %s%d is %d\n",
+ pr_debug("%s: min graphics version supported for %s%d is %u\n",
__func__,
intel_engine_class_repr(info->class),
info->instance,
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 19850489a3fc..64937ec3f2dc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -927,7 +927,7 @@ err_batch:
struct regmask {
i915_reg_t reg;
- unsigned long gen_mask;
+ u8 graphics_ver;
};
static bool find_reg(struct drm_i915_private *i915,
@@ -938,7 +938,7 @@ static bool find_reg(struct drm_i915_private *i915,
u32 offset = i915_mmio_reg_offset(reg);
while (count--) {
- if (INTEL_INFO(i915)->gen_mask & tbl->gen_mask &&
+ if (GRAPHICS_VER(i915) == tbl->graphics_ver &&
i915_mmio_reg_offset(tbl->reg) == offset)
return true;
tbl++;
@@ -951,8 +951,8 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
{
/* Alas, we must pardon some whitelists. Mistakes already made */
static const struct regmask pardon[] = {
- { GEN9_CTX_PREEMPT_REG, INTEL_GEN_MASK(9, 9) },
- { GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
+ { GEN9_CTX_PREEMPT_REG, 9 },
+ { GEN8_L3SQCREG4, 9 },
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
@@ -974,7 +974,7 @@ static bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
{
/* Some registers do not seem to behave and our writes unreadable */
static const struct regmask wo[] = {
- { GEN9_SLICE_COMMON_ECO_CHICKEN1, INTEL_GEN_MASK(9, 9) },
+ { GEN9_SLICE_COMMON_ECO_CHICKEN1, 9 },
};
return find_reg(i915, reg, wo, ARRAY_SIZE(wo));
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
index 129e0cf7dfe2..64e0b86bf258 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.c
@@ -121,4 +121,3 @@ void intel_guc_log_debugfs_register(struct intel_guc_log *log,
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), log);
}
-
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 02:51:14 +0000