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path: root/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c24
1 files changed, 16 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7460560fbefc..a1f4a00e5e04 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1044,14 +1044,6 @@ static void reset_back_end_for_pipe(
pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
}
- if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
- if (resource_unreference_clock_source(&context->res_ctx,
- dc->res_pool, pipe_ctx->clock_source)) {
- pipe_ctx->clock_source->funcs->cs_power_down(pipe_ctx->clock_source);
- pipe_ctx->clock_source = NULL;
- }
-
-
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
break;
@@ -1273,6 +1265,22 @@ static void reset_hw_ctx_wrap(
plane_atomic_power_down(dc, i);
}
+ /* power down changed clock sources */
+ for (i = 0; i < dc->res_pool->clk_src_count; i++)
+ if (context->res_ctx.clock_source_changed[i]) {
+ struct clock_source *clk = dc->res_pool->clock_sources[i];
+
+ clk->funcs->cs_power_down(clk);
+ context->res_ctx.clock_source_changed[i] = false;
+ }
+
+ if (context->res_ctx.dp_clock_source_changed) {
+ struct clock_source *clk = dc->res_pool->dp_clock_source;
+
+ clk->funcs->cs_power_down(clk);
+ context->res_ctx.dp_clock_source_changed = false;
+ }
+
/* Reset Back End*/
for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
struct pipe_ctx *pipe_ctx_old =