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-rw-r--r--arch/x86/mm/tlb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index dbbcfd59726a..37689a7cc03b 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -241,7 +241,7 @@ void initialize_tlbstate_and_flush(void)
* doesn't work like other CR4 bits because it can only be set from
* long mode.)
*/
- WARN_ON(boot_cpu_has(X86_CR4_PCIDE) &&
+ WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
!(cr4_read_shadow() & X86_CR4_PCIDE));
/* Force ASID 0 and force a TLB flush. */