diff options
Diffstat (limited to 'arch/ppc/platforms')
| -rw-r--r-- | arch/ppc/platforms/4xx/ebony.c | 2 | ||||
| -rw-r--r-- | arch/ppc/platforms/pmac_setup.c | 2 | ||||
| -rw-r--r-- | arch/ppc/platforms/radstone_ppc7d.c | 8 |
3 files changed, 6 insertions, 6 deletions
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c index d6b2b1965dcb..9decb72e7aaf 100644 --- a/arch/ppc/platforms/4xx/ebony.c +++ b/arch/ppc/platforms/4xx/ebony.c @@ -91,7 +91,7 @@ ebony_calibrate_decr(void) * on Rev. C silicon then errata forces us to * use the internal clock. */ - if (strcmp(cur_cpu_spec[0]->cpu_name, "440GP Rev. B") == 0) + if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0) freq = EBONY_440GP_RB_SYSCLK; else freq = EBONY_440GP_RC_SYSCLK; diff --git a/arch/ppc/platforms/pmac_setup.c b/arch/ppc/platforms/pmac_setup.c index 1ad779ecc8fc..e6a12182bfbb 100644 --- a/arch/ppc/platforms/pmac_setup.c +++ b/arch/ppc/platforms/pmac_setup.c @@ -448,7 +448,7 @@ static int pmac_pm_enter(suspend_state_t state) enable_kernel_fp(); #ifdef CONFIG_ALTIVEC - if (cur_cpu_spec[0]->cpu_features & CPU_FTR_ALTIVEC) + if (cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC) enable_kernel_altivec(); #endif /* CONFIG_ALTIVEC */ diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c index c30607a972d8..06ec30f7e2f4 100644 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ b/arch/ppc/platforms/radstone_ppc7d.c @@ -1185,18 +1185,18 @@ static void __init ppc7d_setup_arch(void) ROOT_DEV = Root_HDA1; #endif - if ((cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450) || - (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR)) + if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) || + (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)) /* 745x is different. We only want to pass along enable. */ _set_L2CR(L2CR_L2E); - else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR) + else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR) /* All modules have 1MB of L2. We also assume that an * L2 divisor of 3 will work. */ _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); - if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) + if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR) /* No L3 cache */ _set_L3CR(0); |