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-rw-r--r--arch/blackfin/mach-common/Makefile5
-rw-r--r--arch/blackfin/mach-common/arch_checks.c13
-rw-r--r--arch/blackfin/mach-common/cache.S115
-rw-r--r--arch/blackfin/mach-common/cacheinit.S77
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S663
-rw-r--r--arch/blackfin/mach-common/entry.S42
-rw-r--r--arch/blackfin/mach-common/head.S207
-rw-r--r--arch/blackfin/mach-common/interrupt.S4
-rw-r--r--arch/blackfin/mach-common/ints-priority.c72
-rw-r--r--arch/blackfin/mach-common/lock.S45
-rw-r--r--arch/blackfin/mach-common/pm.c226
11 files changed, 1141 insertions, 328 deletions
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 422bfee34adc..e6ed57c56d4b 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -3,9 +3,10 @@
#
obj-y := \
- cache.o cacheinit.o entry.o \
- interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
+ cache.o entry.o head.o \
+ interrupt.o irqpanic.o arch_checks.o ints-priority.o
+obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o
obj-$(CONFIG_PM) += pm.o dpmc_modes.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index caaab49e9cfa..98133b968f7b 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -27,8 +27,9 @@
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <asm/mach/anomaly.h>
-#include <asm/mach-common/clocks.h>
+#include <asm/fixed_code.h>
+#include <mach/anomaly.h>
+#include <asm/clocks.h>
#ifdef CONFIG_BFIN_KERNEL_CLOCK
@@ -54,8 +55,10 @@
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
-#ifdef CONFIG_MEM_SIZE
-#if (CONFIG_MEM_SIZE % 4)
-#error "SDRAM mem size must be multible of 4MB"
+#if CONFIG_BOOT_LOAD < FIXED_CODE_END
+# error "The kernel load address must be after the fixed code section"
#endif
+
+#if (CONFIG_BOOT_LOAD & 0x3)
+# error "The kernel load address must be 4 byte aligned"
#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 0521b1588204..85f8c79b3c37 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -34,81 +34,6 @@
#include <asm/cache.h>
.text
-.align 2
-ENTRY(_cache_invalidate)
-
- /*
- * Icache or DcacheA or DcacheB Invalidation
- * or any combination thereof
- * R0 has bits
- * CPLB_ENABLE_ICACHE_P,CPLB_ENABLE_DCACHE_P,CPLB_ENABLE_DCACHE2_P
- * set as required
- */
- [--SP] = R7;
-
- R7 = R0;
- CC = BITTST(R7,CPLB_ENABLE_ICACHE_P);
- IF !CC JUMP .Lno_icache;
- [--SP] = RETS;
- CALL _icache_invalidate;
- RETS = [SP++];
-.Lno_icache:
- CC = BITTST(R7,CPLB_ENABLE_DCACHE_P);
- IF !CC JUMP .Lno_dcache_a;
- R0 = 0; /* specifies bank A */
- [--SP] = RETS;
- CALL _dcache_invalidate;
- RETS = [SP++];
-.Lno_dcache_a:
- CC = BITTST(R7,CPLB_ENABLE_DCACHE2_P);
- IF !CC JUMP .Lno_dcache_b;
- R0 = 0;
- BITSET(R0, 23); /* specifies bank B */
- [--SP] = RETS;
- CALL _dcache_invalidate;
- RETS = [SP++];
-.Lno_dcache_b:
- R7 = [SP++];
- RTS;
-ENDPROC(_cache_invalidate)
-
-/* Invalidate the Entire Instruction cache by
- * disabling IMC bit
- */
-ENTRY(_icache_invalidate)
-ENTRY(_invalidate_entire_icache)
- [--SP] = ( R7:5);
-
- P0.L = LO(IMEM_CONTROL);
- P0.H = HI(IMEM_CONTROL);
- R7 = [P0];
-
- /* Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
- BITCLR(R7,IMC_P);
- CLI R6;
- SSYNC; /* SSYNC required before invalidating cache. */
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- /* Configures the instruction cache agian */
- R6 = (IMC | ENICPLB);
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- ( R7:5) = [SP++];
- RTS;
-ENDPROC(_invalidate_entire_icache)
-ENDPROC(_icache_invalidate)
/*
* blackfin_cache_flush_range(start, end)
@@ -190,46 +115,6 @@ ENTRY(_blackfin_dcache_invalidate_range)
RTS;
ENDPROC(_blackfin_dcache_invalidate_range)
-/* Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-ENTRY(_invalidate_entire_dcache)
-ENTRY(_dcache_invalidate)
- [--SP] = ( R7:6);
-
- P0.L = LO(DMEM_CONTROL);
- P0.H = HI(DMEM_CONTROL);
- R7 = [P0];
-
- /* Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
- BITCLR(R7,DMC0_P);
- BITCLR(R7,DMC1_P);
- CLI R6;
- SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- /* Configures the data cache again */
-
- R6 = DMEM_CNTR;
- R7 = R7 | R6;
-
- CLI R6;
- SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
- .align 8;
- [P0] = R7;
- SSYNC;
- STI R6;
-
- ( R7:6) = [SP++];
- RTS;
-ENDPROC(_dcache_invalidate)
-ENDPROC(_invalidate_entire_dcache)
-
ENTRY(_blackfin_dcache_flush_range)
R2 = -L1_CACHE_BYTES;
R2 = R0 & R2;
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
deleted file mode 100644
index 22fada0c1cb3..000000000000
--- a/arch/blackfin/mach-common/cacheinit.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * File: arch/blackfin/mach-common/cacheinit.S
- * Based on:
- * Author: LG Soft India
- *
- * Created: ?
- * Description: cache initialization
- *
- * Modified:
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This function sets up the data and instruction cache. The
- * tables like icplb table, dcplb table and Page Descriptor table
- * are defined in cplbtab.h. You can configure those tables for
- * your suitable requirements
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-.text
-
-#if ANOMALY_05000125
-#if defined(CONFIG_BFIN_ICACHE)
-ENTRY(_bfin_write_IMEM_CONTROL)
-
- /* Enable Instruction Cache */
- P0.l = LO(IMEM_CONTROL);
- P0.h = HI(IMEM_CONTROL);
-
- /* Anomaly 05000125 */
- CLI R1;
- SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
- .align 8;
- [P0] = R0;
- SSYNC;
- STI R1;
- RTS;
-
-ENDPROC(_bfin_write_IMEM_CONTROL)
-#endif
-
-#if defined(CONFIG_BFIN_DCACHE)
-ENTRY(_bfin_write_DMEM_CONTROL)
- P0.l = LO(DMEM_CONTROL);
- P0.h = HI(DMEM_CONTROL);
-
- CLI R1;
- SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
- .align 8;
- [P0] = R0;
- SSYNC;
- STI R1;
- RTS;
-
-ENDPROC(_bfin_write_DMEM_CONTROL)
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index b7981d31c392..ad5431e2cd05 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -6,8 +6,8 @@
#include <linux/linkage.h>
#include <asm/blackfin.h>
-#include <asm/mach/irq.h>
-
+#include <mach/irq.h>
+#include <asm/dpmc.h>
.section .l1.text
@@ -51,86 +51,32 @@ ENTRY(_sleep_mode)
RETS = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
+ENDPROC(_sleep_mode)
ENTRY(_hibernate_mode)
[--SP] = ( R7:0, P5:0 );
[--SP] = RETS;
+ R3 = R0;
+ R0 = IWR_DISABLE_ALL;
+ R1 = IWR_DISABLE_ALL;
+ R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
+ call _set_dram_srfs;
+ SSYNC;
R0 = 0xFFFF (Z);
call _set_rtc_istat;
P0.H = hi(VR_CTL);
P0.L = lo(VR_CTL);
- R1 = W[P0](z);
- BITSET (R1, 8);
- BITCLR (R1, 0);
- BITCLR (R1, 1);
- W[P0] = R1.L;
- SSYNC;
+ W[P0] = R3.L;
CLI R2;
IDLE;
-
- /* Actually, adding anything may not be necessary...SDRAM contents
- * are lost
- */
-
-ENTRY(_deep_sleep)
- [--SP] = ( R7:0, P5:0 );
- [--SP] = RETS;
-
- CLI R4;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
-
- call _set_dram_srfs;
-
- /* Clear all the interrupts,bits sticky */
- R0 = 0xFFFF (Z);
- call _set_rtc_istat
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R0 = W[P0](z);
- BITSET (R0, 5);
- W[P0] = R0.L;
-
- call _test_pll_locked;
-
- SSYNC;
- IDLE;
-
- call _unset_dram_srfs;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R0 = w[p0](z);
- BITCLR (R0, 3);
- BITCLR (R0, 5);
- BITCLR (R0, 8);
- w[p0] = R0;
- IDLE;
- call _test_pll_locked;
-
- STI R4;
-
- RETS = [SP++];
- ( R7:0, P5:0 ) = [SP++];
- RTS;
+.Lforever:
+ jump .Lforever;
+ENDPROC(_hibernate_mode)
ENTRY(_sleep_deeper)
[--SP] = ( R7:0, P5:0 );
@@ -232,53 +178,73 @@ ENTRY(_sleep_deeper)
RETS = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
+ENDPROC(_sleep_deeper)
ENTRY(_set_dram_srfs)
/* set the dram to self refresh mode */
-#if defined(CONFIG_BF54x)
+ SSYNC;
+#if defined(EBIU_RSTCTL) /* DDR */
P0.H = hi(EBIU_RSTCTL);
P0.L = lo(EBIU_RSTCTL);
R2 = [P0];
- R3.H = hi(SRREQ);
- R3.L = lo(SRREQ);
-#else
- P0.H = hi(EBIU_SDGCTL);
+ BITSET(R2, 3); /* SRREQ enter self-refresh mode */
+ [P0] = R2;
+ SSYNC;
+1:
+ R2 = [P0];
+ CC = BITTST(R2, 4);
+ if !CC JUMP 1b;
+#else /* SDRAM */
P0.L = lo(EBIU_SDGCTL);
+ P0.H = hi(EBIU_SDGCTL);
R2 = [P0];
- R3.H = hi(SRFS);
- R3.L = lo(SRFS);
-#endif
- R2 = R2|R3;
+ BITSET(R2, 24); /* SRFS enter self-refresh mode */
[P0] = R2;
- ssync;
-#if defined(CONFIG_BF54x)
-.LSRR_MODE:
+ SSYNC;
+
+ P0.L = lo(EBIU_SDSTAT);
+ P0.H = hi(EBIU_SDSTAT);
+1:
+ R2 = w[P0];
+ SSYNC;
+ cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
+ if !cc jump 1b;
+
+ P0.L = lo(EBIU_SDGCTL);
+ P0.H = hi(EBIU_SDGCTL);
R2 = [P0];
- CC = BITTST(R2, 4);
- if !CC JUMP .LSRR_MODE;
+ BITCLR(R2, 0); /* SCTLE disable CLKOUT */
+ [P0] = R2;
#endif
RTS;
+ENDPROC(_set_dram_srfs)
ENTRY(_unset_dram_srfs)
/* set the dram out of self refresh mode */
-#if defined(CONFIG_BF54x)
+#if defined(EBIU_RSTCTL) /* DDR */
P0.H = hi(EBIU_RSTCTL);
P0.L = lo(EBIU_RSTCTL);
R2 = [P0];
- R3.H = hi(SRREQ);
- R3.L = lo(SRREQ);
-#else
+ BITCLR(R2, 3); /* clear SRREQ bit */
+ [P0] = R2;
+#elif defined(EBIU_SDGCTL) /* SDRAM */
+
+ P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
+ P0.H = hi(EBIU_SDGCTL);
+ R2 = [P0];
+ BITSET(R2, 0); /* SCTLE enable CLKOUT */
+ [P0] = R2
+ SSYNC;
+
+ P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
P0.H = hi(EBIU_SDGCTL);
- P0.L = lo(EBIU_SDGCTL);
R2 = [P0];
- R3.H = hi(SRFS);
- R3.L = lo(SRFS);
+ BITCLR(R2, 24); /* clear SRFS bit */
+ [P0] = R2
#endif
- R3 = ~R3;
- R2 = R2&R3;
- [P0] = R2;
- ssync;
+ SSYNC;
RTS;
+ENDPROC(_unset_dram_srfs)
ENTRY(_set_sic_iwr)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
@@ -300,6 +266,7 @@ ENTRY(_set_sic_iwr)
SSYNC;
RTS;
+ENDPROC(_set_sic_iwr)
ENTRY(_set_rtc_istat)
#ifndef CONFIG_BF561
@@ -307,8 +274,14 @@ ENTRY(_set_rtc_istat)
P0.L = lo(RTC_ISTAT);
w[P0] = R0.L;
SSYNC;
+#elif (ANOMALY_05000371)
+ nop;
+ nop;
+ nop;
+ nop;
#endif
RTS;
+ENDPROC(_set_rtc_istat)
ENTRY(_test_pll_locked)
P0.H = hi(PLL_STAT);
@@ -318,3 +291,509 @@ ENTRY(_test_pll_locked)
CC = BITTST(R0,5);
IF !CC JUMP 1b;
RTS;
+ENDPROC(_test_pll_locked)
+
+.section .text
+
+ENTRY(_do_hibernate)
+ [--SP] = ( R7:0, P5:0 );
+ [--SP] = RETS;
+ /* Save System MMRs */
+ R2 = R0;
+ P0.H = hi(PLL_CTL);
+ P0.L = lo(PLL_CTL);
+
+#ifdef SIC_IMASK0
+ PM_SYS_PUSH(SIC_IMASK0)
+#endif
+#ifdef SIC_IMASK1
+ PM_SYS_PUSH(SIC_IMASK1)
+#endif
+#ifdef SIC_IMASK2
+ PM_SYS_PUSH(SIC_IMASK2)
+#endif
+#ifdef SIC_IMASK
+ PM_SYS_PUSH(SIC_IMASK)
+#endif
+#ifdef SICA_IMASK0
+ PM_SYS_PUSH(SICA_IMASK0)
+#endif
+#ifdef SICA_IMASK1
+ PM_SYS_PUSH(SICA_IMASK1)
+#endif
+#ifdef SIC_IAR2
+ PM_SYS_PUSH(SIC_IAR0)
+ PM_SYS_PUSH(SIC_IAR1)
+ PM_SYS_PUSH(SIC_IAR2)
+#endif
+#ifdef SIC_IAR3
+ PM_SYS_PUSH(SIC_IAR3)
+#endif
+#ifdef SIC_IAR4
+ PM_SYS_PUSH(SIC_IAR4)
+ PM_SYS_PUSH(SIC_IAR5)
+ PM_SYS_PUSH(SIC_IAR6)
+#endif
+#ifdef SIC_IAR7
+ PM_SYS_PUSH(SIC_IAR7)
+#endif
+#ifdef SIC_IAR8
+ PM_SYS_PUSH(SIC_IAR8)
+ PM_SYS_PUSH(SIC_IAR9)
+ PM_SYS_PUSH(SIC_IAR10)
+ PM_SYS_PUSH(SIC_IAR11)
+#endif
+
+#ifdef SICA_IAR0
+ PM_SYS_PUSH(SICA_IAR0)
+ PM_SYS_PUSH(SICA_IAR1)
+ PM_SYS_PUSH(SICA_IAR2)
+ PM_SYS_PUSH(SICA_IAR3)
+ PM_SYS_PUSH(SICA_IAR4)
+ PM_SYS_PUSH(SICA_IAR5)
+ PM_SYS_PUSH(SICA_IAR6)
+ PM_SYS_PUSH(SICA_IAR7)
+#endif
+
+#ifdef SIC_IWR
+ PM_SYS_PUSH(SIC_IWR)
+#endif
+#ifdef SIC_IWR0
+ PM_SYS_PUSH(SIC_IWR0)
+#endif
+#ifdef SIC_IWR1
+ PM_SYS_PUSH(SIC_IWR1)
+#endif
+#ifdef SIC_IWR2
+ PM_SYS_PUSH(SIC_IWR2)
+#endif
+#ifdef SICA_IWR0
+ PM_SYS_PUSH(SICA_IWR0)
+#endif
+#ifdef SICA_IWR1
+ PM_SYS_PUSH(SICA_IWR1)
+#endif
+
+#ifdef PINT0_ASSIGN
+ PM_SYS_PUSH(PINT0_ASSIGN)
+ PM_SYS_PUSH(PINT1_ASSIGN)
+ PM_SYS_PUSH(PINT2_ASSIGN)
+ PM_SYS_PUSH(PINT3_ASSIGN)
+#endif
+
+ PM_SYS_PUSH(EBIU_AMBCTL0)
+ PM_SYS_PUSH(EBIU_AMBCTL1)
+ PM_SYS_PUSH16(EBIU_AMGCTL)
+
+#ifdef EBIU_FCTL
+ PM_SYS_PUSH(EBIU_MBSCTL)
+ PM_SYS_PUSH(EBIU_MODE)
+ PM_SYS_PUSH(EBIU_FCTL)
+#endif
+
+ PM_SYS_PUSH16(SYSCR)
+
+ /* Save Core MMRs */
+ P0.H = hi(SRAM_BASE_ADDRESS);
+ P0.L = lo(SRAM_BASE_ADDRESS);
+
+ PM_PUSH(DMEM_CONTROL)
+ PM_PUSH(DCPLB_ADDR0)
+ PM_PUSH(DCPLB_ADDR1)
+ PM_PUSH(DCPLB_ADDR2)
+ PM_PUSH(DCPLB_ADDR3)
+ PM_PUSH(DCPLB_ADDR4)
+ PM_PUSH(DCPLB_ADDR5)
+ PM_PUSH(DCPLB_ADDR6)
+ PM_PUSH(DCPLB_ADDR7)
+ PM_PUSH(DCPLB_ADDR8)
+ PM_PUSH(DCPLB_ADDR9)
+ PM_PUSH(DCPLB_ADDR10)
+ PM_PUSH(DCPLB_ADDR11)
+ PM_PUSH(DCPLB_ADDR12)
+ PM_PUSH(DCPLB_ADDR13)
+ PM_PUSH(DCPLB_ADDR14)
+ PM_PUSH(DCPLB_ADDR15)
+ PM_PUSH(DCPLB_DATA0)
+ PM_PUSH(DCPLB_DATA1)
+ PM_PUSH(DCPLB_DATA2)
+ PM_PUSH(DCPLB_DATA3)
+ PM_PUSH(DCPLB_DATA4)
+ PM_PUSH(DCPLB_DATA5)
+ PM_PUSH(DCPLB_DATA6)
+ PM_PUSH(DCPLB_DATA7)
+ PM_PUSH(DCPLB_DATA8)
+ PM_PUSH(DCPLB_DATA9)
+ PM_PUSH(DCPLB_DATA10)
+ PM_PUSH(DCPLB_DATA11)
+ PM_PUSH(DCPLB_DATA12)
+ PM_PUSH(DCPLB_DATA13)
+ PM_PUSH(DCPLB_DATA14)
+ PM_PUSH(DCPLB_DATA15)
+ PM_PUSH(IMEM_CONTROL)
+ PM_PUSH(ICPLB_ADDR0)
+ PM_PUSH(ICPLB_ADDR1)
+ PM_PUSH(ICPLB_ADDR2)
+ PM_PUSH(ICPLB_ADDR3)
+ PM_PUSH(ICPLB_ADDR4)
+ PM_PUSH(ICPLB_ADDR5)
+ PM_PUSH(ICPLB_ADDR6)
+ PM_PUSH(ICPLB_ADDR7)
+ PM_PUSH(ICPLB_ADDR8)
+ PM_PUSH(ICPLB_ADDR9)
+ PM_PUSH(ICPLB_ADDR10)
+ PM_PUSH(ICPLB_ADDR11)
+ PM_PUSH(ICPLB_ADDR12)
+ PM_PUSH(ICPLB_ADDR13)
+ PM_PUSH(ICPLB_ADDR14)
+ PM_PUSH(ICPLB_ADDR15)
+ PM_PUSH(ICPLB_DATA0)
+ PM_PUSH(ICPLB_DATA1)
+ PM_PUSH(ICPLB_DATA2)
+ PM_PUSH(ICPLB_DATA3)
+ PM_PUSH(ICPLB_DATA4)
+ PM_PUSH(ICPLB_DATA5)
+ PM_PUSH(ICPLB_DATA6)
+ PM_PUSH(ICPLB_DATA7)
+ PM_PUSH(ICPLB_DATA8)
+ PM_PUSH(ICPLB_DATA9)
+ PM_PUSH(ICPLB_DATA10)
+ PM_PUSH(ICPLB_DATA11)
+ PM_PUSH(ICPLB_DATA12)
+ PM_PUSH(ICPLB_DATA13)
+ PM_PUSH(ICPLB_DATA14)
+ PM_PUSH(ICPLB_DATA15)
+ PM_PUSH(EVT0)
+ PM_PUSH(EVT1)
+ PM_PUSH(EVT2)
+ PM_PUSH(EVT3)
+ PM_PUSH(EVT4)
+ PM_PUSH(EVT5)
+ PM_PUSH(EVT6)
+ PM_PUSH(EVT7)
+ PM_PUSH(EVT8)
+ PM_PUSH(EVT9)
+ PM_PUSH(EVT10)
+ PM_PUSH(EVT11)
+ PM_PUSH(EVT12)
+ PM_PUSH(EVT13)
+ PM_PUSH(EVT14)
+ PM_PUSH(EVT15)
+ PM_PUSH(IMASK)
+ PM_PUSH(ILAT)
+ PM_PUSH(IPRIO)
+ PM_PUSH(TCNTL)
+ PM_PUSH(TPERIOD)
+ PM_PUSH(TSCALE)
+ PM_PUSH(TCOUNT)
+ PM_PUSH(TBUFCTL)
+
+ /* Save Core Registers */
+ [--sp] = SYSCFG;
+ [--sp] = ( R7:0, P5:0 );
+ [--sp] = fp;
+ [--sp] = usp;
+
+ [--sp] = i0;
+ [--sp] = i1;
+ [--sp] = i2;
+ [--sp] = i3;
+
+ [--sp] = m0;
+ [--sp] = m1;
+ [--sp] = m2;
+ [--sp] = m3;
+
+ [--sp] = l0;
+ [--sp] = l1;
+ [--sp] = l2;
+ [--sp] = l3;
+
+ [--sp] = b0;
+ [--sp] = b1;
+ [--sp] = b2;
+ [--sp] = b3;
+ [--sp] = a0.x;
+ [--sp] = a0.w;
+ [--sp] = a1.x;
+ [--sp] = a1.w;
+
+ [--sp] = LC0;
+ [--sp] = LC1;
+ [--sp] = LT0;
+ [--sp] = LT1;
+ [--sp] = LB0;
+ [--sp] = LB1;
+
+ [--sp] = ASTAT;
+ [--sp] = CYCLES;
+ [--sp] = CYCLES2;
+
+ [--sp] = RETS;
+ r0 = RETI;
+ [--sp] = r0;
+ [--sp] = RETX;
+ [--sp] = RETN;
+ [--sp] = RETE;
+ [--sp] = SEQSTAT;
+
+ /* Save Magic, return address and Stack Pointer */
+ P0.H = 0;
+ P0.L = 0;
+ R0.H = 0xDEAD; /* Hibernate Magic */
+ R0.L = 0xBEEF;
+ [P0++] = R0; /* Store Hibernate Magic */
+ R0.H = .Lpm_resume_here;
+ R0.L = .Lpm_resume_here;
+ [P0++] = R0; /* Save Return Address */
+ [P0++] = SP; /* Save Stack Pointer */
+ P0.H = _hibernate_mode;
+ P0.L = _hibernate_mode;
+ R0 = R2;
+ call (P0); /* Goodbye */
+
+.Lpm_resume_here:
+
+ /* Restore Core Registers */
+ SEQSTAT = [sp++];
+ RETE = [sp++];
+ RETN = [sp++];
+ RETX = [sp++];
+ r0 = [sp++];
+ RETI = r0;
+ RETS = [sp++];
+
+ CYCLES2 = [sp++];
+ CYCLES = [sp++];
+ ASTAT = [sp++];
+
+ LB1 = [sp++];
+ LB0 = [sp++];
+ LT1 = [sp++];
+ LT0 = [sp++];
+ LC1 = [sp++];
+ LC0 = [sp++];
+
+ a1.w = [sp++];
+ a1.x = [sp++];
+ a0.w = [sp++];
+ a0.x = [sp++];
+ b3 = [sp++];
+ b2 = [sp++];
+ b1 = [sp++];
+ b0 = [sp++];
+
+ l3 = [sp++];
+ l2 = [sp++];
+ l1 = [sp++];
+ l0 = [sp++];
+
+ m3 = [sp++];
+ m2 = [sp++];
+ m1 = [sp++];
+ m0 = [sp++];
+
+ i3 = [sp++];
+ i2 = [sp++];
+ i1 = [sp++];
+ i0 = [sp++];
+
+ usp = [sp++];
+ fp = [sp++];
+
+ ( R7 : 0, P5 : 0) = [ SP ++ ];
+ SYSCFG = [sp++];
+
+ /* Restore Core MMRs */
+
+ PM_POP(TBUFCTL)
+ PM_POP(TCOUNT)
+ PM_POP(TSCALE)
+ PM_POP(TPERIOD)
+ PM_POP(TCNTL)
+ PM_POP(IPRIO)
+ PM_POP(ILAT)
+ PM_POP(IMASK)
+ PM_POP(EVT15)
+ PM_POP(EVT14)
+ PM_POP(EVT13)
+ PM_POP(EVT12)
+ PM_POP(EVT11)
+ PM_POP(EVT10)
+ PM_POP(EVT9)
+ PM_POP(EVT8)
+ PM_POP(EVT7)
+ PM_POP(EVT6)
+ PM_POP(EVT5)
+ PM_POP(EVT4)
+ PM_POP(EVT3)
+ PM_POP(EVT2)
+ PM_POP(EVT1)
+ PM_POP(EVT0)
+ PM_POP(ICPLB_DATA15)
+ PM_POP(ICPLB_DATA14)
+ PM_POP(ICPLB_DATA13)
+ PM_POP(ICPLB_DATA12)
+ PM_POP(ICPLB_DATA11)
+ PM_POP(ICPLB_DATA10)
+ PM_POP(ICPLB_DATA9)
+ PM_POP(ICPLB_DATA8)
+ PM_POP(ICPLB_DATA7)
+ PM_POP(ICPLB_DATA6)
+ PM_POP(ICPLB_DATA5)
+ PM_POP(ICPLB_DATA4)
+ PM_POP(ICPLB_DATA3)
+ PM_POP(ICPLB_DATA2)
+ PM_POP(ICPLB_DATA1)
+ PM_POP(ICPLB_DATA0)
+ PM_POP(ICPLB_ADDR15)
+ PM_POP(ICPLB_ADDR14)
+ PM_POP(ICPLB_ADDR13)
+ PM_POP(ICPLB_ADDR12)
+ PM_POP(ICPLB_ADDR11)
+ PM_POP(ICPLB_ADDR10)
+ PM_POP(ICPLB_ADDR9)
+ PM_POP(ICPLB_ADDR8)
+ PM_POP(ICPLB_ADDR7)
+ PM_POP(ICPLB_ADDR6)
+ PM_POP(ICPLB_ADDR5)
+ PM_POP(ICPLB_ADDR4)
+ PM_POP(ICPLB_ADDR3)
+ PM_POP(ICPLB_ADDR2)
+ PM_POP(ICPLB_ADDR1)
+ PM_POP(ICPLB_ADDR0)
+ PM_POP(IMEM_CONTROL)
+ PM_POP(DCPLB_DATA15)
+ PM_POP(DCPLB_DATA14)
+ PM_POP(DCPLB_DATA13)
+ PM_POP(DCPLB_DATA12)
+ PM_POP(DCPLB_DATA11)
+ PM_POP(DCPLB_DATA10)
+ PM_POP(DCPLB_DATA9)
+ PM_POP(DCPLB_DATA8)
+ PM_POP(DCPLB_DATA7)
+ PM_POP(DCPLB_DATA6)
+ PM_POP(DCPLB_DATA5)
+ PM_POP(DCPLB_DATA4)
+ PM_POP(DCPLB_DATA3)
+ PM_POP(DCPLB_DATA2)
+ PM_POP(DCPLB_DATA1)
+ PM_POP(DCPLB_DATA0)
+ PM_POP(DCPLB_ADDR15)
+ PM_POP(DCPLB_ADDR14)
+ PM_POP(DCPLB_ADDR13)
+ PM_POP(DCPLB_ADDR12)
+ PM_POP(DCPLB_ADDR11)
+ PM_POP(DCPLB_ADDR10)
+ PM_POP(DCPLB_ADDR9)
+ PM_POP(DCPLB_ADDR8)
+ PM_POP(DCPLB_ADDR7)
+ PM_POP(DCPLB_ADDR6)
+ PM_POP(DCPLB_ADDR5)
+ PM_POP(DCPLB_ADDR4)
+ PM_POP(DCPLB_ADDR3)
+ PM_POP(DCPLB_ADDR2)
+ PM_POP(DCPLB_ADDR1)
+ PM_POP(DCPLB_ADDR0)
+ PM_POP(DMEM_CONTROL)
+
+ /* Restore System MMRs */
+
+ P0.H = hi(PLL_CTL);
+ P0.L = lo(PLL_CTL);
+ PM_SYS_POP16(SYSCR)
+
+#ifdef EBIU_FCTL
+ PM_SYS_POP(EBIU_FCTL)
+ PM_SYS_POP(EBIU_MODE)
+ PM_SYS_POP(EBIU_MBSCTL)
+#endif
+ PM_SYS_POP16(EBIU_AMGCTL)
+ PM_SYS_POP(EBIU_AMBCTL1)
+ PM_SYS_POP(EBIU_AMBCTL0)
+
+#ifdef PINT0_ASSIGN
+ PM_SYS_POP(PINT3_ASSIGN)
+ PM_SYS_POP(PINT2_ASSIGN)
+ PM_SYS_POP(PINT1_ASSIGN)
+ PM_SYS_POP(PINT0_ASSIGN)
+#endif
+
+#ifdef SICA_IWR1
+ PM_SYS_POP(SICA_IWR1)
+#endif
+#ifdef SICA_IWR0
+ PM_SYS_POP(SICA_IWR0)
+#endif
+#ifdef SIC_IWR2
+ PM_SYS_POP(SIC_IWR2)
+#endif
+#ifdef SIC_IWR1
+ PM_SYS_POP(SIC_IWR1)
+#endif
+#ifdef SIC_IWR0
+ PM_SYS_POP(SIC_IWR0)
+#endif
+#ifdef SIC_IWR
+ PM_SYS_POP(SIC_IWR)
+#endif
+
+#ifdef SICA_IAR0
+ PM_SYS_POP(SICA_IAR7)
+ PM_SYS_POP(SICA_IAR6)
+ PM_SYS_POP(SICA_IAR5)
+ PM_SYS_POP(SICA_IAR4)
+ PM_SYS_POP(SICA_IAR3)
+ PM_SYS_POP(SICA_IAR2)
+ PM_SYS_POP(SICA_IAR1)
+ PM_SYS_POP(SICA_IAR0)
+#endif
+
+#ifdef SIC_IAR8
+ PM_SYS_POP(SIC_IAR11)
+ PM_SYS_POP(SIC_IAR10)
+ PM_SYS_POP(SIC_IAR9)
+ PM_SYS_POP(SIC_IAR8)
+#endif
+#ifdef SIC_IAR7
+ PM_SYS_POP(SIC_IAR7)
+#endif
+#ifdef SIC_IAR6
+ PM_SYS_POP(SIC_IAR6)
+ PM_SYS_POP(SIC_IAR5)
+ PM_SYS_POP(SIC_IAR4)
+#endif
+#ifdef SIC_IAR3
+ PM_SYS_POP(SIC_IAR3)
+#endif
+#ifdef SIC_IAR2
+ PM_SYS_POP(SIC_IAR2)
+ PM_SYS_POP(SIC_IAR1)
+ PM_SYS_POP(SIC_IAR0)
+#endif
+#ifdef SICA_IMASK1
+ PM_SYS_POP(SICA_IMASK1)
+#endif
+#ifdef SICA_IMASK0
+ PM_SYS_POP(SICA_IMASK0)
+#endif
+#ifdef SIC_IMASK
+ PM_SYS_POP(SIC_IMASK)
+#endif
+#ifdef SIC_IMASK2
+ PM_SYS_POP(SIC_IMASK2)
+#endif
+#ifdef SIC_IMASK1
+ PM_SYS_POP(SIC_IMASK1)
+#endif
+#ifdef SIC_IMASK0
+ PM_SYS_POP(SIC_IMASK0)
+#endif
+
+ [--sp] = RETI; /* Clear Global Interrupt Disable */
+ SP += 4;
+
+ RETS = [SP++];
+ ( R7:0, P5:0 ) = [SP++];
+ RTS;
+ENDPROC(_do_hibernate)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 038f70e0be65..847c172a99eb 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -43,7 +43,7 @@
#include <asm/asm-offsets.h>
#include <asm/trace.h>
-#include <asm/mach-common/context.S>
+#include <asm/context.S>
#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
# define EX_SCRATCH_REG RETN
@@ -158,6 +158,39 @@ ENTRY(_ex_single_step)
cc = r7 == r6;
if cc jump _bfin_return_from_exception;
+#ifdef CONFIG_KGDB
+ /* Don't do single step in hardware exception handler */
+ p5.l = lo(IPEND);
+ p5.h = hi(IPEND);
+ r6 = [p5];
+ cc = bittst(r6, 4);
+ if cc jump _bfin_return_from_exception;
+ cc = bittst(r6, 5);
+ if cc jump _bfin_return_from_exception;
+
+ /* skip single step if current interrupt priority is higher than
+ * that of the first instruction, from which gdb starts single step */
+ r6 >>= 6;
+ r7 = 10;
+.Lfind_priority_start:
+ cc = bittst(r6, 0);
+ if cc jump .Lfind_priority_done;
+ r6 >>= 1;
+ r7 += -1;
+ cc = r7 == 0;
+ if cc jump .Lfind_priority_done;
+ jump.s .Lfind_priority_start;
+.Lfind_priority_done:
+ p4.l = _debugger_step;
+ p4.h = _debugger_step;
+ r6 = [p4];
+ cc = r6 == 0;
+ if cc jump .Ldo_single_step;
+ r6 += -1;
+ cc = r6 < r7;
+ if cc jump 1f;
+.Ldo_single_step:
+#else
/* If we were in user mode, do the single step normally. */
p5.l = lo(IPEND);
p5.h = hi(IPEND);
@@ -166,6 +199,7 @@ ENTRY(_ex_single_step)
r7 = r7 & r6;
cc = r7 == 0;
if !cc jump 1f;
+#endif
/* Single stepping only a single instruction, so clear the trace
* bit here. */
@@ -1388,6 +1422,12 @@ ENTRY(_sys_call_table)
.long _sys_semtimedop
.long _sys_timerfd_settime
.long _sys_timerfd_gettime
+ .long _sys_signalfd4 /* 360 */
+ .long _sys_eventfd2
+ .long _sys_epoll_create1
+ .long _sys_dup3
+ .long _sys_pipe2
+ .long _sys_inotify_init1 /* 365 */
.rept NR_syscalls-(.-_sys_call_table)/4
.long _sys_ni_syscall
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
new file mode 100644
index 000000000000..191b4e974c4b
--- /dev/null
+++ b/arch/blackfin/mach-common/head.S
@@ -0,0 +1,207 @@
+/*
+ * Common Blackfin startup code
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/blackfin.h>
+#include <asm/thread_info.h>
+#include <asm/trace.h>
+
+__INIT
+
+#define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
+
+ENTRY(__start)
+ /* R0: argument of command line string, passed from uboot, save it */
+ R7 = R0;
+ /* Enable Cycle Counter and Nesting Of Interrupts */
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
+ R0 = SYSCFG_SNEN;
+#else
+ R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
+ SYSCFG = R0;
+ R0 = 0;
+
+ /* Clear Out All the data and pointer Registers */
+ R1 = R0;
+ R2 = R0;
+ R3 = R0;
+ R4 = R0;
+ R5 = R0;
+ R6 = R0;
+
+ P0 = R0;
+ P1 = R0;
+ P2 = R0;
+ P3 = R0;
+ P4 = R0;
+ P5 = R0;
+
+ LC0 = r0;
+ LC1 = r0;
+ L0 = r0;
+ L1 = r0;
+ L2 = r0;
+ L3 = r0;
+
+ /* Clear Out All the DAG Registers */
+ B0 = r0;
+ B1 = r0;
+ B2 = r0;
+ B3 = r0;
+
+ I0 = r0;
+ I1 = r0;
+ I2 = r0;
+ I3 = r0;
+
+ M0 = r0;
+ M1 = r0;
+ M2 = r0;
+ M3 = r0;
+
+ trace_buffer_init(p0,r0);
+ P0 = R1;
+ R0 = R1;
+
+ /* Turn off the icache */
+ p0.l = LO(IMEM_CONTROL);
+ p0.h = HI(IMEM_CONTROL);
+ R1 = [p0];
+ R0 = ~ENICPLB;
+ R0 = R0 & R1;
+ [p0] = R0;
+ SSYNC;
+
+ /* Turn off the dcache */
+ p0.l = LO(DMEM_CONTROL);
+ p0.h = HI(DMEM_CONTROL);
+ R1 = [p0];
+ R0 = ~ENDCPLB;
+ R0 = R0 & R1;
+ [p0] = R0;
+ SSYNC;
+
+ /* Save RETX, in case of doublefault */
+ p0.l = ___retx;
+ p0.h = ___retx;
+ R0 = RETX;
+ [P0] = R0;
+
+ /* Initialize stack pointer */
+ sp.l = lo(INITIAL_STACK);
+ sp.h = hi(INITIAL_STACK);
+ fp = sp;
+ usp = sp;
+
+#ifdef CONFIG_EARLY_PRINTK
+ call _init_early_exception_vectors;
+#endif
+
+ /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
+ call _bf53x_relocate_l1_mem;
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
+ call _start_dma_code;
+#endif
+
+ /* This section keeps the processor in supervisor mode
+ * during kernel boot. Switches to user mode at end of boot.
+ * See page 3-9 of Hardware Reference manual for documentation.
+ */
+
+ /* EVT15 = _real_start */
+
+ p0.l = lo(EVT15);
+ p0.h = hi(EVT15);
+ p1.l = _real_start;
+ p1.h = _real_start;
+ [p0] = p1;
+ csync;
+
+ p0.l = lo(IMASK);
+ p0.h = hi(IMASK);
+ p1.l = IMASK_IVG15;
+ p1.h = 0x0;
+ [p0] = p1;
+ csync;
+
+ raise 15;
+ p0.l = .LWAIT_HERE;
+ p0.h = .LWAIT_HERE;
+ reti = p0;
+#if ANOMALY_05000281
+ nop; nop; nop;
+#endif
+ rti;
+
+.LWAIT_HERE:
+ jump .LWAIT_HERE;
+ENDPROC(__start)
+
+/* A little BF561 glue ... */
+#ifndef WDOG_CTL
+# define WDOG_CTL WDOGA_CTL
+#endif
+
+ENTRY(_real_start)
+ /* Enable nested interrupts */
+ [--sp] = reti;
+
+ /* watchdog off for now */
+ p0.l = lo(WDOG_CTL);
+ p0.h = hi(WDOG_CTL);
+ r0 = 0xAD6(z);
+ w[p0] = r0;
+ ssync;
+
+ /* Zero out the bss region
+ * Note: this will fail if bss is 0 bytes ...
+ */
+ r0 = 0 (z);
+ r1.l = ___bss_start;
+ r1.h = ___bss_start;
+ r2.l = ___bss_stop;
+ r2.h = ___bss_stop;
+ r2 = r2 - r1;
+ r2 >>= 2;
+ p1 = r1;
+ p2 = r2;
+ lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
+.L_clear_bss:
+ [p1++] = r0;
+
+ /* In case there is a NULL pointer reference,
+ * zero out region before stext
+ */
+ p1 = r0;
+ r2.l = __stext;
+ r2.h = __stext;
+ r2 >>= 2;
+ p2 = r2;
+ lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
+.L_clear_zero:
+ [p1++] = r0;
+
+ /* Pass the u-boot arguments to the global value command line */
+ R0 = R7;
+ call _cmdline_init;
+
+ /* Load the current thread pointer and stack */
+ sp.l = _init_thread_union;
+ sp.h = _init_thread_union;
+ p1 = THREAD_SIZE (z);
+ sp = sp + p1;
+ usp = sp;
+ fp = sp;
+ jump.l _start_kernel;
+ENDPROC(_real_start)
+
+__FINIT
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 7f752c87fe46..b27e59d32401 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -29,7 +29,7 @@
*/
#include <asm/blackfin.h>
-#include <asm/mach/irq.h>
+#include <mach/irq.h>
#include <linux/linkage.h>
#include <asm/entry.h>
#include <asm/asm-offsets.h>
@@ -37,7 +37,7 @@
#include <asm/traps.h>
#include <asm/thread_info.h>
-#include <asm/mach-common/context.S>
+#include <asm/context.S>
.extern _ret_from_exception
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index f5fd768022ea..5fa536727c61 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -71,6 +71,7 @@ atomic_t num_spurious;
#ifdef CONFIG_PM
unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
+unsigned vr_wakeup;
#endif
struct ivgx {
@@ -184,17 +185,56 @@ static void bfin_internal_unmask_irq(unsigned int irq)
#ifdef CONFIG_PM
int bfin_internal_set_wake(unsigned int irq, unsigned int state)
{
- unsigned bank, bit;
+ unsigned bank, bit, wakeup = 0;
unsigned long flags;
bank = SIC_SYSIRQ(irq) / 32;
bit = SIC_SYSIRQ(irq) % 32;
+ switch (irq) {
+#ifdef IRQ_RTC
+ case IRQ_RTC:
+ wakeup |= WAKE;
+ break;
+#endif
+#ifdef IRQ_CAN0_RX
+ case IRQ_CAN0_RX:
+ wakeup |= CANWE;
+ break;
+#endif
+#ifdef IRQ_CAN1_RX
+ case IRQ_CAN1_RX:
+ wakeup |= CANWE;
+ break;
+#endif
+#ifdef IRQ_USB_INT0
+ case IRQ_USB_INT0:
+ wakeup |= USBWE;
+ break;
+#endif
+#ifdef IRQ_KEY
+ case IRQ_KEY:
+ wakeup |= KPADWE;
+ break;
+#endif
+#ifdef CONFIG_BF54x
+ case IRQ_CNT:
+ wakeup |= ROTWE;
+ break;
+#endif
+ default:
+ break;
+ }
+
local_irq_save(flags);
- if (state)
+ if (state) {
bfin_sic_iwr[bank] |= (1 << bit);
- else
+ vr_wakeup |= wakeup;
+
+ } else {
bfin_sic_iwr[bank] &= ~(1 << bit);
+ vr_wakeup &= ~wakeup;
+ }
local_irq_restore(flags);
@@ -459,6 +499,8 @@ static struct irq_chip bfin_gpio_irqchip = {
.mask = bfin_gpio_mask_irq,
.mask_ack = bfin_gpio_mask_ack_irq,
.unmask = bfin_gpio_unmask_irq,
+ .disable = bfin_gpio_mask_irq,
+ .enable = bfin_gpio_unmask_irq,
.set_type = bfin_gpio_irq_type,
.startup = bfin_gpio_irq_startup,
.shutdown = bfin_gpio_irq_shutdown,
@@ -846,6 +888,8 @@ static struct irq_chip bfin_gpio_irqchip = {
.mask = bfin_gpio_mask_irq,
.mask_ack = bfin_gpio_mask_ack_irq,
.unmask = bfin_gpio_unmask_irq,
+ .disable = bfin_gpio_mask_irq,
+ .enable = bfin_gpio_unmask_irq,
.set_type = bfin_gpio_irq_type,
.startup = bfin_gpio_irq_startup,
.shutdown = bfin_gpio_irq_shutdown,
@@ -939,6 +983,11 @@ int __init init_arch_irq(void)
local_irq_disable();
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+ /* Clear EMAC Interrupt Status bits so we can demux it later */
+ bfin_write_EMAC_SYSTAT(-1);
+#endif
+
#ifdef CONFIG_BF54x
# ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
@@ -1024,13 +1073,22 @@ int __init init_arch_irq(void)
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
- bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
- bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
+#if defined(CONFIG_BF52x)
+ /* BF52x system reset does not properly reset SIC_IWR1 which
+ * will screw up the bootrom as it relies on MDMA0/1 waking it
+ * up from IDLE instructions. See this report for more info:
+ * http://blackfin.uclinux.org/gf/tracker/4323
+ */
+ bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+#else
+ bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
+#endif
# ifdef CONFIG_BF54x
- bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
# endif
#else
- bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR(IWR_DISABLE_ALL);
#endif
return 0;
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S
index 30b887e67dd6..9daf01201e9f 100644
--- a/arch/blackfin/mach-common/lock.S
+++ b/arch/blackfin/mach-common/lock.S
@@ -28,13 +28,10 @@
*/
#include <linux/linkage.h>
-#include <asm/cplb.h>
#include <asm/blackfin.h>
.text
-#ifdef CONFIG_BFIN_ICACHE_LOCK
-
/* When you come here, it is assumed that
* R0 - Which way to be locked
*/
@@ -189,18 +186,38 @@ ENTRY(_cache_lock)
RTS;
ENDPROC(_cache_lock)
-#endif /* BFIN_ICACHE_LOCK */
-
-/* Return the ILOC bits of IMEM_CONTROL
+/* Invalidate the Entire Instruction cache by
+ * disabling IMC bit
*/
+ENTRY(_invalidate_entire_icache)
+ [--SP] = ( R7:5);
-ENTRY(_read_iloc)
- P1.H = HI(IMEM_CONTROL);
- P1.L = LO(IMEM_CONTROL);
- R1 = 0xF;
- R0 = [P1];
- R0 = R0 >> 3;
- R0 = R0 & R1;
+ P0.L = LO(IMEM_CONTROL);
+ P0.H = HI(IMEM_CONTROL);
+ R7 = [P0];
+
+ /* Clear the IMC bit , All valid bits in the instruction
+ * cache are set to the invalid state
+ */
+ BITCLR(R7,IMC_P);
+ CLI R6;
+ SSYNC; /* SSYNC required before invalidating cache. */
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+
+ /* Configures the instruction cache agian */
+ R6 = (IMC | ENICPLB);
+ R7 = R7 | R6;
+
+ CLI R6;
+ SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
+ .align 8;
+ [P0] = R7;
+ SSYNC;
+ STI R6;
+ ( R7:5) = [SP++];
RTS;
-ENDPROC(_read_iloc)
+ENDPROC(_invalidate_entire_icache)
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 0be805ca423f..e28c6af1f415 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -38,8 +38,9 @@
#include <linux/io.h>
#include <linux/irq.h>
-#include <asm/dpmc.h>
#include <asm/gpio.h>
+#include <asm/dma.h>
+#include <asm/dpmc.h>
#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
#define WAKEUP_TYPE PM_WAKE_HIGH
@@ -61,16 +62,17 @@
#define WAKEUP_TYPE PM_WAKE_BOTH_EDGES
#endif
+
void bfin_pm_suspend_standby_enter(void)
{
+ unsigned long flags;
+
#ifdef CONFIG_PM_WAKEUP_BY_GPIO
gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
#endif
- u32 flags;
-
local_irq_save(flags);
- bfin_pm_setup();
+ bfin_pm_standby_setup();
#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
@@ -78,21 +80,203 @@ void bfin_pm_suspend_standby_enter(void)
sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
#endif
- bfin_pm_restore();
+ bfin_pm_standby_restore();
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
- bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
- bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
+#if defined(CONFIG_BF52x)
+ /* BF52x system reset does not properly reset SIC_IWR1 which
+ * will screw up the bootrom as it relies on MDMA0/1 waking it
+ * up from IDLE instructions. See this report for more info:
+ * http://blackfin.uclinux.org/gf/tracker/4323
+ */
+ bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+#else
+ bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
+#endif
# ifdef CONFIG_BF54x
- bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
# endif
#else
- bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+ bfin_write_SIC_IWR(IWR_DISABLE_ALL);
#endif
local_irq_restore(flags);
}
+int bf53x_suspend_l1_mem(unsigned char *memptr)
+{
+ dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
+ dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
+ L1_DATA_A_LENGTH);
+ dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
+ (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
+ memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
+ L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
+ L1_SCRATCH_LENGTH);
+
+ return 0;
+}
+
+int bf53x_resume_l1_mem(unsigned char *memptr)
+{
+ dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
+ dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
+ L1_DATA_A_LENGTH);
+ dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
+ L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
+ memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
+ L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
+
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_WB
+static void flushinv_all_dcache(void)
+{
+ u32 way, bank, subbank, set;
+ u32 status, addr;
+ u32 dmem_ctl = bfin_read_DMEM_CONTROL();
+
+ for (bank = 0; bank < 2; ++bank) {
+ if (!(dmem_ctl & (1 << (DMC1_P - bank))))
+ continue;
+
+ for (way = 0; way < 2; ++way)
+ for (subbank = 0; subbank < 4; ++subbank)
+ for (set = 0; set < 64; ++set) {
+
+ bfin_write_DTEST_COMMAND(
+ way << 26 |
+ bank << 23 |
+ subbank << 16 |
+ set << 5
+ );
+ CSYNC();
+ status = bfin_read_DTEST_DATA0();
+
+ /* only worry about valid/dirty entries */
+ if ((status & 0x3) != 0x3)
+ continue;
+
+ /* construct the address using the tag */
+ addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
+
+ /* flush it */
+ __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
+ }
+ }
+}
+#endif
+
+static inline void dcache_disable(void)
+{
+#ifdef CONFIG_BFIN_DCACHE
+ unsigned long ctrl;
+
+#ifdef CONFIG_BFIN_WB
+ flushinv_all_dcache();
+#endif
+ SSYNC();
+ ctrl = bfin_read_DMEM_CONTROL();
+ ctrl &= ~ENDCPLB;
+ bfin_write_DMEM_CONTROL(ctrl);
+ SSYNC();
+#endif
+}
+
+static inline void dcache_enable(void)
+{
+#ifdef CONFIG_BFIN_DCACHE
+ unsigned long ctrl;
+ SSYNC();
+ ctrl = bfin_read_DMEM_CONTROL();
+ ctrl |= ENDCPLB;
+ bfin_write_DMEM_CONTROL(ctrl);
+ SSYNC();
+#endif
+}
+
+static inline void icache_disable(void)
+{
+#ifdef CONFIG_BFIN_ICACHE
+ unsigned long ctrl;
+ SSYNC();
+ ctrl = bfin_read_IMEM_CONTROL();
+ ctrl &= ~ENICPLB;
+ bfin_write_IMEM_CONTROL(ctrl);
+ SSYNC();
+#endif
+}
+
+static inline void icache_enable(void)
+{
+#ifdef CONFIG_BFIN_ICACHE
+ unsigned long ctrl;
+ SSYNC();
+ ctrl = bfin_read_IMEM_CONTROL();
+ ctrl |= ENICPLB;
+ bfin_write_IMEM_CONTROL(ctrl);
+ SSYNC();
+#endif
+}
+
+int bfin_pm_suspend_mem_enter(void)
+{
+ unsigned long flags;
+ int wakeup, ret;
+
+ unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
+ + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
+ GFP_KERNEL);
+
+ if (memptr == NULL) {
+ panic("bf53x_suspend_l1_mem malloc failed");
+ return -ENOMEM;
+ }
+
+ wakeup = bfin_read_VR_CTL() & ~FREQ;
+ wakeup |= SCKELOW;
+
+#ifdef CONFIG_PM_BFIN_WAKE_PH6
+ wakeup |= PHYWE;
+#endif
+#ifdef CONFIG_PM_BFIN_WAKE_GP
+ wakeup |= GPWE;
+#endif
+
+ local_irq_save(flags);
+
+ ret = blackfin_dma_suspend();
+
+ if (ret) {
+ local_irq_restore(flags);
+ kfree(memptr);
+ return ret;
+ }
+
+ bfin_gpio_pm_hibernate_suspend();
+
+ dcache_disable();
+ icache_disable();
+ bf53x_suspend_l1_mem(memptr);
+
+ do_hibernate(wakeup | vr_wakeup); /* Goodbye */
+
+ bf53x_resume_l1_mem(memptr);
+
+ icache_enable();
+ dcache_enable();
+
+ bfin_gpio_pm_hibernate_restore();
+ blackfin_dma_resume();
+
+ local_irq_restore(flags);
+ kfree(memptr);
+
+ return 0;
+}
+
/*
* bfin_pm_valid - Tell the PM core that we only support the standby sleep
* state
@@ -101,7 +285,24 @@ void bfin_pm_suspend_standby_enter(void)
*/
static int bfin_pm_valid(suspend_state_t state)
{
- return (state == PM_SUSPEND_STANDBY);
+ return (state == PM_SUSPEND_STANDBY
+#ifndef BF533_FAMILY
+ /*
+ * On BF533/2/1:
+ * If we enter Hibernate the SCKE Pin is driven Low,
+ * so that the SDRAM enters Self Refresh Mode.
+ * However when the reset sequence that follows hibernate
+ * state is executed, SCKE is driven High, taking the
+ * SDRAM out of Self Refresh.
+ *
+ * If you reconfigure and access the SDRAM "very quickly",
+ * you are likely to avoid errors, otherwise the SDRAM
+ * start losing its contents.
+ * An external HW workaround is possible using logic gates.
+ */
+ || state == PM_SUSPEND_MEM
+#endif
+ );
}
/*
@@ -115,10 +316,9 @@ static int bfin_pm_enter(suspend_state_t state)
case PM_SUSPEND_STANDBY:
bfin_pm_suspend_standby_enter();
break;
-
case PM_SUSPEND_MEM:
- return -ENOTSUPP;
-
+ bfin_pm_suspend_mem_enter();
+ break;
default:
return -EINVAL;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 13:43:18 +0000