diff options
Diffstat (limited to 'Documentation')
13 files changed, 379 insertions, 227 deletions
diff --git a/Documentation/ABI/testing/debugfs-turris-mox-rwtm b/Documentation/ABI/testing/debugfs-turris-mox-rwtm new file mode 100644 index 000000000000..2b3255ee68fd --- /dev/null +++ b/Documentation/ABI/testing/debugfs-turris-mox-rwtm @@ -0,0 +1,9 @@ +What: /sys/kernel/debug/turris-mox-rwtm/do_sign +Date: Jun 2020 +KernelVersion: 5.8 +Contact: Marek Behún <marek.behun@nic.cz> +Description: (W) Message to sign with the ECDSA private key stored in + device's OTP. The message must be exactly 64 bytes (since + this is intended for SHA-512 hashes). + (R) The resulting signature, 136 bytes. This contains the R and + S values of the ECDSA signature, both in big-endian format. diff --git a/Documentation/ABI/testing/sysfs-bus-optee-devices b/Documentation/ABI/testing/sysfs-bus-optee-devices new file mode 100644 index 000000000000..0f58701367b6 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-optee-devices @@ -0,0 +1,8 @@ +What: /sys/bus/tee/devices/optee-ta-<uuid>/ +Date: May 2020 +KernelVersion 5.8 +Contact: op-tee@lists.trustedfirmware.org +Description: + OP-TEE bus provides reference to registered drivers under this directory. The <uuid> + matches Trusted Application (TA) driver and corresponding TA in secure OS. Drivers + are free to create needed API under optee-ta-<uuid> directory. diff --git a/Documentation/ABI/testing/sysfs-devices-soc b/Documentation/ABI/testing/sysfs-devices-soc index ba3a3fac0ee1..ea999e292f11 100644 --- a/Documentation/ABI/testing/sysfs-devices-soc +++ b/Documentation/ABI/testing/sysfs-devices-soc @@ -26,6 +26,30 @@ Description: Read-only attribute common to all SoCs. Contains SoC family name (e.g. DB8500). + On many of ARM based silicon with SMCCC v1.2+ compliant firmware + this will contain the JEDEC JEP106 manufacturer’s identification + code. The format is "jep106:XXYY" where XX is identity code and + YY is continuation code. + + This manufacturer’s identification code is defined by one + or more eight (8) bit fields, each consisting of seven (7) + data bits plus one (1) odd parity bit. It is a single field, + limiting the possible number of vendors to 126. To expand + the maximum number of identification codes, a continuation + scheme has been defined. + + The specified mechanism is that an identity code of 0x7F + represents the "continuation code" and implies the presence + of an additional identity code field, and this mechanism + may be extended to multiple continuation codes followed + by the manufacturer's identity code. + + For example, ARM has identity code 0x7F 0x7F 0x7F 0x7F 0x3B, + which is code 0x3B on the fifth 'page'. This is shortened + as JEP106 identity code of 0x3B and a continuation code of + 0x4 to represent the four continuation codes preceding the + identity code. + What: /sys/devices/socX/serial_number Date: January 2019 contact: Bjorn Andersson <bjorn.andersson@linaro.org> @@ -40,6 +64,12 @@ Description: Read-only attribute supported by most SoCs. In the case of ST-Ericsson's chips this contains the SoC serial number. + On many of ARM based silicon with SMCCC v1.2+ compliant firmware + this will contain the SOC ID appended to the family attribute + to ensure there is no conflict in this namespace across various + vendors. The format is "jep106:XXYY:ZZZZ" where XX is identity + code, YY is continuation code and ZZZZ is the SOC ID. + What: /sys/devices/socX/revision Date: January 2012 contact: Lee Jones <lee.jones@linaro.org> diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 354b448fc0c3..78456437df5f 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -11,10 +11,12 @@ Required properties: * "qcom,scm-apq8084" * "qcom,scm-ipq4019" * "qcom,scm-ipq806x" + * "qcom,scm-ipq8074" * "qcom,scm-msm8660" * "qcom,scm-msm8916" * "qcom,scm-msm8960" * "qcom,scm-msm8974" + * "qcom,scm-msm8994" * "qcom,scm-msm8996" * "qcom,scm-msm8998" * "qcom,scm-sc7180" diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt index 1a8718f8855d..178fca08278f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt @@ -55,7 +55,7 @@ Required Properties: corresponds to a range of host irqs. For more details on TISCI IRQ resource management refer: -http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html +https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html Example: -------- diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt deleted file mode 100644 index 6ed79e60248a..000000000000 --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt +++ /dev/null @@ -1,49 +0,0 @@ -Freescale i.MX System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "fsl,<chip>-src" -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain SRC interrupt and CPU WDOG interrupt, - in this order. -- #reset-cells: 1, see below - -example: - -src: src@20d8000 { - compatible = "fsl,imx6q-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 0x04 0 96 0x04>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -The system reset controller can be used to reset the GPU, VPU, -IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device -nodes should specify the reset line on the SRC in their resets -property, containing a phandle to the SRC device node and a -RESET_INDEX specifying which module to reset, as described in -reset.txt - -example: - - ipu1: ipu@2400000 { - resets = <&src 2>; - }; - ipu2: ipu@2800000 { - resets = <&src 4>; - }; - -The following RESET_INDEX values are valid for i.MX5: -GPU_RESET 0 -VPU_RESET 1 -IPU1_RESET 2 -OPEN_VG_RESET 3 -The following additional RESET_INDEX value is valid for i.MX6: -IPU2_RESET 4 diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml new file mode 100644 index 000000000000..27c5e34a3ac6 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX System Reset Controller + +maintainers: + - Philipp Zabel <p.zabel@pengutronix.de> + +description: | + The system reset controller can be used to reset the GPU, VPU, + IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device + nodes should specify the reset line on the SRC in their resets + property, containing a phandle to the SRC device node and a + RESET_INDEX specifying which module to reset, as described in + reset.txt + + The following RESET_INDEX values are valid for i.MX5: + GPU_RESET 0 + VPU_RESET 1 + IPU1_RESET 2 + OPEN_VG_RESET 3 + The following additional RESET_INDEX value is valid for i.MX6: + IPU2_RESET 4 + +properties: + compatible: + oneOf: + - const: "fsl,imx51-src" + - items: + - const: "fsl,imx50-src" + - const: "fsl,imx51-src" + - items: + - const: "fsl,imx53-src" + - const: "fsl,imx51-src" + - items: + - const: "fsl,imx6q-src" + - const: "fsl,imx51-src" + - items: + - const: "fsl,imx6sx-src" + - const: "fsl,imx51-src" + - items: + - const: "fsl,imx6sl-src" + - const: "fsl,imx51-src" + - items: + - const: "fsl,imx6ul-src" + - const: "fsl,imx51-src" + - items: + - const: "fsl,imx6sll-src" + - const: "fsl,imx51-src" + + reg: + maxItems: 1 + + interrupts: + items: + - description: SRC interrupt + - description: CPU WDOG interrupts out of SRC + minItems: 1 + maxItems: 2 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#reset-cells' + +additionalProperties: false + +examples: + - | + reset-controller@73fd0000 { + compatible = "fsl,imx51-src"; + reg = <0x73fd0000 0x4000>; + interrupts = <75>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt deleted file mode 100644 index e10502d9153e..000000000000 --- a/Documentation/devicetree/bindings/reset/fsl,imx7-src.txt +++ /dev/null @@ -1,56 +0,0 @@ -Freescale i.MX7 System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: - - For i.MX7 SoCs should be "fsl,imx7d-src", "syscon" - - For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon" - - For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon" - - For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon" - - For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon" -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain SRC interrupt -- #reset-cells: 1, see below - -example: - -src: reset-controller@30390000 { - compatible = "fsl,imx7d-src", "syscon"; - reg = <0x30390000 0x2000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; -}; - - -Specifying reset lines connected to IP modules -============================================== - -The system reset controller can be used to reset various set of -peripherals. Device nodes that need access to reset lines should -specify them as a reset phandle in their corresponding node as -specified in reset.txt. - -Example: - - pcie: pcie@33800000 { - - ... - - resets = <&src IMX7_RESET_PCIEPHY>, - <&src IMX7_RESET_PCIE_CTRL_APPS_EN>; - reset-names = "pciephy", "apps"; - - ... - }; - - -For list of all valid reset indices see -<dt-bindings/reset/imx7-reset.h> for i.MX7, -<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and -<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and -<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and -<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP diff --git a/Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml b/Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml new file mode 100644 index 000000000000..b1a71c1bb05b --- /dev/null +++ b/Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7 System Reset Controller + +maintainers: + - Andrey Smirnov <andrew.smirnov@gmail.com> + +description: | + The system reset controller can be used to reset various set of + peripherals. Device nodes that need access to reset lines should + specify them as a reset phandle in their corresponding node as + specified in reset.txt. + + For list of all valid reset indices see + <dt-bindings/reset/imx7-reset.h> for i.MX7, + <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN, + <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP. + +properties: + compatible: + items: + - enum: + - fsl,imx7d-src + - fsl,imx8mq-src + - fsl,imx8mp-src + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + reset-controller@30390000 { + compatible = "fsl,imx7d-src", "syscon"; + reg = <0x30390000 0x2000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt deleted file mode 100644 index 616fddcd09fd..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt +++ /dev/null @@ -1,62 +0,0 @@ -Qualcomm Resource Power Manager (RPM) over SMD - -This driver is used to interface with the Resource Power Manager (RPM) found in -various Qualcomm platforms. The RPM allows each component in the system to vote -for state of the system resources, such as clocks, regulators and bus -frequencies. - -The SMD information for the RPM edge should be filled out. See qcom,smd.txt for -the required edge properties. All SMD related properties will reside within the -RPM node itself. - -= SUBDEVICES - -The RPM exposes resources to its subnodes. The rpm_requests node must be -present and this subnode may contain children that designate regulator -resources. - -- compatible: - Usage: required - Value type: <string> - Definition: must be one of: - "qcom,rpm-apq8084" - "qcom,rpm-msm8916" - "qcom,rpm-msm8974" - "qcom,rpm-msm8976" - "qcom,rpm-msm8998" - "qcom,rpm-sdm660" - "qcom,rpm-qcs404" - -- qcom,smd-channels: - Usage: required - Value type: <string> - Definition: must be "rpm_requests" - -Refer to Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt -for information on the regulator subnodes that can exist under the rpm_requests. - -Example: - - soc { - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - ... - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml new file mode 100644 index 000000000000..468d658ce3e7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,smd-rpm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Resource Power Manager (RPM) over SMD + +description: | + This driver is used to interface with the Resource Power Manager (RPM) found + in various Qualcomm platforms. The RPM allows each component in the system + to vote for state of the system resources, such as clocks, regulators and bus + frequencies. + + The SMD information for the RPM edge should be filled out. See qcom,smd.txt + for the required edge properties. All SMD related properties will reside + within the RPM node itself. + + The RPM exposes resources to its subnodes. The rpm_requests node must be + present and this subnode may contain children that designate regulator + resources. + + Refer to Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt + for information on the regulator subnodes that can exist under the + rpm_requests. + +maintainers: + - Kathiravan T <kathirav@codeaurora.org> + +properties: + compatible: + enum: + - qcom,rpm-apq8084 + - qcom,rpm-ipq6018 + - qcom,rpm-msm8916 + - qcom,rpm-msm8974 + - qcom,rpm-msm8976 + - qcom,rpm-msm8996 + - qcom,rpm-msm8998 + - qcom,rpm-sdm660 + - qcom,rpm-qcs404 + + qcom,smd-channels: + $ref: /schemas/types.yaml#/definitions/string-array + description: Channel name used for the RPM communication + items: + - const: rpm_requests + +if: + properties: + compatible: + contains: + enum: + - qcom,rpm-apq8084 + - qcom,rpm-msm8916 + - qcom,rpm-msm8974 +then: + required: + - qcom,smd-channels + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-msm8974"; + qcom,smd-channels = "rpm_requests"; + + /* Regulator nodes to follow */ + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt deleted file mode 100644 index 59758ccce809..000000000000 --- a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Texas Instruments K3 NavigatorSS Ring Accelerator - -The Ring Accelerator (RA) is a machine which converts read/write accesses -from/to a constant address into corresponding read/write accesses from/to a -circular data structure in memory. The RA eliminates the need for each DMA -controller which needs to access ring elements from having to know the current -state of the ring (base address, current offset). The DMA controller -performs a read or write access to a specific address range (which maps to the -source interface on the RA) and the RA replaces the address for the transaction -with a new address which corresponds to the head or tail element of the ring -(head for reads, tail for writes). - -The Ring Accelerator is a hardware module that is responsible for accelerating -management of the packet queues. The K3 SoCs can have more than one RA instances - -Required properties: -- compatible : Must be "ti,am654-navss-ringacc"; -- reg : Should contain register location and length of the following - named register regions. -- reg-names : should be - "rt" - The RA Ring Real-time Control/Status Registers - "fifos" - The RA Queues Registers - "proxy_gcfg" - The RA Proxy Global Config Registers - "proxy_target" - The RA Proxy Datapath Registers -- ti,num-rings : Number of rings supported by RA -- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range -- ti,sci : phandle on TI-SCI compatible System controller node -- ti,sci-dev-id : TI-SCI device id of the ring accelerator -- msi-parent : phandle for "ti,sci-inta" interrupt controller - -Optional properties: - -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability - issue software w/a - -Example: - -ringacc: ringacc@3c000000 { - compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", - "proxy_gcfg", "proxy_target"; - ti,num-rings = <818>; - ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ - ti,dma-ring-reset-quirk; - ti,sci = <&dmsc>; - ti,sci-dev-id = <187>; - msi-parent = <&inta_main_udmass>; -}; - -client: - -dma_ipx: dma_ipx@<addr> { - ... - ti,ringacc = <&ringacc>; - ... -} diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml new file mode 100644 index 000000000000..ae33fc957141 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments K3 NavigatorSS Ring Accelerator + +maintainers: + - Santosh Shilimkar <ssantosh@kernel.org> + - Grygorii Strashko <grygorii.strashko@ti.com> + +description: | + The Ring Accelerator (RA) is a machine which converts read/write accesses + from/to a constant address into corresponding read/write accesses from/to a + circular data structure in memory. The RA eliminates the need for each DMA + controller which needs to access ring elements from having to know the current + state of the ring (base address, current offset). The DMA controller + performs a read or write access to a specific address range (which maps to the + source interface on the RA) and the RA replaces the address for the transaction + with a new address which corresponds to the head or tail element of the ring + (head for reads, tail for writes). + + The Ring Accelerator is a hardware module that is responsible for accelerating + management of the packet queues. The K3 SoCs can have more than one RA instances + +properties: + compatible: + items: + - const: ti,am654-navss-ringacc + + reg: + items: + - description: real time registers regions + - description: fifos registers regions + - description: proxy gcfg registers regions + - description: proxy target registers regions + + reg-names: + items: + - const: rt + - const: fifos + - const: proxy_gcfg + - const: proxy_target + + msi-parent: true + + ti,num-rings: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of rings supported by RA + + ti,sci-rm-range-gp-rings: + $ref: /schemas/types.yaml#/definitions/uint32 + description: TI-SCI RM subtype for GP ring range + + ti,sci: + $ref: /schemas/types.yaml#definitions/phandle-array + description: phandle on TI-SCI compatible System controller node + + ti,sci-dev-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: TI-SCI device id of the ring accelerator + + ti,dma-ring-reset-quirk: + $ref: /schemas/types.yaml#definitions/flag + description: | + enable ringacc/udma ring state interoperability issue software w/a + +required: + - compatible + - reg + - reg-names + - msi-parent + - ti,num-rings + - ti,sci-rm-range-gp-rings + - ti,sci + - ti,sci-dev-id + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + ti,num-rings = <818>; + ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <187>; + msi-parent = <&inta_main_udmass>; + }; + }; |