diff options
| -rw-r--r-- | drivers/usb/phy/phy-samsung-usb.h | 36 |
1 files changed, 2 insertions, 34 deletions
diff --git a/drivers/usb/phy/phy-samsung-usb.h b/drivers/usb/phy/phy-samsung-usb.h index 68771bfd1825..4eef45555971 100644 --- a/drivers/usb/phy/phy-samsung-usb.h +++ b/drivers/usb/phy/phy-samsung-usb.h @@ -21,7 +21,6 @@ /* Register definitions */ #define SAMSUNG_PHYPWR (0x00) - #define PHYPWR_NORMAL_MASK (0x19 << 0) #define PHYPWR_OTG_DISABLE (0x1 << 4) #define PHYPWR_ANALOG_POWERDOWN (0x1 << 3) @@ -31,7 +30,6 @@ #define PHYPWR_SLEEP_PHY0 (0x1 << 5) #define SAMSUNG_PHYCLK (0x04) - #define PHYCLK_MODE_USB11 (0x1 << 6) #define PHYCLK_EXT_OSC (0x1 << 5) #define PHYCLK_COMMON_ON_N (0x1 << 4) @@ -42,7 +40,6 @@ #define PHYCLK_CLKSEL_24M (0x3 << 0) #define SAMSUNG_RSTCON (0x08) - #define RSTCON_PHYLINK_SWRST (0x1 << 2) #define RSTCON_HLINK_SWRST (0x1 << 1) #define RSTCON_SWRST (0x1 << 0) @@ -50,26 +47,20 @@ /* EXYNOS4X12 */ #define EXYNOS4X12_PHY_HSIC_CTRL0 (0x04) #define EXYNOS4X12_PHY_HSIC_CTRL1 (0x08) - #define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12) #define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9) #define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6) - #define RSTCON_HOSTPHY_SWRST (0xf << 3) /* EXYNOS5 */ #define EXYNOS5_PHY_HOST_CTRL0 (0x00) - #define HOST_CTRL0_PHYSWRSTALL (0x1 << 31) - #define HOST_CTRL0_REFCLKSEL_MASK (0x3 << 19) #define HOST_CTRL0_REFCLKSEL_XTAL (0x0 << 19) #define HOST_CTRL0_REFCLKSEL_EXTL (0x1 << 19) #define HOST_CTRL0_REFCLKSEL_CLKCORE (0x2 << 19) - #define HOST_CTRL0_FSEL_MASK (0x7 << 16) #define HOST_CTRL0_FSEL(_x) ((_x) << 16) - #define FSEL_CLKSEL_50M (0x7) #define FSEL_CLKSEL_24M (0x5) #define FSEL_CLKSEL_20M (0x4) @@ -77,7 +68,6 @@ #define FSEL_CLKSEL_12M (0x2) #define FSEL_CLKSEL_10M (0x1) #define FSEL_CLKSEL_9600K (0x0) - #define HOST_CTRL0_TESTBURNIN (0x1 << 11) #define HOST_CTRL0_RETENABLE (0x1 << 10) #define HOST_CTRL0_COMMONON_N (0x1 << 9) @@ -98,10 +88,8 @@ #define EXYNOS5_PHY_HSIC_CTRL2 (0x20) #define EXYNOS5_PHY_HSIC_TUNE2 (0x24) - #define HSIC_CTRL_REFCLKSEL_MASK (0x3 << 23) #define HSIC_CTRL_REFCLKSEL (0x2 << 23) - #define HSIC_CTRL_REFCLKDIV_MASK (0x7f << 16) #define HSIC_CTRL_REFCLKDIV(_x) ((_x) << 16) #define HSIC_CTRL_REFCLKDIV_12 (0x24 << 16) @@ -109,7 +97,6 @@ #define HSIC_CTRL_REFCLKDIV_16 (0x1a << 16) #define HSIC_CTRL_REFCLKDIV_19_2 (0x15 << 16) #define HSIC_CTRL_REFCLKDIV_20 (0x14 << 16) - #define HSIC_CTRL_SIDDQ (0x1 << 6) #define HSIC_CTRL_FORCESLEEP (0x1 << 5) #define HSIC_CTRL_FORCESUSPEND (0x1 << 4) @@ -118,36 +105,29 @@ #define HSIC_CTRL_PHYSWRST (0x1 << 0) #define EXYNOS5_PHY_HOST_EHCICTRL (0x30) - #define HOST_EHCICTRL_ENAINCRXALIGN (0x1 << 29) #define HOST_EHCICTRL_ENAINCR4 (0x1 << 28) #define HOST_EHCICTRL_ENAINCR8 (0x1 << 27) #define HOST_EHCICTRL_ENAINCR16 (0x1 << 26) #define EXYNOS5_PHY_HOST_OHCICTRL (0x34) - #define HOST_OHCICTRL_SUSPLGCY (0x1 << 3) #define HOST_OHCICTRL_APPSTARTCLK (0x1 << 2) #define HOST_OHCICTRL_CNTSEL (0x1 << 1) #define HOST_OHCICTRL_CLKCKTRST (0x1 << 0) #define EXYNOS5_PHY_OTG_SYS (0x38) - #define OTG_SYS_PHYLINK_SWRESET (0x1 << 14) #define OTG_SYS_LINKSWRST_UOTG (0x1 << 13) #define OTG_SYS_PHY0_SWRST (0x1 << 12) - #define OTG_SYS_REFCLKSEL_MASK (0x3 << 9) #define OTG_SYS_REFCLKSEL_XTAL (0x0 << 9) #define OTG_SYS_REFCLKSEL_EXTL (0x1 << 9) #define OTG_SYS_REFCLKSEL_CLKCORE (0x2 << 9) - #define OTG_SYS_IDPULLUP_UOTG (0x1 << 8) #define OTG_SYS_COMMON_ON (0x1 << 7) - #define OTG_SYS_FSEL_MASK (0x7 << 4) #define OTG_SYS_FSEL(_x) ((_x) << 4) - #define OTG_SYS_FORCESLEEP (0x1 << 3) #define OTG_SYS_OTGDISABLE (0x1 << 2) #define OTG_SYS_SIDDQ_UOTG (0x1 << 1) @@ -157,13 +137,11 @@ /* EXYNOS5: USB 3.0 DRD */ #define EXYNOS5_DRD_LINKSYSTEM (0x04) - #define LINKSYSTEM_FLADJ_MASK (0x3f << 1) #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) #define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) #define EXYNOS5_DRD_PHYUTMI (0x08) - #define PHYUTMI_OTGDISABLE (0x1 << 6) #define PHYUTMI_FORCESUSPEND (0x1 << 1) #define PHYUTMI_FORCESLEEP (0x1 << 0) @@ -171,68 +149,58 @@ #define EXYNOS5_DRD_PHYPIPE (0x0c) #define EXYNOS5_DRD_PHYCLKRST (0x10) - #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) - #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) - #define PHYCLKRST_SSC_EN (0x1 << 20) #define PHYCLKRST_REF_SSP_EN (0x1 << 19) #define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) - #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) - #define PHYCLKRST_FSEL_MASK (0x3f << 5) #define PHYCLKRST_FSEL(_x) ((_x) << 5) #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) - #define PHYCLKRST_RETENABLEN (0x1 << 4) - #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) - #define PHYCLKRST_PORTRESET (0x1 << 1) #define PHYCLKRST_COMMONONN (0x1 << 0) #define EXYNOS5_DRD_PHYREG0 (0x14) + #define EXYNOS5_DRD_PHYREG1 (0x18) #define EXYNOS5_DRD_PHYPARAM0 (0x1c) - #define PHYPARAM0_REF_USE_PAD (0x1 << 31) #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) #define EXYNOS5_DRD_PHYPARAM1 (0x20) - #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) #define PHYPARAM1_PCS_TXDEEMPH (0x1c) #define EXYNOS5_DRD_PHYTERM (0x24) #define EXYNOS5_DRD_PHYTEST (0x28) - #define PHYTEST_POWERDOWN_SSP (0x1 << 3) #define PHYTEST_POWERDOWN_HSP (0x1 << 2) #define EXYNOS5_DRD_PHYADP (0x2c) #define EXYNOS5_DRD_PHYBATCHG (0x30) - #define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) #define EXYNOS5_DRD_PHYRESUME (0x34) + #define EXYNOS5_DRD_LINKPORT (0x44) #ifndef MHZ |