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authorDavid S. Miller <davem@davemloft.net>2012-09-06 20:35:36 -0700
committerDavid S. Miller <davem@davemloft.net>2012-09-06 20:35:36 -0700
commitc69ad0a3f7d871aa61fb669fb41c951df6660a61 (patch)
tree4dee9eab4894c9103f617be916359724172c240c /tools
parentce33fdc52ad50043eef07d11473bc51e225565bd (diff)
sparc64: Use cpu_pgsz_mask for linear kernel mapping config.
This required a little bit of reordering of how we set up the memory management early on. We now only know the final values of kern_linear_pte_xor[] after we take over the trap table and start processing TLB misses ourselves. So once we fill those values in we re-clear the kernel's 4M TSB and flush the TLBs. That way if we find we support larger than 4M pages we won't have any stale smaller page size entries in the TSB. SUN4U Panther support for larger page sizes should now be extremely trivial but I have no hardware on which to test it and I believe that some of the sun4u TLB miss assembler needs to be audited first to make sure it really can handle larger than 4M PTEs properly. Signed-off-by: David S. Miller <davem@davemloft.net>
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