diff options
| author | Lubomir Rintel <lkundrak@v3.sk> | 2020-05-11 23:01:34 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-05-19 20:52:49 +0100 |
| commit | a97e384ba78fd8bf7ba8c32718424d8a7536416e (patch) | |
| tree | 17a048ef526c1c4524b5393716924a784beb4103 /sound/soc/pxa/mmp-sspa.h | |
| parent | ce5955866d971864a6cd8d012411ec96b048a696 (diff) | |
ASoC: mmp-sspa: Add Device Tree support
This makes it possible to select CONFIG_SND_MMP_SOC_SSPA directly, as
opposed to via CONFIG_SND_MMP_SOC, and for the driver to bind to a device
tree node. That makes the driver useful on Device Tree based systems,
with audio-graph-card or simple-card.
The aforementioned card drivers control the master clock themselves and
don't call the set_dai_sysclk() or set_dai_pll(), thus the respective
handlers don't serve any purpose anymore. Instead, they return early and
the hw_params() handler sets the appropriate bitclk itself.
The register range is split into two -- for the RX block and for the TX
block. On a MMP2 there are two pairs of them; the first one has the
clock controller in the middle, while the second just has a hole:
0xd42a0c00 - 0xd42a0c30 RX1
0xd42a0c30 - 0xd42a0c40 Clocks
0xd42a0c80 - 0xd42a0cb0 TX1
0xd42a0d00 - 0xd42a0d30 RX2
0xd42a0d80 - 0xd42a0cb0 TX2
For this reason, mmp_sspa_write_reg() and mmp_sspa_read_reg() are
replaced with direct calls to I/O routines.
Tested on a MMP2-based OLPC XO-1.75 laptop with rt5631 coded, mmp_tdma DMA
engine and MMP2 clock controller glued together with audio-graph-card.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lore.kernel.org/r/20200511210134.1224532-12-lkundrak@v3.sk
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/pxa/mmp-sspa.h')
| -rw-r--r-- | sound/soc/pxa/mmp-sspa.h | 28 |
1 files changed, 9 insertions, 19 deletions
diff --git a/sound/soc/pxa/mmp-sspa.h b/sound/soc/pxa/mmp-sspa.h index 328969b57ad1..938ef2f667e3 100644 --- a/sound/soc/pxa/mmp-sspa.h +++ b/sound/soc/pxa/mmp-sspa.h @@ -10,25 +10,15 @@ /* * SSPA Registers */ -#define SSPA_RXD (0x00) -#define SSPA_RXID (0x04) -#define SSPA_RXCTL (0x08) -#define SSPA_RXSP (0x0c) -#define SSPA_RXFIFO_UL (0x10) -#define SSPA_RXINT_MASK (0x14) -#define SSPA_RXC (0x18) -#define SSPA_RXFIFO_NOFS (0x1c) -#define SSPA_RXFIFO_SIZE (0x20) - -#define SSPA_TXD (0x80) -#define SSPA_TXID (0x84) -#define SSPA_TXCTL (0x88) -#define SSPA_TXSP (0x8c) -#define SSPA_TXFIFO_LL (0x90) -#define SSPA_TXINT_MASK (0x94) -#define SSPA_TXC (0x98) -#define SSPA_TXFIFO_NOFS (0x9c) -#define SSPA_TXFIFO_SIZE (0xa0) +#define SSPA_D (0x00) +#define SSPA_ID (0x04) +#define SSPA_CTL (0x08) +#define SSPA_SP (0x0c) +#define SSPA_FIFO_UL (0x10) +#define SSPA_INT_MASK (0x14) +#define SSPA_C (0x18) +#define SSPA_FIFO_NOFS (0x1c) +#define SSPA_FIFO_SIZE (0x20) /* SSPA Control Register */ #define SSPA_CTL_XPH (1 << 31) /* Read Phase */ |