diff options
| author | Jie Yang <yang.jie@intel.com> | 2015-01-08 20:12:52 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-01-08 18:18:27 +0000 |
| commit | 69067f9d52aa325baa0d113c1f35eb98fe486bfc (patch) | |
| tree | d3be7faca0eacd3d12125027c4f08ddfac3569ff /sound/soc/intel | |
| parent | eb55fab997c0bf1b1ddf0a7199da0ceb18432b96 (diff) | |
ASoC: Intel: Always enable DRAM block for FW dump
The first 512 bytes of data DRAM memory is used for FW dump,
and this first data SRAM block should be never power gated
(always on), here always enable the block(DSRAM[0]) for D0
stage.
Signed-off-by: Jie Yang <yang.jie@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel')
| -rw-r--r-- | sound/soc/intel/sst-haswell-dsp.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/sound/soc/intel/sst-haswell-dsp.c b/sound/soc/intel/sst-haswell-dsp.c index 57039b00efc2..c42ffae5fe9f 100644 --- a/sound/soc/intel/sst-haswell-dsp.c +++ b/sound/soc/intel/sst-haswell-dsp.c @@ -306,7 +306,7 @@ static void hsw_reset(struct sst_dsp *sst) static int hsw_set_dsp_D0(struct sst_dsp *sst) { int tries = 10; - u32 reg; + u32 reg, fw_dump_bit; /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); @@ -368,7 +368,9 @@ finish: can't be accessed, please enable each block before accessing. */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK; - writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); + /* for D0, always enable the block(DSRAM[0]) used for FW dump */ + fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT; + writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0); /* disable DMA finish function for SSP0 & SSP1 */ @@ -491,6 +493,7 @@ static const struct sst_sram_shift sram_shift[] = { {SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */ {SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */ }; + static u32 hsw_block_get_bit(struct sst_mem_block *block) { u32 bit = 0, shift = 0, index; @@ -587,7 +590,9 @@ static int hsw_block_disable(struct sst_mem_block *block) val = readl(sst->addr.pci_cfg + SST_VDRTCTL0); bit = hsw_block_get_bit(block); - writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0); + /* don't disable DSRAM[0], keep it always enable for FW dump*/ + if (bit != (1 << SST_VDRTCL0_DSRAMPGE_SHIFT)) + writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0); /* wait 18 DSP clock ticks */ udelay(10); @@ -612,7 +617,7 @@ static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata) const struct sst_adsp_memregion *region; struct device *dev; int ret = -ENODEV, i, j, region_count; - u32 offset, size; + u32 offset, size, fw_dump_bit; dev = sst->dma_dev; @@ -669,9 +674,11 @@ static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata) } } + /* always enable the block(DSRAM[0]) used for FW dump */ + fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT; /* set default power gating control, enable power gating control for all blocks. that is, can't be accessed, please enable each block before accessing. */ - writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0); + writel(0xffffffff & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0); return 0; } |