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| author | Alex Deucher <alexander.deucher@amd.com> | 2012-08-22 09:54:56 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2012-08-29 12:11:01 -0400 |
| commit | 8d1af57ae3c4458ed0de93ef97f388dd1b3239c7 (patch) | |
| tree | d0c091c27dfa52065449301f0f11a03c15e47f1c /scripts/sortextable.c | |
| parent | 4e58591c8961b3e31709313f75819f2eec06e322 (diff) | |
drm/radeon/atom: rework DIG modesetting on DCE3+
The ordering is important and the current drm code
wasn't cutting it for modern DIG encoders. We need
to have information about crtc before setting up
the encoders so I've shifted the ordering a bit.
Probably we'll need a full rework akin to danvet's
recent intel patchs. This patch fixes numerous
issues with DP bridge chips and makes link training
much more reliable.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'scripts/sortextable.c')
0 files changed, 0 insertions, 0 deletions