kbuild: split final module linking out into Makefile.modfinal

I think splitting the modpost and linking modules into separate
Makefiles will be useful especially when more complex build steps
come in. The main motivation of this commit is to integrate the
proposed klp-convert feature cleanly.

I moved the logging 'Building modules, stage 2.' to Makefile.modpost
to avoid the code duplication although I do not know whether or not
this message is needed in the first place.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 11 insertions, 68 deletions

diff --git a/scripts/Makefile.modpost b/scripts/Makefile.modpost
index 905db30d6622..9800a3988f23 100644
--- a/scripts/Makefile.modpost
+++ b/scripts/Makefile.modpost
@@ -15,8 +15,6 @@
 # 2) modpost is then used to
 # 3)  create one <module>.mod.c file pr. module
 # 4)  create one Module.symvers file with CRC for all exported symbols
-# 5) compile all <module>.mod.c files
-# 6) final link of the module to a <module.ko> file
 
 # Step 3 is used to place certain information in the module's ELF
 # section, including information such as:
@@ -60,13 +58,10 @@ MODPOST = scripts/mod/modpost						\
 
 ifdef MODPOST_VMLINUX
 
-__modpost: vmlinux.o
+quiet_cmd_modpost = MODPOST vmlinux.o
+      cmd_modpost = $(MODPOST) vmlinux.o
 
-quiet_cmd_modpost = MODPOST $@
-      cmd_modpost = $(MODPOST) $@
-
-PHONY += vmlinux.o
-vmlinux.o:
+__modpost:
 	$(call cmd,modpost)
 
 else
@@ -83,74 +78,22 @@ include $(if $(wildcard $(KBUILD_EXTMOD)/Kbuild), \
              $(KBUILD_EXTMOD)/Kbuild, $(KBUILD_EXTMOD)/Makefile)
 endif
 
-include scripts/Makefile.lib
+MODPOST += $(subst -i,-n,$(filter -i,$(MAKEFLAGS))) -s -T - $(wildcard vmlinux)
 
 # find all modules listed in modules.order
 modules := $(sort $(shell cat $(MODORDER)))
 
-# Stop after building .o files if NOFINAL is set. Makes compile tests quicker
-__modpost: $(if $(KBUILD_MODPOST_NOFINAL), $(modules:.ko:.o),$(modules))
-	@:
-
-MODPOST += $(subst -i,-n,$(filter -i,$(MAKEFLAGS))) -s -T - $(wildcard vmlinux)
-
-# We can go over command line length here, so be careful.
+# Read out modules.order instead of expanding $(modules) to pass in modpost.
+# Otherwise, allmodconfig would fail with "Argument list too long".
 quiet_cmd_modpost = MODPOST $(words $(modules)) modules
       cmd_modpost = sed 's/ko$$/o/' $(MODORDER) | $(MODPOST)
 
-PHONY += modules-modpost
-modules-modpost:
+__modpost:
+	@$(kecho) '  Building modules, stage 2.'
 	$(call cmd,modpost)
-
-# Declare generated files as targets for modpost
-$(modules:.ko=.mod.c): modules-modpost
-
-# Step 5), compile all *.mod.c files
-
-# modname is set to make c_flags define KBUILD_MODNAME
-modname = $(notdir $(@:.mod.o=))
-
-quiet_cmd_cc_o_c = CC [M]  $@
-      cmd_cc_o_c = $(CC) $(c_flags) $(KBUILD_CFLAGS_MODULE) $(CFLAGS_MODULE) \
-		   -c -o $@ $<
-
-$(modules:.ko=.mod.o): %.mod.o: %.mod.c FORCE
-	$(call if_changed_dep,cc_o_c)
-
-targets += $(modules:.ko=.mod.o)
-
-ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(SRCARCH)/Makefile.postlink)
-
-# Step 6), final link of the modules with optional arch pass after final link
-quiet_cmd_ld_ko_o = LD [M]  $@
-      cmd_ld_ko_o =                                                     \
-	$(LD) -r $(KBUILD_LDFLAGS)                                      \
-                 $(KBUILD_LDFLAGS_MODULE) $(LDFLAGS_MODULE)             \
-                 $(addprefix -T , $(KBUILD_LDS_MODULE))                 \
-                 -o $@ $(filter %.o, $^);                               \
-	$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
-
-$(modules): %.ko :%.o %.mod.o $(KBUILD_LDS_MODULE) FORCE
-	+$(call if_changed,ld_ko_o)
-
-targets += $(modules)
-
-
-# Add FORCE to the prequisites of a target to force it to be always rebuilt.
-# ---------------------------------------------------------------------------
-
-PHONY += FORCE
-
-FORCE:
-
-# Read all saved command lines and dependencies for the $(targets) we
-# may be building above, using $(if_changed{,_dep}). As an
-# optimization, we don't need to read them if the target does not
-# exist, we will rebuild anyway in that case.
-
-existing-targets := $(wildcard $(sort $(targets)))
-
--include $(foreach f,$(existing-targets),$(dir $(f)).$(notdir $(f)).cmd)
+ifneq ($(KBUILD_MODPOST_NOFINAL),1)
+	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modfinal
+endif
 
 endif