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authorNicholas Piggin <npiggin@gmail.com>2016-10-13 14:43:52 +1100
committerMichael Ellerman <mpe@ellerman.id.au>2016-11-14 11:11:51 +1100
commitf4329f2ecb149282fdfdd8830a936a56b1497a05 (patch)
tree437623c6fe2f44a63a62e754fb423b84bd62967a /net/ipv4/ip_input.c
parentfda0440d82d38e603cd713e997fdfedb97e0ef0c (diff)
powerpc/64s: Reduce exception alignment
Exception handlers are aligned to 128 bytes (L1 cache) on 64s, which is overkill. It can reduce the icache footprint of any individual exception path. However taken as a whole, the expansion in icache footprint seems likely to be counter-productive and cause more total misses. Create IFETCH_ALIGN_SHIFT/BYTES, which should give optimal ifetch alignment with much more reasonable alignment. This saves 1792 bytes from head_64.o text with an allmodconfig build. Other subarchitectures should define appropriate IFETCH_ALIGN_SHIFT values if this becomes more widely used. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'net/ipv4/ip_input.c')
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