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| author | Arnd Bergmann <arnd@arndb.de> | 2020-03-25 21:05:21 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2020-03-25 21:05:22 +0100 |
| commit | d0d593464a94a7b82d14c7a6cf8b26fae0ac7dd8 (patch) | |
| tree | f4447ffa363176c43cd04eac29bd13c5ea13ca8e /net/caif/Makefile | |
| parent | ec18b456be46f5ddc9e9c1750fa1ea03f4f3920c (diff) | |
| parent | 1a1a9fafc6a2536835b38886ca4afe50d19dd2b9 (diff) | |
Merge tag 'zynq-soc-for-v5.7' of https://github.com/Xilinx/linux-xlnx into arm/soc
ARM: Xilinx Zynq SoC patches for v5.7
- Use proper clock header in soc code
* tag 'zynq-soc-for-v5.7' of https://github.com/Xilinx/linux-xlnx:
ARM: zynq: Replace <linux/clk-provider.h> by <linux/of_clk.h>
Link: https://lore.kernel.org/r/005af9f0-85b5-7bac-2d99-5bb3857debb3@monstr.eu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'net/caif/Makefile')
0 files changed, 0 insertions, 0 deletions