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authorKan Liang <kan.liang@linux.intel.com>2019-10-08 08:50:10 -0700
committerIngo Molnar <mingo@kernel.org>2019-10-12 15:13:09 +0200
commit52e92f409dede388b7dc3ee13491fbf7a80db935 (patch)
tree9180e415dd7b31cb5634ab977ee77d3f4da6e258 /kernel
parent0917b95079af82c69d8f5bab301faeebcd2cb3cd (diff)
perf/x86/cstate: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. From the perspective of Intel cstate residency counters, there is nothing changed compared with Ice Lake. Share icl_cstates with Ice Lake. Update the comments for Tiger Lake. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/1570549810-25049-10-git-send-email-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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