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authorFelix Fietkau <nbd@openwrt.org>2011-05-19 12:20:25 +0200
committerJohn W. Linville <linville@tuxdriver.com>2011-06-01 15:11:00 -0400
commitfce041beb03f93c7a771f0b4b6c45bb71ef90901 (patch)
tree7946e026ba6e82dd944ce956c9865b06e58d3030 /init
parente62ddec94a1e11ab1043b607e20ae0d142069132 (diff)
ath9k: unify edma and non-edma tx code, improve tx fifo handling
EDMA based chips (AR9380+) have 8 Tx FIFO slots, which are used to fix the tx queue start/stop race conditions which have to be worked around for earlier chips by keeping the last descriptor in the queue. The current code stores all frames that do not fit onto the 8 FIFO slots in a separate list. Whenever a FIFO slot is freed up, the next frame (or A-MPDU) from the pending queue gets moved to that slot. This process is not only inefficient, but also unnecessary. The code can be improved visibly by keeping the pending queue fully linked, and moving the contents of the entire queue to a FIFO slot as it becomes available. This patch makes the necessary changes for that and also merges some code that was duplicated for EDMA vs non-EDMA. It changes txq->axq_link to point to the last descriptor instead of the link pointer, so that ath9k_hw_set_desc_link can be used, which works on all chips. With this patch, a small performance increase for non-aggregated traffic was observed on AR9380 based embedded hardware. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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