diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2019-10-09 16:07:51 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2019-10-15 16:39:10 -0500 |
| commit | e5adf79a1d8086aefa56f48eeb08f8fe4e054a3d (patch) | |
| tree | f053b77ce7824bd10bd5f99127159eb81663b5b8 /include | |
| parent | 751035b8dc061ae434c3311bac9cd6d0e5e00f94 (diff) | |
PCI/ATS: Cache PRI PRG Response PASID Required bit
The PRG Response PASID Required bit in the PRI Capability is read-only.
Read it once when we enumerate the device and cache the value so we don't
need to read it again.
Based-on-patch-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/pci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index 6542100bd2dd..64d35e730fab 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -456,6 +456,7 @@ struct pci_dev { #ifdef CONFIG_PCI_PRI u16 pri_cap; /* PRI Capability offset */ u32 pri_reqs_alloc; /* Number of PRI requests allocated */ + unsigned int pasid_required:1; /* PRG Response PASID Required */ #endif #ifdef CONFIG_PCI_PASID u16 pasid_cap; /* PASID Capability offset */ |