diff options
| author | Andi Kleen <ak@suse.de> | 2005-04-16 15:25:05 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:25:05 -0700 |
| commit | c29601e9c1e7893d1755364e350c9188bd56d69f (patch) | |
| tree | 14813ddce4d8897b40cc8b3a2f76ace3ac58b36f /include | |
| parent | dc37db4d8cb376bb67c6357c50d707ced3d71c39 (diff) | |
[PATCH] x86_64: Support constantly ticking TSCs
On Intel Noconas the TSC ticks with a constant frequency. Don't scale the
factor used by udelay when cpufreq changes the frequency.
This generalizes an earlier patch by Intel for this.
Cc: <venkatesh.pallipadi@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-x86_64/cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h index 0e47a6d53726..e68ad97a6319 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86_64/cpufeature.h @@ -62,6 +62,7 @@ #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ #define X86_FEATURE_K8_C (3*32+ 4) /* C stepping K8 */ +#define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */ /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |