diff options
| author | Patil, Rachna <rachna@ti.com> | 2013-07-20 17:27:00 +0100 |
|---|---|---|
| committer | Jonathan Cameron <jic23@kernel.org> | 2013-07-21 18:27:35 +0100 |
| commit | b1451e546899bc8f450773b2af02e0cd000cf1fa (patch) | |
| tree | b4147d4c31a3572c0c6c427fcd1ae8dfc7401c6c /include | |
| parent | a1a8e1dc111d6f05e7164e851e58219d428359e1 (diff) | |
iio: ti_am335x_adc: Fix wrong samples received on 1st read
Previously we tried to read data form ADC even before ADC sequencer
finished sampling. This led to wrong samples.
We now wait on ADC status register idle bit to be set.
Signed-off-by: Patil, Rachna <rachna@ti.com>
Signed-off-by: Zubair Lutfullah <zubair.lutfullah@gmail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mfd/ti_am335x_tscadc.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h index 8d73fe29796a..db1791bb997a 100644 --- a/include/linux/mfd/ti_am335x_tscadc.h +++ b/include/linux/mfd/ti_am335x_tscadc.h @@ -113,11 +113,27 @@ #define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3) #define CNTRLREG_TSCENB BIT(7) +/* FIFO READ Register */ +#define FIFOREAD_DATA_MASK (0xfff << 0) +#define FIFOREAD_CHNLID_MASK (0xf << 16) + +/* Sequencer Status */ +#define SEQ_STATUS BIT(5) + #define ADC_CLK 3000000 #define MAX_CLK_DIV 7 #define TOTAL_STEPS 16 #define TOTAL_CHANNELS 8 +/* +* ADC runs at 3MHz, and it takes +* 15 cycles to latch one data output. +* Hence the idle time for ADC to +* process one sample data would be +* around 5 micro seconds. +*/ +#define IDLE_TIMEOUT 5 /* microsec */ + #define TSCADC_CELLS 2 struct ti_tscadc_dev { |