diff options
| author | Peter Griffin <peter.griffin@linaro.org> | 2014-06-16 11:23:00 +0200 |
|---|---|---|
| committer | Maxime Coquelin <maxime.coquelin@st.com> | 2014-06-17 16:55:17 +0200 |
| commit | 9796853e902447e53a17dae5df9eb609f0e31e6a (patch) | |
| tree | 66aa57d3740335c1c70f637707eaba00116dd9a1 /include | |
| parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) | |
ARM: STi: DT: Properly define sti-ethclk & stmmaceth for stih415/6
This patch fixes two problems: -
1) The device tree isn't currently providing sti-ethclk which is
required by the dwmac glue code to correctly configure the ethernet
PHY clock speed.
This means depending on what the bootloader/jtag has
configured this clock to, and what switch/hub the board is plugged
into you most likely will NOT successfully negotiate a ethernet link.
2) The stmmaceth clock was associated with the wrong clock. It was
referencing the PHY clock rather than the interconnect clock which
clocks the IP.
This patch also brings us closer to not having to boot the upstream
kernel with the clk_ignore_unused parameter.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/stih415-clks.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/stih416-clks.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/stih415-clks.h b/include/dt-bindings/clock/stih415-clks.h index 0d2c7397e028..d80caa68aebd 100644 --- a/include/dt-bindings/clock/stih415-clks.h +++ b/include/dt-bindings/clock/stih415-clks.h @@ -10,6 +10,7 @@ #define CLK_ETH1_PHY 4 /* CLOCKGEN A1 */ +#define CLK_ICN_IF_2 0 #define CLK_GMAC0_PHY 3 #endif diff --git a/include/dt-bindings/clock/stih416-clks.h b/include/dt-bindings/clock/stih416-clks.h index 552c779eb6af..f9bdbd13568d 100644 --- a/include/dt-bindings/clock/stih416-clks.h +++ b/include/dt-bindings/clock/stih416-clks.h @@ -10,6 +10,7 @@ #define CLK_ETH1_PHY 4 /* CLOCKGEN A1 */ +#define CLK_ICN_IF_2 0 #define CLK_GMAC0_PHY 3 #endif |