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authorEric Yang <Eric.Yang2@amd.com>2019-11-15 12:04:25 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-12-05 18:23:04 -0500
commit44ce6c3dc8479bb3ed68df13b502b0901675e7d6 (patch)
tree45979ce66d0ea9908ce127875dd62ff3e61d781b /include
parentdd0b162fd00915728860a360c97752988782b8cc (diff)
drm/amd/display: update dispclk and dppclk vco frequency
Value obtained from DV is not allowing 8k60 CTA mode with DSC to pass, after checking real value being used in hw, find out that correct value is 3600, which will allow that mode. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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