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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2019-01-07 13:07:37 +0200
committerVinod Koul <vkoul@kernel.org>2019-01-07 17:57:13 +0530
commit078165779608873e7b6eae1316a39c73af9f3edc (patch)
tree0b98eb26219af322982feee99a031fbb5440697d /include
parentd7dba6be0f31ae61f5f3296aa130f45d57d30f74 (diff)
dmaengine: dw: Remove unused internal property
All known devices, which use DT for configuration, support memory-to-memory transfers. So enable it by default. The rest two cases, i.e. Intel Quark and PPC460ex, instantiate DMA driver and use its channels exclusively for hardware, which means there is no available channel for any other purposes anyway. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include')
-rw-r--r--include/linux/platform_data/dma-dw.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index d443025c5c72..1c85eeee4171 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -38,7 +38,6 @@ struct dw_dma_slave {
/**
* struct dw_dma_platform_data - Controller configuration parameters
* @nr_channels: Number of channels supported by hardware (max 8)
- * @is_memcpy: The device channels do support memory-to-memory transfers.
* @is_idma32: The type of the DMA controller is iDMA32
* @chan_allocation_order: Allocate channels starting from 0 or 7
* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
@@ -51,7 +50,6 @@ struct dw_dma_slave {
*/
struct dw_dma_platform_data {
unsigned int nr_channels;
- bool is_memcpy;
bool is_idma32;
#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */