diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-08-14 12:28:15 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-08-14 12:28:15 -0700 |
| commit | 97c24d1d455df17ca3ef281d1a290988f4686643 (patch) | |
| tree | 36e4602be13301bf1669fcb7998b8a2d431cf1c9 /include/linux | |
| parent | 91d85ea6786107aa2837bef3e957165ad7c8b823 (diff) | |
| parent | 7fd781e8f9b72544a1c7f04456eb33d5ffaed592 (diff) | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc:
mmc: remove unused "ddr" parameter in struct mmc_ios
mmc: dw_mmc: Fix DDR mode support.
mmc: core: use defined R1_STATE_PRG macro for card status
mmc: sdhci: use f_max instead of host->clock for timeouts
mmc: sdhci: move timeout_clk calculation farther down
mmc: sdhci: check host->clock before using it as a denominator
mmc: Revert "mmc: sdhci: Fix SDHCI_QUIRK_TIMEOUT_USES_SDCLK"
mmc: tmio: eliminate unused variable 'mmc' warning
mmc: esdhc-imx: fix card interrupt loss on freescale eSDHC
mmc: sdhci-s3c: Fix build for header change
mmc: dw_mmc: Fix mask in IDMAC_SET_BUFFER1_SIZE macro
mmc: cb710: fix possible pci_dev leak in cb710_pci_configure()
mmc: core: Detect eMMC v4.5 ext_csd entries
mmc: mmc_test: avoid stalled file in debugfs
mmc: sdhci-s3c: add BROKEN_ADMA_ZEROLEN_DESC quirk
mmc: sdhci: pxav3: controller needs 32 bit ADMA addressing
mmc: sdhci: fix retuning timer wrongly deleted in sdhci_tasklet_finish
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mmc/host.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 0f83858147a6..1d09562ccf73 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -56,8 +56,6 @@ struct mmc_ios { #define MMC_TIMING_UHS_SDR104 4 #define MMC_TIMING_UHS_DDR50 5 - unsigned char ddr; /* dual data rate used */ - #define MMC_SDR_MODE 0 #define MMC_1_2V_DDR_MODE 1 #define MMC_1_8V_DDR_MODE 2 |