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authorTudor Ambarus <tudor.ambarus@microchip.com>2019-11-07 08:42:01 +0000
committerTudor Ambarus <tudor.ambarus@microchip.com>2019-11-11 08:56:37 +0200
commitbb2dc7f46ad897ba1c2d8ae773c77601ba240932 (patch)
treeed1ae10cccda1b961f4b40edfb684af5e82a77ff /include/linux/mtd/spi-nor.h
parent4da11da15a7cc56432a92ee47748c95cf29dbe3d (diff)
mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1
JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'include/linux/mtd/spi-nor.h')
-rw-r--r--include/linux/mtd/spi-nor.h4
1 files changed, 1 insertions, 3 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 11daecc5a83d..364309845de0 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -144,10 +144,8 @@
#define FSR_P_ERR BIT(4) /* Program operation status */
#define FSR_PT_ERR BIT(1) /* Protection error bit */
-/* Configuration Register bits. */
-#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
-
/* Status Register 2 bits. */
+#define SR2_QUAD_EN_BIT1 BIT(1)
#define SR2_QUAD_EN_BIT7 BIT(7)
/* Supported SPI protocols */