diff options
| author | Andrew Bresticker <abrestic@chromium.org> | 2015-06-18 17:28:40 -0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:44 +0200 |
| commit | 3358d2d9f47af86bdd71edb24b361f72a54ec04e (patch) | |
| tree | 3ae890b9c2ef525ff6177eb8a2ee154142829719 /include/linux/clk | |
| parent | f55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff) | |
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence. Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/linux/clk')
| -rw-r--r-- | include/linux/clk/tegra.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index 57bf7aab4516..7007a5f48080 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h @@ -121,4 +121,9 @@ static inline void tegra_cpu_clock_resume(void) } #endif +extern void tegra210_xusb_pll_hw_control_enable(void); +extern void tegra210_xusb_pll_hw_sequence_start(void); +extern void tegra210_sata_pll_hw_control_enable(void); +extern void tegra210_sata_pll_hw_sequence_start(void); + #endif /* __LINUX_CLK_TEGRA_H_ */ |