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authorTaniya Das <tdas@codeaurora.org>2018-06-23 19:49:26 +0530
committerStephen Boyd <sboyd@kernel.org>2018-07-06 16:46:22 -0700
commit6c79d12e945e85556674a04cde13657a5d7943da (patch)
treebc407ffc3267b7a81f2e2bc802c8c3e6d71114ea /include/dt-bindings
parentda172d2b6ba8c98101b9c18a986758662a91adbb (diff)
dt-bindings: clock: Introduce QCOM Display clock bindings
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/qcom,dispcc-sdm845.h45
1 files changed, 45 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
new file mode 100644
index 000000000000..11eed4bc9646
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK 0
+#define DISP_CC_MDSS_AXI_CLK 1
+#define DISP_CC_MDSS_BYTE0_CLK 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 4
+#define DISP_CC_MDSS_BYTE1_CLK 5
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 6
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 7
+#define DISP_CC_MDSS_ESC0_CLK 8
+#define DISP_CC_MDSS_ESC0_CLK_SRC 9
+#define DISP_CC_MDSS_ESC1_CLK 10
+#define DISP_CC_MDSS_ESC1_CLK_SRC 11
+#define DISP_CC_MDSS_MDP_CLK 12
+#define DISP_CC_MDSS_MDP_CLK_SRC 13
+#define DISP_CC_MDSS_MDP_LUT_CLK 14
+#define DISP_CC_MDSS_PCLK0_CLK 15
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
+#define DISP_CC_MDSS_PCLK1_CLK 17
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 18
+#define DISP_CC_MDSS_ROT_CLK 19
+#define DISP_CC_MDSS_ROT_CLK_SRC 20
+#define DISP_CC_MDSS_RSCC_AHB_CLK 21
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22
+#define DISP_CC_MDSS_VSYNC_CLK 23
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
+#define DISP_CC_PLL0 25
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
+
+/* DISP_CC Reset */
+#define DISP_CC_MDSS_RSCC_BCR 0
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+
+#endif