diff options
| author | Biju Das <biju.das@bp.renesas.com> | 2019-09-05 07:52:06 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-10-01 09:49:40 +0200 |
| commit | be67c41781cb4c06a4acb0b92db0cbb728e955e2 (patch) | |
| tree | 21ec82672ccdebf4ab2e423bf3d8480d04109df8 /include/dt-bindings/power | |
| parent | 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff) | |
dt-bindings: power: Add r8a774b1 SYSC power domain definitions
This patch adds power domain indices for the RZ/G2N (a.k.a r8a774b1)
SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1567666326-27373-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/dt-bindings/power')
| -rw-r--r-- | include/dt-bindings/power/r8a774b1-sysc.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h new file mode 100644 index 000000000000..373736402f04 --- /dev/null +++ b/include/dt-bindings/power/r8a774b1-sysc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774B1_PD_CA57_CPU0 0 +#define R8A774B1_PD_CA57_CPU1 1 +#define R8A774B1_PD_A3VP 9 +#define R8A774B1_PD_CA57_SCU 12 +#define R8A774B1_PD_A3VC 14 +#define R8A774B1_PD_3DG_A 17 +#define R8A774B1_PD_3DG_B 18 +#define R8A774B1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774B1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */ |