diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2018-12-14 10:04:16 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-02-05 13:27:56 -0800 |
| commit | c3424f59a0cb994a098c3701bf14617580a18290 (patch) | |
| tree | 0802022eb21952dd6851b70389b213ed222261d7 /include/dt-bindings/clock | |
| parent | bfeffd155283772bbe78c6a05dec7c0128ee500c (diff) | |
dt-bindings: clock: add clock for MT2712
Add new clock according to 3rd ECO design change.
It's the parent clock of audio clock mux.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/mt2712-clk.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h index 76265836a1e1..c3b29dff9c0e 100644 --- a/include/dt-bindings/clock/mt2712-clk.h +++ b/include/dt-bindings/clock/mt2712-clk.h @@ -228,7 +228,8 @@ #define CLK_TOP_NFI2X_EN 189 #define CLK_TOP_NFIECC_EN 190 #define CLK_TOP_NFI1X_CK_EN 191 -#define CLK_TOP_NR_CLK 192 +#define CLK_TOP_APLL2_D3 192 +#define CLK_TOP_NR_CLK 193 /* INFRACFG */ |