diff options
| author | Alim Akhtar <alim.akhtar@samsung.com> | 2015-09-10 14:14:34 +0530 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-09-15 11:16:09 +0200 |
| commit | a259a61be1d0d01aa2dd4778722e4d161780c813 (patch) | |
| tree | cf30590cb9eb7c06a3b3ae56717e9ae2be6b0fde /include/dt-bindings/clock | |
| parent | 6ce0f5cf11a1165675a1eef8a17b8738fea3f9da (diff) | |
clk: samsung: exynos7: Correct CMU_FSYS0 clocks names
This patch renames CMU_FSYS0 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys0_200.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/exynos7-clk.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 287665451a89..667faed474ce 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -62,7 +62,8 @@ #define CLK_SCLK_MMC2 6 #define CLK_SCLK_MMC1 7 #define CLK_SCLK_MMC0 8 -#define TOP1_NR_CLK 9 +#define CLK_ACLK_FSYS0_200 9 +#define TOP1_NR_CLK 10 /* CCORE */ #define PCLK_RTC 1 |