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authorMichael Turquette <mturquette@baylibre.com>2016-05-23 15:44:26 -0700
committerMichael Turquette <mturquette@baylibre.com>2016-06-22 18:07:31 -0700
commit738f66d3211d7ae0cd0012ba6457dac9a03bfd6b (patch)
tree555daf5390d4f71e13faa433eb94544dd2811312 /include/dt-bindings/clock
parent2cc9e7ec219819db10474160d65837c6c260522a (diff)
clk: gxbb: add AmLogic GXBB clk controller driver
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
new file mode 100644
index 000000000000..f889d80246cb
--- /dev/null
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -0,0 +1,12 @@
+/*
+ * GXBB clock tree IDs
+ */
+
+#ifndef __GXBB_CLKC_H
+#define __GXBB_CLKC_H
+
+#define CLKID_CPUCLK 1
+#define CLKID_CLK81 12
+#define CLKID_ETH 36
+
+#endif /* __GXBB_CLKC_H */