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| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2017-02-23 12:44:38 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-03-20 14:04:27 +0100 |
| commit | 9326947f2215e1816a9133b0b47e4c9200552777 (patch) | |
| tree | e2aebbe96a3976767a69c22346b0a6315cf3a58a /include/dt-bindings/clock/tegra210-car.h | |
| parent | c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201 (diff) | |
clk: tegra: Fix pll_a1 iddq register, add pll_a1
pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add
pll_a1 to the set of clocks defined for Tegra210.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings/clock/tegra210-car.h')
0 files changed, 0 insertions, 0 deletions