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authorNaveen Krishna Ch <naveenkrishna.ch@gmail.com>2014-10-21 11:13:51 +0530
committerSylwester Nawrocki <s.nawrocki@samsung.com>2014-10-31 10:45:51 +0100
commit57a2b485fa512be47b479077b5f89e1bfe536709 (patch)
tree3be9142227263189fcf6c53304e5f4491b3f7c0e /include/dt-bindings/clock/exynos7-clk.h
parent532abc3a4a4502e13315d246c545d7567c80b03e (diff)
clk: samsung: exynos7: add clocks for I2C block
Exynos7 supports 12 I2C channels, add the I2C gate clocks to support them. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings/clock/exynos7-clk.h')
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h16
1 files changed, 14 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 00fd6de1cb25..6d07b6f1d615 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,14 @@
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
-#define PERIC0_NR_CLK 3
+#define PCLK_HSI2C0 3
+#define PCLK_HSI2C1 4
+#define PCLK_HSI2C4 5
+#define PCLK_HSI2C5 6
+#define PCLK_HSI2C9 7
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PERIC0_NR_CLK 10
/* PERIC1 */
#define PCLK_UART1 1
@@ -39,7 +46,12 @@
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
-#define PERIC1_NR_CLK 7
+#define PCLK_HSI2C2 7
+#define PCLK_HSI2C3 8
+#define PCLK_HSI2C6 9
+#define PCLK_HSI2C7 10
+#define PCLK_HSI2C8 11
+#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID 1