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authorTomeu Vizoso <tomeu.vizoso@collabora.com>2015-10-15 12:31:23 +0200
committerKukjin Kim <kgene@kernel.org>2015-10-24 04:31:18 +0900
commitb4dc272b60fd7b43ff5b9ef89714d38c65db2cdb (patch)
treeb764e97729c81e63a659b970ac8966c98479b7d9 /include/dt-bindings/clock/exynos5250.h
parentb29dd5fa56141365ab7e72fd73e5e0e02d62dd6e (diff)
clk: samsung: exynos5250: Add DISP1 clocks
When the DISP1 power domain is powered off, there's two clocks that need to be temporarily reparented to OSC, and back to their original parents when the domain is powered on again. We expose these two clocks in the DT bindings so that the DT node of the power domain can reference them. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'include/dt-bindings/clock/exynos5250.h')
-rw-r--r--include/dt-bindings/clock/exynos5250.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 8183d1c237d9..15508adcdfde 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -173,8 +173,10 @@
/* mux clocks */
#define CLK_MOUT_HDMI 1024
#define CLK_MOUT_GPLL 1025
+#define CLK_MOUT_ACLK200_DISP1_SUB 1026
+#define CLK_MOUT_ACLK300_DISP1_SUB 1027
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 1026
+#define CLK_NR_CLKS 1028
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */