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authorBiju Das <biju.das@bp.renesas.com>2018-09-11 11:12:48 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2018-09-19 16:37:56 +0200
commit6ff9cb53dabca55952ef66853ff145f7c424f6bd (patch)
tree4cadf484b3add36ef9e36e17e663fbaca70cbb0a /include/dt-bindings/clock/bcm-cygnus.h
parentbbd71915ee9c56cc585c76b4b3aee791152ffbff (diff)
clk: renesas: Add r8a7744 CPG Core Clock Definitions
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's Manual. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/dt-bindings/clock/bcm-cygnus.h')
0 files changed, 0 insertions, 0 deletions