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authorGiulio Benetti <giulio.benetti@micronovasrl.com>2018-02-15 18:54:48 +0100
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-02-16 21:16:03 +0100
commitfa4127c5eb8def998fd8a471d51a4f2560dea0a2 (patch)
treee463a25d2caa1c25a2576205f50c4c5848b8ba51 /include/drm
parentcd0e93d865538decfd0f917c112d3fc57aac90fe (diff)
drm/sun4i: fix HSYNC and VSYNC polarity
Differently from other Lcd signals, HSYNC and VSYNC signals result inverted if their bits are cleared to 0. Invert their settings of IO_POL register. Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/1518717288-123578-1-git-send-email-giulio.benetti@micronovasrl.com
Diffstat (limited to 'include/drm')
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