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authorLinus Torvalds <torvalds@g5.osdl.org>2006-05-31 16:48:05 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2006-05-31 16:48:05 -0700
commitba8f5baba79da8eb502f8534c3a8ecb64aceb790 (patch)
tree39a0438607446681bdf5173c7480ff90f3825945 /include/asm-mips/cpu.h
parent5cedae9ca752a43cfb1074907d12c9f01fbebd45 (diff)
parent44d921b246923380f26b8010e47ac5dfe48fcec5 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Treat R14000 like R10000. [MIPS] Remove EXPERIMENTAL from PAGE_SIZE_16KB [MIPS] Update/Fix instruction definitions [MIPS] DSP and MDMX share the same config flag bit. [MIPS] Fix deadlock on MP with cache aliases. [MIPS] Use generic STABS_DEBUG macro. [MIPS] Create consistency in "system type" selection. [MIPS] Use generic DWARF_DEBUG [MIPS] Fix kgdb exception handler from user mode. [MIPS] Update struct sigcontext member names [MIPS] Update/fix futex assembly [MIPS] Remove support for sysmips(2) SETNAME and MIPS_RDNVRAM operations. [MIPS] Fix detection and handling of the 74K processor. [MIPS] Add missing 34K processor IDs [MIPS] Fix marking buddy of pte global for MIPS32 w/36-bit physical address [MIPS] AU1xxx mips_timer_interrupt() fixes [MIPS] Fix typo
Diffstat (limited to 'include/asm-mips/cpu.h')
-rw-r--r--include/asm-mips/cpu.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 818b9a97e214..dff2a0a52f8f 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -51,6 +51,7 @@
#define PRID_IMP_R4300 0x0b00
#define PRID_IMP_VR41XX 0x0c00
#define PRID_IMP_R12000 0x0e00
+#define PRID_IMP_R14000 0x0f00
#define PRID_IMP_R8000 0x1000
#define PRID_IMP_PR4450 0x1200
#define PRID_IMP_R4600 0x2000
@@ -87,6 +88,7 @@
#define PRID_IMP_24K 0x9300
#define PRID_IMP_34K 0x9500
#define PRID_IMP_24KE 0x9600
+#define PRID_IMP_74K 0x9700
/*
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -196,7 +198,9 @@
#define CPU_34K 60
#define CPU_PR4450 61
#define CPU_SB1A 62
-#define CPU_LAST 62
+#define CPU_74K 63
+#define CPU_R14000 64
+#define CPU_LAST 64
/*
* ISA Level encodings