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authorJoseph Gravenor <joseph.gravenor@amd.com>2019-11-08 14:30:34 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-12-05 18:17:02 -0500
commit10bce710fa6feb13ec270d5420aad3b81f6bf7ea (patch)
tree76c2a133b24f501ba3e7f536914f9f3d7f473ffd /fs/jfs
parenta51d9f8fe756beac51ce26ef54195da00a260d13 (diff)
drm/amd/display: have two different sr and pstate latency tables for renoir
[Why] new sr and pstate latencies are optimized for the case when we are not using lpddr4 memory [How] have two different wm tables, one for the lpddr case and one for non lpddr case Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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