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authorThierry Reding <treding@nvidia.com>2019-12-09 13:00:04 +0100
committerBen Skeggs <bskeggs@redhat.com>2020-01-15 10:49:59 +1000
commit0d0d498265e7cb3329d2a7185b1d7cfb3be95d65 (patch)
tree6c7b57f1c2c9e2424fe05157686d58c5917fb573 /fs/gfs2/recovery.c
parent6992ceb8c0f6f8e2f4374a1ab4dd84cd76cc4b64 (diff)
drm/nouveau/ltc/gp10b: Add custom L2 cache implementation
There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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