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authorDavid Woodhouse <David.Woodhouse@intel.com>2015-10-24 21:06:39 +0200
committerDavid Woodhouse <David.Woodhouse@intel.com>2015-10-24 21:06:39 +0200
commit5a10ba27d963bc79d6ac2e4996cdbb012195c306 (patch)
treea7d84b59269fb4b9497533080a5c9f3adda8a2f8 /firmware/kaweth
parent5d52f482ebb7d0845e84cb235700061bc5682ada (diff)
iommu/vt-d: Handle Caching Mode implementations of SVM
Not entirely clear why, but it seems we need to reserve PASID zero and flush it when we make a PASID entry present. Quite we we couldn't use the true PASID value, isn't clear. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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