diff options
| author | Brad Love <brad@nextdimension.cc> | 2018-05-08 17:20:20 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-05-11 11:29:53 -0400 |
| commit | ff9d1c0143e2eaf48f8e560aaa396751ef5c3358 (patch) | |
| tree | 0171b9cdf9925f96ef5d13b9fa44ac7c777c2540 /drivers | |
| parent | f72ff638e66616aa6e776f2e1ecb23f85ac9e121 (diff) | |
media: cx23885: Add some missing register documentation
Document what these two register calls are doing.
Signed-off-by: Brad Love <brad@nextdimension.cc>
Signed-off-by: Hans Verkuil <hansverk@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/media/pci/cx23885/cx23885-core.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/media/pci/cx23885/cx23885-core.c b/drivers/media/pci/cx23885/cx23885-core.c index 11a1dcee69f3..94b996ff12a9 100644 --- a/drivers/media/pci/cx23885/cx23885-core.c +++ b/drivers/media/pci/cx23885/cx23885-core.c @@ -1464,8 +1464,15 @@ int cx23885_start_dma(struct cx23885_tsport *port, reg = reg | 0xa; cx_write(PAD_CTRL, reg); - /* FIXME and these two registers should be documented. */ + /* Sets MOE_CLK_DIS to disable MoE clock */ + /* sets MCLK_DLY_SEL/BCLK_DLY_SEL to 1 buffer delay each */ cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011); + + /* ALT_GPIO_ALT_SET: GPIO[0] + * IR_ALT_TX_SEL: GPIO[1] + * GPIO1_ALT_SEL: VIP_656_DATA[0] + * GPIO0_ALT_SEL: VIP_656_CLK + */ cx_write(ALT_PIN_OUT_SEL, 0x10100045); } |